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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id t9sm1607367otq.65.2020.01.15.06.56.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:56:46 -0800 (PST) Received: from rob (uid 1000) (envelope-from rob@rob-hp-laptop) id 22040c by rob-hp-laptop (DragonFly Mail Agent v0.11); Wed, 15 Jan 2020 08:56:45 -0600 Date: Wed, 15 Jan 2020 08:56:45 -0600 From: Rob Herring To: Ludovic Barre Cc: Ulf Hansson , srinivas.kandagatla@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc Message-ID: <20200115145645.GA599@bogus> References: <20200110134823.14882-1-ludovic.barre@st.com> <20200110134823.14882-6-ludovic.barre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200110134823.14882-6-ludovic.barre@st.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote: > To support the sdr104 mode, the sdmmc variant has a > hardware delay block to manage the clock phase when sampling > data received by the card. > > This patch adds a second base register (optional) for > sdmmc delay block. > > Signed-off-by: Ludovic Barre > --- > Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt > index 6d3c626e017d..4ec921e4bf34 100644 > --- a/Documentation/devicetree/bindings/mmc/mmci.txt > +++ b/Documentation/devicetree/bindings/mmc/mmci.txt > @@ -28,6 +28,8 @@ specific for ux500 variant: > - st,sig-pin-fbclk : feedback clock signal pin used. > > specific for sdmmc variant: > +- reg : a second base register may be defined if a delay > + block is present and used for tuning. Which compatibles have a 2nd reg entry? > - st,sig-dir : signal direction polarity used for cmd, dat0 dat123. > - st,neg-edge : data & command phase relation, generated on > sd clock falling edge. > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E80DBC33CB1 for ; Wed, 15 Jan 2020 14:56:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A84022465A for ; Wed, 15 Jan 2020 14:56:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Wfcq6sjW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A84022465A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ErbK1QCEbn8g6/Ru5j2aSkYVcgk1U9f6BljbQc5hgFw=; b=Wfcq6sjWUimvSi qw7NYaq80anY2aQOny5bX2TrnbDFe4+6P+YJtRdxSSkQqHyLEhx9nmMlIWVrQrhtS4oWSagMbdpCr lh8lcq+3CA+fVWs6jQX3/HiIVOwW0HWG+ma/6gQRxF3L75IpIFjlCtQEkbChSFtrv5FoUIACfrjhn 50dOnn9GL1WpcRPryFl+nGneEcoPxtklcFL1DwlZlzlCvSWSuj0uO6u+LsmkM1t9c7GeXVBQX9NXp SEGzR6yRtL4ZjBVLhx2xUT9/SLdwjpTqueTkvbI7v4DzftGZOAxViGZ7cZp2i49nZcmLO2YkyZ3f5 4kQV0Jh25+L8B22dhvoA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1irk6J-0004Av-S2; Wed, 15 Jan 2020 14:56:55 +0000 Received: from mail-oi1-f194.google.com ([209.85.167.194]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1irk6D-00049W-Jp for linux-arm-kernel@lists.infradead.org; Wed, 15 Jan 2020 14:56:54 +0000 Received: by mail-oi1-f194.google.com with SMTP id n16so15589506oie.12 for ; Wed, 15 Jan 2020 06:56:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=9gnxD+G4FNn+U8wzPNZLFG38GLzn+JUvySqC1BxpFAA=; b=gYlHxAvJ1WaQX99Y4PJvhYpoa8FfsVzeLE6Xb+RGXXwYDZ50GNTVPWCLFC66sRTqqr bVRRR1depCnII5FkBo6Bk8eu5lf+8TAHvRhODpFmGSzrHe4Gdwek9I/uT6ZMYpoXw1ya V3OLdxoo/3ZkNq/qW/S18JU6lGH+Cuk7uyX9UgQAWCyd5h6V5jEkRTTSVzHUhALtF54J Uagmr5pxdEWNYjdifI5fjQi87Az8WaIYKlOMkMu1UpMIcSIms0M59RBbhVtfxakVbNPJ rRSqf0o4mZ6HeFINXGKWq4y5mvl5S01OgncjtDulzN61Okzs7oyxamcx2cvgfI9XJtnT iPWQ== X-Gm-Message-State: APjAAAVqBJBrjx4l6gXoRfuouryRQhxQnVAQk5WbD1bIjCswa/6OHF4m KIWvbVfwXNSnBmPjbmBv5TXW1bI= X-Google-Smtp-Source: APXvYqxahidKY5uPySbt6WXe/S0K6vDCHzN8zDDOc4DEbU6nokdVSDoPpH3cLa0ULVPNTtid5IgulA== X-Received: by 2002:aca:3857:: with SMTP id f84mr100858oia.150.1579100207637; Wed, 15 Jan 2020 06:56:47 -0800 (PST) Received: from rob-hp-laptop (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id 6sm5697290oil.43.2020.01.15.06.56.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:56:46 -0800 (PST) Received: from rob (uid 1000) (envelope-from rob@rob-hp-laptop) id 22040c by rob-hp-laptop (DragonFly Mail Agent v0.11); Wed, 15 Jan 2020 08:56:45 -0600 Date: Wed, 15 Jan 2020 08:56:45 -0600 From: Rob Herring To: Ludovic Barre Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc Message-ID: <20200115145645.GA599@bogus> References: <20200110134823.14882-1-ludovic.barre@st.com> <20200110134823.14882-6-ludovic.barre@st.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200110134823.14882-6-ludovic.barre@st.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200115_065649_652295_978F5E6A X-CRM114-Status: GOOD ( 16.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Alexandre Torgue , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote: > To support the sdr104 mode, the sdmmc variant has a > hardware delay block to manage the clock phase when sampling > data received by the card. > > This patch adds a second base register (optional) for > sdmmc delay block. > > Signed-off-by: Ludovic Barre > --- > Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt > index 6d3c626e017d..4ec921e4bf34 100644 > --- a/Documentation/devicetree/bindings/mmc/mmci.txt > +++ b/Documentation/devicetree/bindings/mmc/mmci.txt > @@ -28,6 +28,8 @@ specific for ux500 variant: > - st,sig-pin-fbclk : feedback clock signal pin used. > > specific for sdmmc variant: > +- reg : a second base register may be defined if a delay > + block is present and used for tuning. Which compatibles have a 2nd reg entry? > - st,sig-dir : signal direction polarity used for cmd, dat0 dat123. > - st,neg-edge : data & command phase relation, generated on > sd clock falling edge. > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel