From: Josh Poimboeuf <jpoimboe@redhat.com>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, Tony Luck <tony.luck@intel.com>,
Michal Hocko <mhocko@suse.com>,
linux-kernel@vger.kernel.org,
Neelima Krishnan <neelima.krishnan@intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH] x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR
Date: Thu, 16 Jan 2020 08:38:22 -0600 [thread overview]
Message-ID: <20200116143822.ffunlqsboxkvsv4x@treble> (raw)
In-Reply-To: <2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com>
On Fri, Jan 10, 2020 at 02:50:54PM -0800, Pawan Gupta wrote:
> /proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to
> be present on boot cpu even if it was disabled during the bootup. This
> is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX
> state is changed via a new MSR IA32_TSX_CTRL.
>
> Update the cached HLE bit also since it is expected to change after an
> update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL.
>
> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
--
Josh
prev parent reply other threads:[~2020-01-16 14:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 22:50 [PATCH] x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR Pawan Gupta
2020-01-15 21:15 ` Josh Poimboeuf
2020-01-15 21:49 ` Luck, Tony
2020-01-15 21:52 ` Andi Kleen
2020-01-16 14:38 ` Josh Poimboeuf [this message]
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