From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UPPERCASE_50_75,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD2D9C33CAF for ; Thu, 16 Jan 2020 21:12:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 937E620728 for ; Thu, 16 Jan 2020 21:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388316AbgAPVMD (ORCPT ); Thu, 16 Jan 2020 16:12:03 -0500 Received: from mga07.intel.com ([134.134.136.100]:15982 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726527AbgAPVMD (ORCPT ); Thu, 16 Jan 2020 16:12:03 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jan 2020 13:12:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,327,1574150400"; d="scan'208";a="398419874" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga005.jf.intel.com with ESMTP; 16 Jan 2020 13:12:00 -0800 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1isCQr-00040S-7K; Thu, 16 Jan 2020 23:12:01 +0200 Date: Thu, 16 Jan 2020 23:12:01 +0200 From: Andy Shevchenko To: Mika Westerberg Cc: Linus Walleij , linux-gpio@vger.kernel.org Subject: Re: [PATCH] pinctrl: tigerlake: Tiger Lake uses _HID enumeration Message-ID: <20200116211201.GN32742@smile.fi.intel.com> References: <20200116110902.31523-1-mika.westerberg@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200116110902.31523-1-mika.westerberg@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Thu, Jan 16, 2020 at 02:09:02PM +0300, Mika Westerberg wrote: > Turns out that Tiger Lake GPIO will be enumerated using _HID method where > there is only a single ACPI device and multiple BARs so rework the driver > to support that scheme instead. > Pushed to my review and testing queue, thank! P.S. Will be promoted soon to for-next > Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support") > Signed-off-by: Mika Westerberg > --- > drivers/pinctrl/intel/pinctrl-tigerlake.c | 547 ++++++++++------------ > 1 file changed, 250 insertions(+), 297 deletions(-) > > diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c > index 58572b15b3ce..08a86f6fdea6 100644 > --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c > +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c > @@ -2,7 +2,7 @@ > /* > * Intel Tiger Lake PCH pinctrl/GPIO driver > * > - * Copyright (C) 2019, Intel Corporation > + * Copyright (C) 2019 - 2020, Intel Corporation > * Authors: Andy Shevchenko > * Mika Westerberg > */ > @@ -21,15 +21,19 @@ > #define TGL_GPI_IS 0x100 > #define TGL_GPI_IE 0x120 > > -#define TGL_GPP(r, s, e) \ > +#define TGL_NO_GPIO -1 > + > +#define TGL_GPP(r, s, e, g) \ > { \ > .reg_num = (r), \ > .base = (s), \ > .size = ((e) - (s) + 1), \ > + .gpio_base = (g), \ > } > > -#define TGL_COMMUNITY(s, e, g) \ > +#define TGL_COMMUNITY(b, s, e, g) \ > { \ > + .barno = (b), \ > .padown_offset = TGL_PAD_OWN, \ > .padcfglock_offset = TGL_PADCFGLOCK, \ > .hostown_offset = TGL_HOSTSW_OWN, \ > @@ -42,7 +46,7 @@ > } > > /* Tiger Lake-LP */ > -static const struct pinctrl_pin_desc tgllp_community0_pins[] = { > +static const struct pinctrl_pin_desc tgllp_pins[] = { > /* GPP_B */ > PINCTRL_PIN(0, "CORE_VID_0"), > PINCTRL_PIN(1, "CORE_VID_1"), > @@ -113,324 +117,273 @@ static const struct pinctrl_pin_desc tgllp_community0_pins[] = { > PINCTRL_PIN(64, "GPPC_A_22"), > PINCTRL_PIN(65, "I2S1_SCLK"), > PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), > -}; > - > -static const struct intel_padgroup tgllp_community0_gpps[] = { > - TGL_GPP(0, 0, 25), /* GPP_B */ > - TGL_GPP(1, 26, 41), /* GPP_T */ > - TGL_GPP(2, 42, 66), /* GPP_A */ > -}; > - > -static const struct intel_community tgllp_community0[] = { > - TGL_COMMUNITY(0, 66, tgllp_community0_gpps), > -}; > - > -static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = { > - .uid = "0", > - .pins = tgllp_community0_pins, > - .npins = ARRAY_SIZE(tgllp_community0_pins), > - .communities = tgllp_community0, > - .ncommunities = ARRAY_SIZE(tgllp_community0), > -}; > - > -static const struct pinctrl_pin_desc tgllp_community1_pins[] = { > /* GPP_S */ > - PINCTRL_PIN(0, "SNDW0_CLK"), > - PINCTRL_PIN(1, "SNDW0_DATA"), > - PINCTRL_PIN(2, "SNDW1_CLK"), > - PINCTRL_PIN(3, "SNDW1_DATA"), > - PINCTRL_PIN(4, "SNDW2_CLK"), > - PINCTRL_PIN(5, "SNDW2_DATA"), > - PINCTRL_PIN(6, "SNDW3_CLK"), > - PINCTRL_PIN(7, "SNDW3_DATA"), > + PINCTRL_PIN(67, "SNDW0_CLK"), > + PINCTRL_PIN(68, "SNDW0_DATA"), > + PINCTRL_PIN(69, "SNDW1_CLK"), > + PINCTRL_PIN(70, "SNDW1_DATA"), > + PINCTRL_PIN(71, "SNDW2_CLK"), > + PINCTRL_PIN(72, "SNDW2_DATA"), > + PINCTRL_PIN(73, "SNDW3_CLK"), > + PINCTRL_PIN(74, "SNDW3_DATA"), > /* GPP_H */ > - PINCTRL_PIN(8, "GPPC_H_0"), > - PINCTRL_PIN(9, "GPPC_H_1"), > - PINCTRL_PIN(10, "GPPC_H_2"), > - PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"), > - PINCTRL_PIN(12, "I2C2_SDA"), > - PINCTRL_PIN(13, "I2C2_SCL"), > - PINCTRL_PIN(14, "I2C3_SDA"), > - PINCTRL_PIN(15, "I2C3_SCL"), > - PINCTRL_PIN(16, "I2C4_SDA"), > - PINCTRL_PIN(17, "I2C4_SCL"), > - PINCTRL_PIN(18, "SRCCLKREQB_4"), > - PINCTRL_PIN(19, "SRCCLKREQB_5"), > - PINCTRL_PIN(20, "M2_SKT2_CFG_0"), > - PINCTRL_PIN(21, "M2_SKT2_CFG_1"), > - PINCTRL_PIN(22, "M2_SKT2_CFG_2"), > - PINCTRL_PIN(23, "M2_SKT2_CFG_3"), > - PINCTRL_PIN(24, "DDPB_CTRLCLK"), > - PINCTRL_PIN(25, "DDPB_CTRLDATA"), > - PINCTRL_PIN(26, "CPU_C10_GATEB"), > - PINCTRL_PIN(27, "TIME_SYNC_0"), > - PINCTRL_PIN(28, "IMGCLKOUT_1"), > - PINCTRL_PIN(29, "IMGCLKOUT_2"), > - PINCTRL_PIN(30, "IMGCLKOUT_3"), > - PINCTRL_PIN(31, "IMGCLKOUT_4"), > + PINCTRL_PIN(75, "GPPC_H_0"), > + PINCTRL_PIN(76, "GPPC_H_1"), > + PINCTRL_PIN(77, "GPPC_H_2"), > + PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), > + PINCTRL_PIN(79, "I2C2_SDA"), > + PINCTRL_PIN(80, "I2C2_SCL"), > + PINCTRL_PIN(81, "I2C3_SDA"), > + PINCTRL_PIN(82, "I2C3_SCL"), > + PINCTRL_PIN(83, "I2C4_SDA"), > + PINCTRL_PIN(84, "I2C4_SCL"), > + PINCTRL_PIN(85, "SRCCLKREQB_4"), > + PINCTRL_PIN(86, "SRCCLKREQB_5"), > + PINCTRL_PIN(87, "M2_SKT2_CFG_0"), > + PINCTRL_PIN(88, "M2_SKT2_CFG_1"), > + PINCTRL_PIN(89, "M2_SKT2_CFG_2"), > + PINCTRL_PIN(90, "M2_SKT2_CFG_3"), > + PINCTRL_PIN(91, "DDPB_CTRLCLK"), > + PINCTRL_PIN(92, "DDPB_CTRLDATA"), > + PINCTRL_PIN(93, "CPU_C10_GATEB"), > + PINCTRL_PIN(94, "TIME_SYNC_0"), > + PINCTRL_PIN(95, "IMGCLKOUT_1"), > + PINCTRL_PIN(96, "IMGCLKOUT_2"), > + PINCTRL_PIN(97, "IMGCLKOUT_3"), > + PINCTRL_PIN(98, "IMGCLKOUT_4"), > /* GPP_D */ > - PINCTRL_PIN(32, "ISH_GP_0"), > - PINCTRL_PIN(33, "ISH_GP_1"), > - PINCTRL_PIN(34, "ISH_GP_2"), > - PINCTRL_PIN(35, "ISH_GP_3"), > - PINCTRL_PIN(36, "IMGCLKOUT_0"), > - PINCTRL_PIN(37, "SRCCLKREQB_0"), > - PINCTRL_PIN(38, "SRCCLKREQB_1"), > - PINCTRL_PIN(39, "SRCCLKREQB_2"), > - PINCTRL_PIN(40, "SRCCLKREQB_3"), > - PINCTRL_PIN(41, "ISH_SPI_CSB"), > - PINCTRL_PIN(42, "ISH_SPI_CLK"), > - PINCTRL_PIN(43, "ISH_SPI_MISO"), > - PINCTRL_PIN(44, "ISH_SPI_MOSI"), > - PINCTRL_PIN(45, "ISH_UART0_RXD"), > - PINCTRL_PIN(46, "ISH_UART0_TXD"), > - PINCTRL_PIN(47, "ISH_UART0_RTSB"), > - PINCTRL_PIN(48, "ISH_UART0_CTSB"), > - PINCTRL_PIN(49, "ISH_GP_4"), > - PINCTRL_PIN(50, "ISH_GP_5"), > - PINCTRL_PIN(51, "I2S_MCLK1_OUT"), > - PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"), > + PINCTRL_PIN(99, "ISH_GP_0"), > + PINCTRL_PIN(100, "ISH_GP_1"), > + PINCTRL_PIN(101, "ISH_GP_2"), > + PINCTRL_PIN(102, "ISH_GP_3"), > + PINCTRL_PIN(103, "IMGCLKOUT_0"), > + PINCTRL_PIN(104, "SRCCLKREQB_0"), > + PINCTRL_PIN(105, "SRCCLKREQB_1"), > + PINCTRL_PIN(106, "SRCCLKREQB_2"), > + PINCTRL_PIN(107, "SRCCLKREQB_3"), > + PINCTRL_PIN(108, "ISH_SPI_CSB"), > + PINCTRL_PIN(109, "ISH_SPI_CLK"), > + PINCTRL_PIN(110, "ISH_SPI_MISO"), > + PINCTRL_PIN(111, "ISH_SPI_MOSI"), > + PINCTRL_PIN(112, "ISH_UART0_RXD"), > + PINCTRL_PIN(113, "ISH_UART0_TXD"), > + PINCTRL_PIN(114, "ISH_UART0_RTSB"), > + PINCTRL_PIN(115, "ISH_UART0_CTSB"), > + PINCTRL_PIN(116, "ISH_GP_4"), > + PINCTRL_PIN(117, "ISH_GP_5"), > + PINCTRL_PIN(118, "I2S_MCLK1_OUT"), > + PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), > /* GPP_U */ > - PINCTRL_PIN(53, "UART3_RXD"), > - PINCTRL_PIN(54, "UART3_TXD"), > - PINCTRL_PIN(55, "UART3_RTSB"), > - PINCTRL_PIN(56, "UART3_CTSB"), > - PINCTRL_PIN(57, "GSPI3_CS0B"), > - PINCTRL_PIN(58, "GSPI3_CLK"), > - PINCTRL_PIN(59, "GSPI3_MISO"), > - PINCTRL_PIN(60, "GSPI3_MOSI"), > - PINCTRL_PIN(61, "GSPI4_CS0B"), > - PINCTRL_PIN(62, "GSPI4_CLK"), > - PINCTRL_PIN(63, "GSPI4_MISO"), > - PINCTRL_PIN(64, "GSPI4_MOSI"), > - PINCTRL_PIN(65, "GSPI5_CS0B"), > - PINCTRL_PIN(66, "GSPI5_CLK"), > - PINCTRL_PIN(67, "GSPI5_MISO"), > - PINCTRL_PIN(68, "GSPI5_MOSI"), > - PINCTRL_PIN(69, "GSPI6_CS0B"), > - PINCTRL_PIN(70, "GSPI6_CLK"), > - PINCTRL_PIN(71, "GSPI6_MISO"), > - PINCTRL_PIN(72, "GSPI6_MOSI"), > - PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"), > - PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"), > - PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"), > - PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"), > + PINCTRL_PIN(120, "UART3_RXD"), > + PINCTRL_PIN(121, "UART3_TXD"), > + PINCTRL_PIN(122, "UART3_RTSB"), > + PINCTRL_PIN(123, "UART3_CTSB"), > + PINCTRL_PIN(124, "GSPI3_CS0B"), > + PINCTRL_PIN(125, "GSPI3_CLK"), > + PINCTRL_PIN(126, "GSPI3_MISO"), > + PINCTRL_PIN(127, "GSPI3_MOSI"), > + PINCTRL_PIN(128, "GSPI4_CS0B"), > + PINCTRL_PIN(129, "GSPI4_CLK"), > + PINCTRL_PIN(130, "GSPI4_MISO"), > + PINCTRL_PIN(131, "GSPI4_MOSI"), > + PINCTRL_PIN(132, "GSPI5_CS0B"), > + PINCTRL_PIN(133, "GSPI5_CLK"), > + PINCTRL_PIN(134, "GSPI5_MISO"), > + PINCTRL_PIN(135, "GSPI5_MOSI"), > + PINCTRL_PIN(136, "GSPI6_CS0B"), > + PINCTRL_PIN(137, "GSPI6_CLK"), > + PINCTRL_PIN(138, "GSPI6_MISO"), > + PINCTRL_PIN(139, "GSPI6_MOSI"), > + PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), > + PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), > + PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), > + PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), > /* vGPIO */ > - PINCTRL_PIN(77, "CNV_BTEN"), > - PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"), > - PINCTRL_PIN(79, "CNV_BT_IF_SELECT"), > - PINCTRL_PIN(80, "vCNV_BT_UART_TXD"), > - PINCTRL_PIN(81, "vCNV_BT_UART_RXD"), > - PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"), > - PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"), > - PINCTRL_PIN(84, "vCNV_MFUART1_TXD"), > - PINCTRL_PIN(85, "vCNV_MFUART1_RXD"), > - PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"), > - PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"), > - PINCTRL_PIN(88, "vUART0_TXD"), > - PINCTRL_PIN(89, "vUART0_RXD"), > - PINCTRL_PIN(90, "vUART0_CTS_B"), > - PINCTRL_PIN(91, "vUART0_RTS_B"), > - PINCTRL_PIN(92, "vISH_UART0_TXD"), > - PINCTRL_PIN(93, "vISH_UART0_RXD"), > - PINCTRL_PIN(94, "vISH_UART0_CTS_B"), > - PINCTRL_PIN(95, "vISH_UART0_RTS_B"), > - PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"), > - PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"), > - PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"), > - PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"), > - PINCTRL_PIN(100, "vI2S2_SCLK"), > - PINCTRL_PIN(101, "vI2S2_SFRM"), > - PINCTRL_PIN(102, "vI2S2_TXD"), > - PINCTRL_PIN(103, "vI2S2_RXD"), > -}; > - > -static const struct intel_padgroup tgllp_community1_gpps[] = { > - TGL_GPP(0, 0, 7), /* GPP_S */ > - TGL_GPP(1, 8, 31), /* GPP_H */ > - TGL_GPP(2, 32, 52), /* GPP_D */ > - TGL_GPP(3, 53, 76), /* GPP_U */ > - TGL_GPP(4, 77, 103), /* vGPIO */ > -}; > - > -static const struct intel_community tgllp_community1[] = { > - TGL_COMMUNITY(0, 103, tgllp_community1_gpps), > -}; > - > -static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = { > - .uid = "1", > - .pins = tgllp_community1_pins, > - .npins = ARRAY_SIZE(tgllp_community1_pins), > - .communities = tgllp_community1, > - .ncommunities = ARRAY_SIZE(tgllp_community1), > -}; > - > -static const struct pinctrl_pin_desc tgllp_community4_pins[] = { > + PINCTRL_PIN(144, "CNV_BTEN"), > + PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), > + PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), > + PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), > + PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), > + PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), > + PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), > + PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), > + PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), > + PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), > + PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), > + PINCTRL_PIN(155, "vUART0_TXD"), > + PINCTRL_PIN(156, "vUART0_RXD"), > + PINCTRL_PIN(157, "vUART0_CTS_B"), > + PINCTRL_PIN(158, "vUART0_RTS_B"), > + PINCTRL_PIN(159, "vISH_UART0_TXD"), > + PINCTRL_PIN(160, "vISH_UART0_RXD"), > + PINCTRL_PIN(161, "vISH_UART0_CTS_B"), > + PINCTRL_PIN(162, "vISH_UART0_RTS_B"), > + PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), > + PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), > + PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), > + PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), > + PINCTRL_PIN(167, "vI2S2_SCLK"), > + PINCTRL_PIN(168, "vI2S2_SFRM"), > + PINCTRL_PIN(169, "vI2S2_TXD"), > + PINCTRL_PIN(170, "vI2S2_RXD"), > /* GPP_C */ > - PINCTRL_PIN(0, "SMBCLK"), > - PINCTRL_PIN(1, "SMBDATA"), > - PINCTRL_PIN(2, "SMBALERTB"), > - PINCTRL_PIN(3, "SML0CLK"), > - PINCTRL_PIN(4, "SML0DATA"), > - PINCTRL_PIN(5, "SML0ALERTB"), > - PINCTRL_PIN(6, "SML1CLK"), > - PINCTRL_PIN(7, "SML1DATA"), > - PINCTRL_PIN(8, "UART0_RXD"), > - PINCTRL_PIN(9, "UART0_TXD"), > - PINCTRL_PIN(10, "UART0_RTSB"), > - PINCTRL_PIN(11, "UART0_CTSB"), > - PINCTRL_PIN(12, "UART1_RXD"), > - PINCTRL_PIN(13, "UART1_TXD"), > - PINCTRL_PIN(14, "UART1_RTSB"), > - PINCTRL_PIN(15, "UART1_CTSB"), > - PINCTRL_PIN(16, "I2C0_SDA"), > - PINCTRL_PIN(17, "I2C0_SCL"), > - PINCTRL_PIN(18, "I2C1_SDA"), > - PINCTRL_PIN(19, "I2C1_SCL"), > - PINCTRL_PIN(20, "UART2_RXD"), > - PINCTRL_PIN(21, "UART2_TXD"), > - PINCTRL_PIN(22, "UART2_RTSB"), > - PINCTRL_PIN(23, "UART2_CTSB"), > + PINCTRL_PIN(171, "SMBCLK"), > + PINCTRL_PIN(172, "SMBDATA"), > + PINCTRL_PIN(173, "SMBALERTB"), > + PINCTRL_PIN(174, "SML0CLK"), > + PINCTRL_PIN(175, "SML0DATA"), > + PINCTRL_PIN(176, "SML0ALERTB"), > + PINCTRL_PIN(177, "SML1CLK"), > + PINCTRL_PIN(178, "SML1DATA"), > + PINCTRL_PIN(179, "UART0_RXD"), > + PINCTRL_PIN(180, "UART0_TXD"), > + PINCTRL_PIN(181, "UART0_RTSB"), > + PINCTRL_PIN(182, "UART0_CTSB"), > + PINCTRL_PIN(183, "UART1_RXD"), > + PINCTRL_PIN(184, "UART1_TXD"), > + PINCTRL_PIN(185, "UART1_RTSB"), > + PINCTRL_PIN(186, "UART1_CTSB"), > + PINCTRL_PIN(187, "I2C0_SDA"), > + PINCTRL_PIN(188, "I2C0_SCL"), > + PINCTRL_PIN(189, "I2C1_SDA"), > + PINCTRL_PIN(190, "I2C1_SCL"), > + PINCTRL_PIN(191, "UART2_RXD"), > + PINCTRL_PIN(192, "UART2_TXD"), > + PINCTRL_PIN(193, "UART2_RTSB"), > + PINCTRL_PIN(194, "UART2_CTSB"), > /* GPP_F */ > - PINCTRL_PIN(24, "CNV_BRI_DT"), > - PINCTRL_PIN(25, "CNV_BRI_RSP"), > - PINCTRL_PIN(26, "CNV_RGI_DT"), > - PINCTRL_PIN(27, "CNV_RGI_RSP"), > - PINCTRL_PIN(28, "CNV_RF_RESET_B"), > - PINCTRL_PIN(29, "GPPC_F_5"), > - PINCTRL_PIN(30, "CNV_PA_BLANKING"), > - PINCTRL_PIN(31, "GPPC_F_7"), > - PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), > - PINCTRL_PIN(33, "BOOTMPC"), > - PINCTRL_PIN(34, "GPPC_F_10"), > - PINCTRL_PIN(35, "GPPC_F_11"), > - PINCTRL_PIN(36, "GSXDOUT"), > - PINCTRL_PIN(37, "GSXSLOAD"), > - PINCTRL_PIN(38, "GSXDIN"), > - PINCTRL_PIN(39, "GSXSRESETB"), > - PINCTRL_PIN(40, "GSXCLK"), > - PINCTRL_PIN(41, "GMII_MDC"), > - PINCTRL_PIN(42, "GMII_MDIO"), > - PINCTRL_PIN(43, "SRCCLKREQB_6"), > - PINCTRL_PIN(44, "EXT_PWR_GATEB"), > - PINCTRL_PIN(45, "EXT_PWR_GATE2B"), > - PINCTRL_PIN(46, "VNN_CTRL"), > - PINCTRL_PIN(47, "V1P05_CTRL"), > - PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), > + PINCTRL_PIN(195, "CNV_BRI_DT"), > + PINCTRL_PIN(196, "CNV_BRI_RSP"), > + PINCTRL_PIN(197, "CNV_RGI_DT"), > + PINCTRL_PIN(198, "CNV_RGI_RSP"), > + PINCTRL_PIN(199, "CNV_RF_RESET_B"), > + PINCTRL_PIN(200, "GPPC_F_5"), > + PINCTRL_PIN(201, "CNV_PA_BLANKING"), > + PINCTRL_PIN(202, "GPPC_F_7"), > + PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), > + PINCTRL_PIN(204, "BOOTMPC"), > + PINCTRL_PIN(205, "GPPC_F_10"), > + PINCTRL_PIN(206, "GPPC_F_11"), > + PINCTRL_PIN(207, "GSXDOUT"), > + PINCTRL_PIN(208, "GSXSLOAD"), > + PINCTRL_PIN(209, "GSXDIN"), > + PINCTRL_PIN(210, "GSXSRESETB"), > + PINCTRL_PIN(211, "GSXCLK"), > + PINCTRL_PIN(212, "GMII_MDC"), > + PINCTRL_PIN(213, "GMII_MDIO"), > + PINCTRL_PIN(214, "SRCCLKREQB_6"), > + PINCTRL_PIN(215, "EXT_PWR_GATEB"), > + PINCTRL_PIN(216, "EXT_PWR_GATE2B"), > + PINCTRL_PIN(217, "VNN_CTRL"), > + PINCTRL_PIN(218, "V1P05_CTRL"), > + PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), > /* HVCMOS */ > - PINCTRL_PIN(49, "L_BKLTEN"), > - PINCTRL_PIN(50, "L_BKLTCTL"), > - PINCTRL_PIN(51, "L_VDDEN"), > - PINCTRL_PIN(52, "SYS_PWROK"), > - PINCTRL_PIN(53, "SYS_RESETB"), > - PINCTRL_PIN(54, "MLK_RSTB"), > + PINCTRL_PIN(220, "L_BKLTEN"), > + PINCTRL_PIN(221, "L_BKLTCTL"), > + PINCTRL_PIN(222, "L_VDDEN"), > + PINCTRL_PIN(223, "SYS_PWROK"), > + PINCTRL_PIN(224, "SYS_RESETB"), > + PINCTRL_PIN(225, "MLK_RSTB"), > /* GPP_E */ > - PINCTRL_PIN(55, "SATAXPCIE_0"), > - PINCTRL_PIN(56, "SPI1_IO_2"), > - PINCTRL_PIN(57, "SPI1_IO_3"), > - PINCTRL_PIN(58, "CPU_GP_0"), > - PINCTRL_PIN(59, "SATA_DEVSLP_0"), > - PINCTRL_PIN(60, "SATA_DEVSLP_1"), > - PINCTRL_PIN(61, "GPPC_E_6"), > - PINCTRL_PIN(62, "CPU_GP_1"), > - PINCTRL_PIN(63, "SPI1_CS1B"), > - PINCTRL_PIN(64, "USB2_OCB_0"), > - PINCTRL_PIN(65, "SPI1_CSB"), > - PINCTRL_PIN(66, "SPI1_CLK"), > - PINCTRL_PIN(67, "SPI1_MISO_IO_1"), > - PINCTRL_PIN(68, "SPI1_MOSI_IO_0"), > - PINCTRL_PIN(69, "DDSP_HPD_A"), > - PINCTRL_PIN(70, "ISH_GP_6"), > - PINCTRL_PIN(71, "ISH_GP_7"), > - PINCTRL_PIN(72, "GPPC_E_17"), > - PINCTRL_PIN(73, "DDP1_CTRLCLK"), > - PINCTRL_PIN(74, "DDP1_CTRLDATA"), > - PINCTRL_PIN(75, "DDP2_CTRLCLK"), > - PINCTRL_PIN(76, "DDP2_CTRLDATA"), > - PINCTRL_PIN(77, "DDPA_CTRLCLK"), > - PINCTRL_PIN(78, "DDPA_CTRLDATA"), > - PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), > + PINCTRL_PIN(226, "SATAXPCIE_0"), > + PINCTRL_PIN(227, "SPI1_IO_2"), > + PINCTRL_PIN(228, "SPI1_IO_3"), > + PINCTRL_PIN(229, "CPU_GP_0"), > + PINCTRL_PIN(230, "SATA_DEVSLP_0"), > + PINCTRL_PIN(231, "SATA_DEVSLP_1"), > + PINCTRL_PIN(232, "GPPC_E_6"), > + PINCTRL_PIN(233, "CPU_GP_1"), > + PINCTRL_PIN(234, "SPI1_CS1B"), > + PINCTRL_PIN(235, "USB2_OCB_0"), > + PINCTRL_PIN(236, "SPI1_CSB"), > + PINCTRL_PIN(237, "SPI1_CLK"), > + PINCTRL_PIN(238, "SPI1_MISO_IO_1"), > + PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), > + PINCTRL_PIN(240, "DDSP_HPD_A"), > + PINCTRL_PIN(241, "ISH_GP_6"), > + PINCTRL_PIN(242, "ISH_GP_7"), > + PINCTRL_PIN(243, "GPPC_E_17"), > + PINCTRL_PIN(244, "DDP1_CTRLCLK"), > + PINCTRL_PIN(245, "DDP1_CTRLDATA"), > + PINCTRL_PIN(246, "DDP2_CTRLCLK"), > + PINCTRL_PIN(247, "DDP2_CTRLDATA"), > + PINCTRL_PIN(248, "DDPA_CTRLCLK"), > + PINCTRL_PIN(249, "DDPA_CTRLDATA"), > + PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), > /* JTAG */ > - PINCTRL_PIN(80, "JTAG_TDO"), > - PINCTRL_PIN(81, "JTAGX"), > - PINCTRL_PIN(82, "PRDYB"), > - PINCTRL_PIN(83, "PREQB"), > - PINCTRL_PIN(84, "CPU_TRSTB"), > - PINCTRL_PIN(85, "JTAG_TDI"), > - PINCTRL_PIN(86, "JTAG_TMS"), > - PINCTRL_PIN(87, "JTAG_TCK"), > - PINCTRL_PIN(88, "DBG_PMODE"), > -}; > - > -static const struct intel_padgroup tgllp_community4_gpps[] = { > - TGL_GPP(0, 0, 23), /* GPP_C */ > - TGL_GPP(1, 24, 48), /* GPP_F */ > - TGL_GPP(2, 49, 54), /* HVCMOS */ > - TGL_GPP(3, 55, 79), /* GPP_E */ > - TGL_GPP(4, 80, 88), /* JTAG */ > + PINCTRL_PIN(251, "JTAG_TDO"), > + PINCTRL_PIN(252, "JTAGX"), > + PINCTRL_PIN(253, "PRDYB"), > + PINCTRL_PIN(254, "PREQB"), > + PINCTRL_PIN(255, "CPU_TRSTB"), > + PINCTRL_PIN(256, "JTAG_TDI"), > + PINCTRL_PIN(257, "JTAG_TMS"), > + PINCTRL_PIN(258, "JTAG_TCK"), > + PINCTRL_PIN(259, "DBG_PMODE"), > + /* GPP_R */ > + PINCTRL_PIN(260, "HDA_BCLK"), > + PINCTRL_PIN(261, "HDA_SYNC"), > + PINCTRL_PIN(262, "HDA_SDO"), > + PINCTRL_PIN(263, "HDA_SDI_0"), > + PINCTRL_PIN(264, "HDA_RSTB"), > + PINCTRL_PIN(265, "HDA_SDI_1"), > + PINCTRL_PIN(266, "GPP_R_6"), > + PINCTRL_PIN(267, "GPP_R_7"), > + /* SPI */ > + PINCTRL_PIN(268, "SPI0_IO_2"), > + PINCTRL_PIN(269, "SPI0_IO_3"), > + PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), > + PINCTRL_PIN(271, "SPI0_MISO_IO_1"), > + PINCTRL_PIN(272, "SPI0_TPM_CSB"), > + PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), > + PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), > + PINCTRL_PIN(275, "SPI0_CLK"), > + PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), > }; > > -static const struct intel_community tgllp_community4[] = { > - TGL_COMMUNITY(0, 88, tgllp_community4_gpps), > +static const struct intel_padgroup tgllp_community0_gpps[] = { > + TGL_GPP(0, 0, 25, 0), /* GPP_B */ > + TGL_GPP(1, 26, 41, 32), /* GPP_T */ > + TGL_GPP(2, 42, 66, 64), /* GPP_A */ > }; > > -static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = { > - .uid = "4", > - .pins = tgllp_community4_pins, > - .npins = ARRAY_SIZE(tgllp_community4_pins), > - .communities = tgllp_community4, > - .ncommunities = ARRAY_SIZE(tgllp_community4), > +static const struct intel_padgroup tgllp_community1_gpps[] = { > + TGL_GPP(0, 67, 74, 96), /* GPP_S */ > + TGL_GPP(1, 75, 98, 128), /* GPP_H */ > + TGL_GPP(2, 99, 119, 160), /* GPP_D */ > + TGL_GPP(3, 120, 143, 192), /* GPP_U */ > + TGL_GPP(4, 144, 170, 224), /* vGPIO */ > }; > > -static const struct pinctrl_pin_desc tgllp_community5_pins[] = { > - /* GPP_R */ > - PINCTRL_PIN(0, "HDA_BCLK"), > - PINCTRL_PIN(1, "HDA_SYNC"), > - PINCTRL_PIN(2, "HDA_SDO"), > - PINCTRL_PIN(3, "HDA_SDI_0"), > - PINCTRL_PIN(4, "HDA_RSTB"), > - PINCTRL_PIN(5, "HDA_SDI_1"), > - PINCTRL_PIN(6, "GPP_R_6"), > - PINCTRL_PIN(7, "GPP_R_7"), > - /* SPI */ > - PINCTRL_PIN(8, "SPI0_IO_2"), > - PINCTRL_PIN(9, "SPI0_IO_3"), > - PINCTRL_PIN(10, "SPI0_MOSI_IO_0"), > - PINCTRL_PIN(11, "SPI0_MISO_IO_1"), > - PINCTRL_PIN(12, "SPI0_TPM_CSB"), > - PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"), > - PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"), > - PINCTRL_PIN(15, "SPI0_CLK"), > - PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"), > +static const struct intel_padgroup tgllp_community4_gpps[] = { > + TGL_GPP(0, 171, 194, 256), /* GPP_C */ > + TGL_GPP(1, 195, 219, 288), /* GPP_F */ > + TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ > + TGL_GPP(3, 226, 250, 320), /* GPP_E */ > + TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ > }; > > static const struct intel_padgroup tgllp_community5_gpps[] = { > - TGL_GPP(0, 0, 7), /* GPP_R */ > - TGL_GPP(1, 8, 16), /* SPI */ > -}; > - > -static const struct intel_community tgllp_community5[] = { > - TGL_COMMUNITY(0, 16, tgllp_community5_gpps), > + TGL_GPP(0, 260, 267, 352), /* GPP_R */ > + TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ > }; > > -static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = { > - .uid = "5", > - .pins = tgllp_community5_pins, > - .npins = ARRAY_SIZE(tgllp_community5_pins), > - .communities = tgllp_community5, > - .ncommunities = ARRAY_SIZE(tgllp_community5), > +static const struct intel_community tgllp_communities[] = { > + TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps), > + TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps), > + TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps), > + TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps), > }; > > -static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = { > - &tgllp_community0_soc_data, > - &tgllp_community1_soc_data, > - &tgllp_community4_soc_data, > - &tgllp_community5_soc_data, > - NULL > +static const struct intel_pinctrl_soc_data tgllp_soc_data = { > + .pins = tgllp_pins, > + .npins = ARRAY_SIZE(tgllp_pins), > + .communities = tgllp_communities, > + .ncommunities = ARRAY_SIZE(tgllp_communities), > }; > > static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { > - { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array }, > + { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, > { } > }; > MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); > @@ -438,7 +391,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); > static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); > > static struct platform_driver tgl_pinctrl_driver = { > - .probe = intel_pinctrl_probe_by_uid, > + .probe = intel_pinctrl_probe_by_hid, > .driver = { > .name = "tigerlake-pinctrl", > .acpi_match_table = tgl_pinctrl_acpi_match, > -- > 2.24.1 > -- With Best Regards, Andy Shevchenko