From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6086CC2D0DB for ; Fri, 31 Jan 2020 15:07:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E96120661 for ; Fri, 31 Jan 2020 15:07:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E96120661 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E4716E9B5; Fri, 31 Jan 2020 15:07:49 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29B7E6E9B5 for ; Fri, 31 Jan 2020 15:07:48 +0000 (UTC) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jan 2020 07:07:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,386,1574150400"; d="scan'208";a="233447977" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga006.jf.intel.com with SMTP; 31 Jan 2020 07:07:44 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 Jan 2020 17:07:43 +0200 Date: Fri, 31 Jan 2020 17:07:43 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: intel-gfx@lists.freedesktop.org Message-ID: <20200131150743.GR13686@intel.com> References: <20200120174728.21095-1-ville.syrjala@linux.intel.com> <20200120174728.21095-3-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200120174728.21095-3-ville.syrjala@linux.intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Jan 20, 2020 at 07:47:12PM +0200, Ville Syrjala wrote: > From: Ville Syrj=E4l=E4 > = > The linetime watermarks really have very little in common with the > plane watermarks. It looks to be cleaner to simply track them in > the crtc_state and program them from the normal modeset/fastset > paths. > = > The only dark cloud comes from the fact that the register is > still supposedly single buffered. So in theory it might still > need some form of two stage programming. Note that even though > HSW/BDWhave two stage programming we never computed any special > intermediate values for the linetime watermarks, and on SKL+ > we don't even have the two stage stuff plugged in since everything > else is double buffered. So let's assume it's all fine and > continue doing what we've been doing. > = > Actually on HSW/BDW the value should not even change without > a full modeset since it doesn't account for pfit downscaling. > Thus only fastboot might be affected. But on SKL+ the pfit > scaling factor is take into consideration so the value may > change during any fastset. > = > As a bonus we'll plug this thing into the state > checker/dump now. > = > v2: Rebase due to bigjoiner prep > v2: Only compute ips linetime for IPS capable pipes. > Bspec says the register values is ignored for other > pipes, but in fact it can't even be written so the > state checker becomes unhappy if we don't compute > it as zero. > = > Cc: Stanislav Lisovskiy > Signed-off-by: Ville Syrj=E4l=E4 Extracted Stan's r-b from the trybot list (whoops) and pushed the lot: https://lists.freedesktop.org/archives/intel-gfx-trybot/2020-January/086561= .html Thanks for the reviews. As Imre pointed out there some further docs/function naming improvements should probably be done to make the thing a bit less confusing. I'll look at that as a followup. -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx