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* [PATCH v2] imx: support for conga-QMX8 board
@ 2020-02-03 13:59 Oliver Graute
  2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
                   ` (2 more replies)
  0 siblings, 3 replies; 21+ messages in thread
From: Oliver Graute @ 2020-02-03 13:59 UTC (permalink / raw)
  To: u-boot

Add i.MX8QM qmx8 congatec board support

U-Boot 2020.01-00003-g99c15cc616 (Feb 03 2020 - 14:28:07 +0100)

CPU:   NXP i.MX8QM RevB A53 at 1200 MHz

Model: Congatec QMX8 Qseven series
Board: conga-QMX8
Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF d6451cc
Boot:  SD2
DRAM:  6 GiB
Device 'gpio at 5d090000': seq 0 is in use by 'gpio at 5d080000'
Device 'gpio at 5d0a0000': seq 1 is in use by 'gpio at 5d090000'
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial at 5a060000
Out:   serial at 5a060000
Err:   serial at 5a060000
switch to partitions #0, OK
mmc2 is current device
Net:   eth0: ethernet at 5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
---

These changes are based on this vendor tree:
git.congatec.com/imx8_early_access/imx8_uboot_internal.git

Changes for v2:
 - added USDHC3_BASE_ADDR
 - replaced CONFIG_FSL_ESDHC with CONFIG_FSL_ESDHC_IMX
 - set CONFIG_FEC_MXC_PHYADDR to -1
 - moved CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to defconfig

 arch/arm/dts/Makefile               |   1 +
 arch/arm/dts/imx8qm-cgtqmx8.dts     | 427 +++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig           |   2 +-
 arch/arm/mach-imx/imx8/Kconfig      |   7 +
 board/congatec/cgtqmx8/Kconfig      |  14 +
 board/congatec/cgtqmx8/MAINTAINERS  |   6 +
 board/congatec/cgtqmx8/Makefile     |  11 +
 board/congatec/cgtqmx8/README       |  15 +
 board/congatec/cgtqmx8/cgtqmx8.c    | 478 ++++++++++++++++++++++++++++
 board/congatec/cgtqmx8/imximage.cfg |  21 ++
 board/congatec/cgtqmx8/spl.c        |  75 +++++
 board/congatec/common/Kconfig       |  48 +++
 board/congatec/common/Makefile      |  23 ++
 board/congatec/common/mmc.c         |  50 +++
 configs/cgtqmx8_defconfig           |  82 +++++
 include/configs/cgtqmx8.h           | 196 ++++++++++++
 16 files changed, 1455 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts
 create mode 100644 board/congatec/cgtqmx8/Kconfig
 create mode 100644 board/congatec/cgtqmx8/MAINTAINERS
 create mode 100644 board/congatec/cgtqmx8/Makefile
 create mode 100644 board/congatec/cgtqmx8/README
 create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c
 create mode 100644 board/congatec/cgtqmx8/imximage.cfg
 create mode 100644 board/congatec/cgtqmx8/spl.c
 create mode 100644 board/congatec/common/Kconfig
 create mode 100644 board/congatec/common/Makefile
 create mode 100644 board/congatec/common/mmc.c
 create mode 100644 configs/cgtqmx8_defconfig
 create mode 100644 include/configs/cgtqmx8.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0127a91a82..4e13640a33 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -664,6 +664,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
+	imx8qm-cgtqmx8.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
new file mode 100644
index 0000000000..79a99ddb10
--- /dev/null
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Copyright 2017 congatec AG
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+	model = "Congatec QMX8 Qseven series";
+	compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay-us = <3000>;
+		};
+
+		reg_usdhc3_vmmc: usdhc3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd2";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay-us = <3000>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_txc_dly;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <6>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c0>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	rtc_ext: m41t62 at 68 {
+		compatible = "st,m41t62";
+		reg = <0x68>;
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	wm8904: wm8904 at 1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+
+		clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
+		clock-names = "mclk";
+		wlf,shared-lrclk;
+		/* power-domains = <&pd_mclk_out0>; */
+
+		assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
+				<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
+				<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+				<&clk IMX8QM_AUD_MCLKOUT0>;
+
+		assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-qmx8 {
+
+		pinctrl_hog: hoggrp{
+			fsl,pins = <
+				SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09		0x00000021
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x00000021
+				SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08		0x00000021
+				SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15			0x00000021
+				SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31		0x00000021
+				SC_P_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021
+				SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00		0x00000021
+				SC_P_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
+			>;
+		};
+
+		pinctrl_lpi2c0: lpi2c0grp {
+			fsl,pins = <
+				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0xc600004c
+				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
+				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
+				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
+				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
+			>;
+		};
+
+		pinctrl_lpuart3: lpuart3grp {
+			fsl,pins = <
+				SC_P_M41_GPIO0_00_DMA_UART3_RX		0x06000020
+				SC_P_M41_GPIO0_01_DMA_UART3_TX		0x06000020
+			>;
+		};
+
+		pinctrl_mlb: mlbgrp {
+			fsl,pins = <
+				SC_P_MLB_SIG_CONN_MLB_SIG		0x21
+				SC_P_MLB_CLK_CONN_MLB_CLK		0x21
+				SC_P_MLB_DATA_CONN_MLB_DATA		0x21
+			>;
+		};
+
+		pinctrl_isl29023: isl29023grp {
+			fsl,pins = <
+				SC_P_ADC_IN2_LSIO_GPIO3_IO20		0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09	0x00000021
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+/*
+		pinctrl_usbotg1: usbotg1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
+			>;
+		};
+*/
+	};
+};
+
+&lpuart0 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 { /* Q7 connector */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&pd_dma_lpuart0 {
+	debug_console;
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc3_vmmc>;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
+	status = "okay";
+};
+/*
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+*/
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4ce2799b72..957d4e6b16 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,7 +23,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8
 	help
 	  bootaux [addr] to boot auxiliary core.
 
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index cdb78afacf..9930ce12ef 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -60,6 +60,12 @@ config TARGET_IMX8QM_MEK
 	select BOARD_LATE_INIT
 	select IMX8QM
 
+config TARGET_CONGA_QMX8
+	bool "Support congatec conga-QMX8 board"
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select IMX8QM
+
 config TARGET_IMX8QM_ROM7720_A1
 	bool "Support i.MX8QM ROM-7720-A1"
 	select BOARD_LATE_INIT
@@ -75,6 +81,7 @@ endchoice
 
 source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/congatec/cgtqmx8/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig
new file mode 100644
index 0000000000..7273039261
--- /dev/null
+++ b/board/congatec/cgtqmx8/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_CONGA_QMX8
+
+config SYS_BOARD
+	default "cgtqmx8"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_CONFIG_NAME
+	default "cgtqmx8"
+
+source "board/congatec/common/Kconfig"
+
+endif
diff --git a/board/congatec/cgtqmx8/MAINTAINERS b/board/congatec/cgtqmx8/MAINTAINERS
new file mode 100644
index 0000000000..a242e534c8
--- /dev/null
+++ b/board/congatec/cgtqmx8/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QM CGTQMX8 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/congatec/cgtqmx8/
+F:	include/configs/cgtqmx8.h
+F:	configs/cgtqmx8_defconfig
diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile
new file mode 100644
index 0000000000..4b59dbb6bc
--- /dev/null
+++ b/board/congatec/cgtqmx8/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cgtqmx8.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/congatec/cgtqmx8/README b/board/congatec/cgtqmx8/README
new file mode 100644
index 0000000000..5724eb89f7
--- /dev/null
+++ b/board/congatec/cgtqmx8/README
@@ -0,0 +1,15 @@
+Build U-Boot
+============
+
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
+$ make cgtqmx8_defconfig
+$ make u-boot.bin
+$ make flash.bin
+
+Flash the binary into the SD card
+=================================
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
new file mode 100644
index 0000000000..921f6184cb
--- /dev/null
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -0,0 +1,478 @@
+//SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2018 congatec AG
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <usb.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <power-domain.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	/* sc_ipc_t ipcHndl = 0; */
+	sc_err_t sciErr = 0;
+
+	/* When start u-boot in XEN VM, directly return */
+	/* if (IS_ENABLED(CONFIG_XEN)) */
+		/* return 0; */
+
+	/* ipcHndl = gd->arch.ipc_channel_handle; */
+
+	/* Power up UART0, this is very early while power domain is not working */
+	sciErr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
+	if (sciErr != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART0 clock root to 80 MHz */
+	sc_pm_clock_rate_t rate = 80000000;
+	sciErr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
+	if (sciErr != SC_ERR_NONE)
+		return 0;
+
+	/* Enable UART0 clock root */
+	sciErr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+	if (sciErr != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc1_sd[] = {
+	SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	struct power_domain pd;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0 (onboard eMMC)     USDHC1
+	 * mmc1 (external SD card) USDHC2
+	 * mmc2 (onboard µSD)      USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+		  /* onboard eMMC */
+			if (!power_domain_lookup_name("conn_sdhc0", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+		  /* external SD card */
+			if (!power_domain_lookup_name("conn_sdhc1", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
+			init_clk_usdhc(1);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_request(USDHC1_CD_GPIO, "sd1_cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		case 2:
+		  /* onboard µSD */
+			if (!power_domain_lookup_name("conn_sdhc2", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#ifdef CONFIG_FEC_MXC
+#include <miiphy.h>
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+}
+
+static void enet_device_phy_reset(void)
+{
+	gpio_set_value(FEC0_RESET, 0);
+	udelay(50);
+	gpio_set_value(FEC0_RESET, 1);
+
+	/* The board has a long delay for this reset to become stable */
+	mdelay(200);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct power_domain pd0;
+
+	/* if (!power_domain_lookup_name(FEC0_PDOMAIN, &pd0)) */
+	  /* power_domain_on(&pd0); */
+
+	setup_iomux_fec();
+
+	/* ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, */
+		/* CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); */
+	if (ret)
+		printf("FEC0 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_GPIO
+
+#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
+#define BKL_ENABLE  IMX_GPIO_NR(1, 7)
+
+static iomux_cfg_t board_gpios[] = {
+	SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+	/* enable LVDS */
+	gpio_request(LVDS_ENABLE, "lvds_enable");
+	gpio_direction_output(LVDS_ENABLE, 1);
+
+	/* enable backlight */
+	gpio_request(BKL_ENABLE, "bkl_enable");
+	gpio_direction_output(BKL_ENABLE, 1);
+
+	/* ethernet reset */
+	gpio_request(FEC0_RESET, "enet0_reset");
+	gpio_direction_output(FEC0_RESET, 1);
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: conga-QMX8\n");
+
+	build_info();
+	print_bootinfo();
+
+	/* Note:  After reloc, ipcHndl will no longer be valid.  If handle
+	 *        returned by sc_ipc_open matches SC_IPC_CH, use this
+	 *        macro (valid after reloc) for subsequent SCI calls.
+	 */
+	/*
+	if (gd->arch.ipc_channel_handle != SC_IPC_CH) {
+		printf("\nSCI error! Invalid handle\n");
+	}
+	*/
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+#ifdef CONFIG_MXC_GPIO
+	board_gpio_init();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+/*
+	puts("SCI reboot request");
+	sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
+	while (1)
+		putc('.');
+*/
+	/* TODO */
+}
+
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return dev_no;
+}
+
+extern uint32_t _end_ofs;
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "QMX8");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+#ifdef IMX_LOAD_HDMI_FIMRWARE
+	char *end_of_uboot;
+	char command[256];
+	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
+	end_of_uboot += 9;
+
+	/* load hdmitxfw.bin and hdmirxfw.bin*/
+	memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
+			IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
+
+	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
+	run_command(command, 0);
+
+	sprintf(command, "hdprx load 0x%x",
+			IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
+	run_command(command, 0);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+/* Only Enable USB3 resources currently */
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg
new file mode 100644
index 0000000000..e324c7ca37
--- /dev/null
+++ b/board/congatec/cgtqmx8/imximage.cfg
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier:	GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c
new file mode 100644
index 0000000000..95ce9f37e8
--- /dev/null
+++ b/board/congatec/cgtqmx8/spl.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int offset;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+	while (offset != -FDT_ERR_NOTFOUND) {
+		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+			       NULL, true);
+		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+						       "nxp,imx8-pd");
+	}
+
+	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig
new file mode 100644
index 0000000000..5c205bd830
--- /dev/null
+++ b/board/congatec/common/Kconfig
@@ -0,0 +1,48 @@
+if !ARCH_IMX8M && !ARCH_IMX8
+
+config CHAIN_OF_TRUST
+	depends on !FIT_SIGNATURE && SECURE_BOOT
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	select FSL_CAAM
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	select CMD_EXT4 if ARM
+	select CMD_EXT4_WRITE if ARM
+	bool
+	default y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y if CHAIN_OF_TRUST
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
+
+endif
+
+config VOL_MONITOR_LTC3882_READ
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor read"
+	default n
+	help
+	 This option enables LTC3882 voltage monitor read
+	 functionality. It is used by common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor set"
+	default n
+	help
+	 This option enables LTC3882 voltage monitor set
+	 functionality. It is used by common VID driver.
+
+config USB_TCPC
+	bool "USB Typec port controller simple driver"
+	default n
+	help
+	  Enable USB type-c port controller (TCPC) driver
diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile
new file mode 100644
index 0000000000..d4ddfbf971
--- /dev/null
+++ b/board/congatec/common/Makefile
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+
+obj-y				+= mmc.o
+
+endif
diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c
new file mode 100644
index 0000000000..9fc3e68728
--- /dev/null
+++ b/board/congatec/common/mmc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+#include <mmc.h>
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if ((autodetect_str != NULL) &&
+		(strcmp(autodetect_str, "yes") == 0)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
new file mode 100644
index 0000000000..21c788cb98
--- /dev/null
+++ b/configs/cgtqmx8_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_CONGA_QMX8=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_IMX_BOOTAUX=y
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
new file mode 100644
index 0000000000..51f325e875
--- /dev/null
+++ b/include/configs/cgtqmx8.h
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2018 congatec AG
+ *
+ */
+
+#ifndef __CGTQMX8_H
+#define __CGTQMX8_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_TEXT_BASE				0x0
+#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
+
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+#define USDHC3_BASE_ADDR                0x5B030000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* FUSE command */
+#define CONFIG_CMD_FUSE
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"m4_1_image=m4_1.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+	"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+#define FEC0_RESET IMX_GPIO_NR(2, 5)
+#define FEC0_PDOMAIN "conn_enet0"
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_MXC_PHYADDR		-1
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __CGTQMX8_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [RFC 1/2] hack to boot with 2020.01
  2020-02-03 13:59 [PATCH v2] imx: support for conga-QMX8 board Oliver Graute
@ 2020-02-03 13:59 ` Oliver Graute
  2020-02-03 17:15   ` Simon Glass
  2020-02-04 17:07   ` Tom Rini
  2020-02-03 13:59 ` [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal" Oliver Graute
  2020-05-04  7:40 ` [PATCH v2] imx: support for conga-QMX8 board Stefano Babic
  2 siblings, 2 replies; 21+ messages in thread
From: Oliver Graute @ 2020-02-03 13:59 UTC (permalink / raw)
  To: u-boot

As proposed here:

https://lists.denx.de/pipermail/u-boot/2020-January/396749.html

Both of my imx8qm boards (Advantech and Congatec) aren't booting
2020.01 without this change. Whats the proper way to fix this on my side?
---
 drivers/core/device.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 4e037083a6..8358051d60 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -395,11 +395,8 @@ int device_probe(struct udevice *dev)
 
 	if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
 	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
-	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
-		ret = dev_power_domain_on(dev);
-		if (ret)
-			goto fail;
-	}
+	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF))
+		dev_power_domain_on(dev);
 
 	ret = uclass_pre_probe_device(dev);
 	if (ret)
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-03 13:59 [PATCH v2] imx: support for conga-QMX8 board Oliver Graute
  2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
@ 2020-02-03 13:59 ` Oliver Graute
  2020-02-13 17:12   ` Neil Armstrong
  2020-05-04  7:40 ` [PATCH v2] imx: support for conga-QMX8 board Stefano Babic
  2 siblings, 1 reply; 21+ messages in thread
From: Oliver Graute @ 2020-02-03 13:59 UTC (permalink / raw)
  To: u-boot

The conga-imx8 board isn't booting without this revert. Can someone tell me
what I need to Do so that this revert is not necessary?

This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
---
 drivers/core/device-remove.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 5c8dc4ad70..586fadee0a 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -16,7 +16,6 @@
 #include <dm/uclass.h>
 #include <dm/uclass-internal.h>
 #include <dm/util.h>
-#include <power-domain.h>
 
 int device_chld_unbind(struct udevice *dev, struct driver *drv)
 {
@@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
 		}
 	}
 
-	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
-	    (dev != gd->cur_serial_dev))
-		dev_power_domain_off(dev);
-
 	if (flags_remove(flags, drv->flags)) {
 		device_free(dev);
 
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [RFC 1/2] hack to boot with 2020.01
  2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
@ 2020-02-03 17:15   ` Simon Glass
  2020-02-04 17:07   ` Tom Rini
  1 sibling, 0 replies; 21+ messages in thread
From: Simon Glass @ 2020-02-03 17:15 UTC (permalink / raw)
  To: u-boot

Hi Oliver,

On Mon, 3 Feb 2020 at 06:59, Oliver Graute
<oliver.graute@kococonnector.com> wrote:
>
> As proposed here:
>
> https://lists.denx.de/pipermail/u-boot/2020-January/396749.html
>
> Both of my imx8qm boards (Advantech and Congatec) aren't booting
> 2020.01 without this change. Whats the proper way to fix this on my side?

Possibly one of the drivers is doing something in ofdata_to_platdata()
that it should be doing in probe()?

You should check what error dev_power_domain_on() is returning.

One trick is to add

   return log_msg_ret("some msg", ret);

to all the error returns, define CONFIG_LOG and LOG_ERROR_RETURN and
you should get some detail.

Regards,
Simon


> ---
>  drivers/core/device.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/core/device.c b/drivers/core/device.c
> index 4e037083a6..8358051d60 100644
> --- a/drivers/core/device.c
> +++ b/drivers/core/device.c
> @@ -395,11 +395,8 @@ int device_probe(struct udevice *dev)
>
>         if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
>             (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
> -           !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
> -               ret = dev_power_domain_on(dev);
> -               if (ret)
> -                       goto fail;
> -       }
> +           !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF))
> +               dev_power_domain_on(dev);
>
>         ret = uclass_pre_probe_device(dev);
>         if (ret)
> --
> 2.17.1
>

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 1/2] hack to boot with 2020.01
  2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
  2020-02-03 17:15   ` Simon Glass
@ 2020-02-04 17:07   ` Tom Rini
  2020-02-05  8:48     ` Oliver Graute
  1 sibling, 1 reply; 21+ messages in thread
From: Tom Rini @ 2020-02-04 17:07 UTC (permalink / raw)
  To: u-boot

On Mon, Feb 03, 2020 at 01:59:14PM +0000, Oliver Graute wrote:
> As proposed here:
> 
> https://lists.denx.de/pipermail/u-boot/2020-January/396749.html
> 
> Both of my imx8qm boards (Advantech and Congatec) aren't booting
> 2020.01 without this change. Whats the proper way to fix this on my side?
>
> ---
>  drivers/core/device.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/core/device.c b/drivers/core/device.c
> index 4e037083a6..8358051d60 100644
> --- a/drivers/core/device.c
> +++ b/drivers/core/device.c
> @@ -395,11 +395,8 @@ int device_probe(struct udevice *dev)
>  
>  	if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
>  	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
> -	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
> -		ret = dev_power_domain_on(dev);
> -		if (ret)
> -			goto fail;
> -	}
> +	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF))
> +		dev_power_domain_on(dev);
>  
>  	ret = uclass_pre_probe_device(dev);
>  	if (ret)

Adding Lokesh and quoting him from
http://patchwork.ozlabs.org/patch/1211325/

"Can you check by not returning on failure here? If yes then check the
power-domain/driver that is failing. If any driver doesn't expect core
to enable power-domain then enable DM_FLAG_DEFAULT_PD_CTRL_OFF in the
respective driver."

-- 
Tom
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^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 1/2] hack to boot with 2020.01
  2020-02-04 17:07   ` Tom Rini
@ 2020-02-05  8:48     ` Oliver Graute
  0 siblings, 0 replies; 21+ messages in thread
From: Oliver Graute @ 2020-02-05  8:48 UTC (permalink / raw)
  To: u-boot

On 04/02/20, Tom Rini wrote:
> On Mon, Feb 03, 2020 at 01:59:14PM +0000, Oliver Graute wrote:
> > As proposed here:
> > 
> > https://lists.denx.de/pipermail/u-boot/2020-January/396749.html
> > 
> > Both of my imx8qm boards (Advantech and Congatec) aren't booting
> > 2020.01 without this change. Whats the proper way to fix this on my side?
> >
> > ---
> >  drivers/core/device.c | 7 ++-----
> >  1 file changed, 2 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/core/device.c b/drivers/core/device.c
> > index 4e037083a6..8358051d60 100644
> > --- a/drivers/core/device.c
> > +++ b/drivers/core/device.c
> > @@ -395,11 +395,8 @@ int device_probe(struct udevice *dev)
> >  
> >  	if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
> >  	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
> > -	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
> > -		ret = dev_power_domain_on(dev);
> > -		if (ret)
> > -			goto fail;
> > -	}
> > +	    !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF))
> > +		dev_power_domain_on(dev);
> >  
> >  	ret = uclass_pre_probe_device(dev);
> >  	if (ret)
> 
> Adding Lokesh and quoting him from
> http://patchwork.ozlabs.org/patch/1211325/
> 
> "Can you check by not returning on failure here? If yes then check the
> power-domain/driver that is failing. If any driver doesn't expect core
> to enable power-domain then enable DM_FLAG_DEFAULT_PD_CTRL_OFF in the
> respective driver."

I tried, if I'am not returning on failure here. U-Boot boots well and
any logging shows me a return value 0 for dev_power_domain_on(). As soon
as I add the if statement with the goto fail U-Boot is stuck and I don't
see any msg on the uart neither return value for dev_power_domain_on.

So currently I can't tell which power-domain driver cause the issue.

Best Regards,

Oliver

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-03 13:59 ` [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal" Oliver Graute
@ 2020-02-13 17:12   ` Neil Armstrong
  2020-02-14  4:20     ` Lokesh Vutla
  2020-02-17 13:05     ` Anatolij Gustschin
  0 siblings, 2 replies; 21+ messages in thread
From: Neil Armstrong @ 2020-02-13 17:12 UTC (permalink / raw)
  To: u-boot

Hi,

On 03/02/2020 14:59, Oliver Graute wrote:
> The conga-imx8 board isn't booting without this revert. Can someone tell me
> what I need to Do so that this revert is not necessary?
> 
> This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
> ---
>  drivers/core/device-remove.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> index 5c8dc4ad70..586fadee0a 100644
> --- a/drivers/core/device-remove.c
> +++ b/drivers/core/device-remove.c
> @@ -16,7 +16,6 @@
>  #include <dm/uclass.h>
>  #include <dm/uclass-internal.h>
>  #include <dm/util.h>
> -#include <power-domain.h>
>  
>  int device_chld_unbind(struct udevice *dev, struct driver *drv)
>  {
> @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
>  		}
>  	}
>  
> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> -	    (dev != gd->cur_serial_dev))
> -		dev_power_domain_off(dev);
> -
>  	if (flags_remove(flags, drv->flags)) {
>  		device_free(dev);
>  
> 

It also breaks amlogic boards with video, since we can't tell we want
to keep the power domains up after boot, it cuts the power domains and
thus defeats all the goal of u-boot video...

The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
aswell, reverting to manual power domain enable.

Neil

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-13 17:12   ` Neil Armstrong
@ 2020-02-14  4:20     ` Lokesh Vutla
  2020-02-14  9:18       ` Oliver Graute
                         ` (3 more replies)
  2020-02-17 13:05     ` Anatolij Gustschin
  1 sibling, 4 replies; 21+ messages in thread
From: Lokesh Vutla @ 2020-02-14  4:20 UTC (permalink / raw)
  To: u-boot



On 13/02/20 10:42 PM, Neil Armstrong wrote:
> Hi,
> 
> On 03/02/2020 14:59, Oliver Graute wrote:
>> The conga-imx8 board isn't booting without this revert. Can someone tell me
>> what I need to Do so that this revert is not necessary?

Can you give more details on where the failure is happening?(logs would really
help).

>>
>> This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
>> ---
>>  drivers/core/device-remove.c | 5 -----
>>  1 file changed, 5 deletions(-)
>>
>> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
>> index 5c8dc4ad70..586fadee0a 100644
>> --- a/drivers/core/device-remove.c
>> +++ b/drivers/core/device-remove.c
>> @@ -16,7 +16,6 @@
>>  #include <dm/uclass.h>
>>  #include <dm/uclass-internal.h>
>>  #include <dm/util.h>
>> -#include <power-domain.h>
>>  
>>  int device_chld_unbind(struct udevice *dev, struct driver *drv)
>>  {
>> @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
>>  		}
>>  	}
>>  
>> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
>> -	    (dev != gd->cur_serial_dev))
>> -		dev_power_domain_off(dev);
>> -
>>  	if (flags_remove(flags, drv->flags)) {
>>  		device_free(dev);
>>  
>>
> 
> It also breaks amlogic boards with video, since we can't tell we want
> to keep the power domains up after boot, it cuts the power domains and
> thus defeats all the goal of u-boot video..
> The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
> aswell, reverting to manual power domain enable.

This doesn't mean U-boot must leave the all power-domains un handled before
jumping to kernel. Please use DM_FLAG_DEFAULT_PD_CTRL_OFF in you driver and
enable power_domain in your probe. Your case is exactly the reason why
DM_FLAG_DEFAULT_PD_CTRL_OFF is introduced.

Thanks and regards,
Lokesh

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  4:20     ` Lokesh Vutla
@ 2020-02-14  9:18       ` Oliver Graute
  2020-02-14  9:30         ` Lokesh Vutla
  2020-02-14 10:01       ` Anatolij Gustschin
                         ` (2 subsequent siblings)
  3 siblings, 1 reply; 21+ messages in thread
From: Oliver Graute @ 2020-02-14  9:18 UTC (permalink / raw)
  To: u-boot

On 14/02/20, Lokesh Vutla wrote:
> 
> 
> On 13/02/20 10:42 PM, Neil Armstrong wrote:
> > Hi,
> > 
> > On 03/02/2020 14:59, Oliver Graute wrote:
> >> The conga-imx8 board isn't booting without this revert. Can someone tell me
> >> what I need to Do so that this revert is not necessary?
> 
> Can you give more details on where the failure is happening?(logs would really
> help).

without that revert patch u-boot is stuck at "Starting kernel ..."
Is there a way to get more details here? currently I don't know howto
debug that power-domain stuff deeper.

Bytes transferred = 27030016 (19c7200 hex)
Using ethernet at 5b040000 device
TFTP from server 10.200.134.119; our IP address is 10.200.134.121
Filename 'imx8qm-cgt-qmx8.dtb'.
Load address: 0x83000000
Loading: #####
         2.5 MiB/s
done
Bytes transferred = 21224 (52e8 hex)
## Flattened Device Tree blob at 83000000
   Booting using the fdt blob at 0x83000000
   Using Device Tree in place at 0000000083000000, end 00000000830082e7

Starting kernel ...

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  9:18       ` Oliver Graute
@ 2020-02-14  9:30         ` Lokesh Vutla
  2020-02-14 10:30           ` Oliver Graute
  0 siblings, 1 reply; 21+ messages in thread
From: Lokesh Vutla @ 2020-02-14  9:30 UTC (permalink / raw)
  To: u-boot



On 14/02/20 2:48 PM, Oliver Graute wrote:
> On 14/02/20, Lokesh Vutla wrote:
>>
>>
>> On 13/02/20 10:42 PM, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 03/02/2020 14:59, Oliver Graute wrote:
>>>> The conga-imx8 board isn't booting without this revert. Can someone tell me
>>>> what I need to Do so that this revert is not necessary?
>>
>> Can you give more details on where the failure is happening?(logs would really
>> help).
> 
> without that revert patch u-boot is stuck at "Starting kernel ..."
> Is there a way to get more details here? currently I don't know howto
> debug that power-domain stuff deeper.

Can you enable debug prints in:
- drivers/power/domain/power-domain-uclass.c
- drivers/power/domain/imx8-power-domain*.c

and provide the logs? this will help which power-domain is causing the issue.

Thanks and regards,
Lokesh

> 
> Bytes transferred = 27030016 (19c7200 hex)
> Using ethernet at 5b040000 device
> TFTP from server 10.200.134.119; our IP address is 10.200.134.121
> Filename 'imx8qm-cgt-qmx8.dtb'.
> Load address: 0x83000000
> Loading: #####
>          2.5 MiB/s
> done
> Bytes transferred = 21224 (52e8 hex)
> ## Flattened Device Tree blob at 83000000
>    Booting using the fdt blob at 0x83000000
>    Using Device Tree in place at 0000000083000000, end 00000000830082e7
> 
> Starting kernel ...
> 
> Best regards,
> 
> Oliver
> 

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  4:20     ` Lokesh Vutla
  2020-02-14  9:18       ` Oliver Graute
@ 2020-02-14 10:01       ` Anatolij Gustschin
  2020-02-14 10:14         ` Anatolij Gustschin
                           ` (2 more replies)
  2020-02-17  8:55       ` Neil Armstrong
  2020-02-17 13:17       ` Anatolij Gustschin
  3 siblings, 3 replies; 21+ messages in thread
From: Anatolij Gustschin @ 2020-02-14 10:01 UTC (permalink / raw)
  To: u-boot

On Fri, 14 Feb 2020 09:50:54 +0530
Lokesh Vutla lokeshvutla at ti.com wrote:

> On 13/02/20 10:42 PM, Neil Armstrong wrote:
> > Hi,
> > 
> > On 03/02/2020 14:59, Oliver Graute wrote:  
> >> The conga-imx8 board isn't booting without this revert. Can someone tell me
> >> what I need to Do so that this revert is not necessary?  
> 
> Can you give more details on where the failure is happening?(logs would really
> help).

On i.MX8QXP based SoM running U-Boot v2020.04-rc2 with below patch the
v4.14.98 kernel from NXP BSP boots:

diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index 65c8ac1a7e..cf79a12f42 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/mach-imx/imx8/fdt.c
@@ -280,7 +280,9 @@ int ft_system_setup(void *blob, bd_t *bd)
 {
 	int ret;
 
+	/*
 	update_fdt_with_owned_resources(blob);
+	*/
 
 	if (is_imx8qm()) {
 		ret = config_smmu_fdt(blob);

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 444e34b492..a218f481b5 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -194,9 +194,18 @@ int device_remove(struct udevice *dev, uint flags)
 		}
 	}
 
-	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
-	    (dev != gd->cur_serial_dev))
+	if (!(dev->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
+	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
+	    (dev != gd->cur_serial_dev)) {
+		dm_warn("%s: OFF '%s', uclass pd %d\n",
+			__func__, dev->name,
+			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
 		dev_power_domain_off(dev);
+	} else {
+		dm_warn("%s: '%s', uclass pd %d\n",
+			__func__, dev->name,
+			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
+	}
 
 	if (flags_remove(flags, drv->flags)) {
 		device_free(dev);

The generated debug log:

Starting kernel ...

device_remove: OFF 'clk', uclass pd 0
device_remove: OFF 'gpioledsgrp', uclass pd 0
device_remove: OFF 'lpi2c0grp', uclass pd 0
device_remove: OFF 'lpi2c1grp', uclass pd 0
device_remove: OFF 'lpuart2grp', uclass pd 0
device_remove: OFF 'usdhc1grp', uclass pd 0
device_remove: OFF 'fec2grp', uclass pd 0
device_remove: OFF 'imx8qxp-som', uclass pd 0
device_remove: OFF 'iomuxc', uclass pd 0
device_remove: OFF 'mu at 5d1c0000', uclass pd 0
device_remove: 'lsio_gpio0', uclass pd 1
device_remove: 'lsio_gpio1', uclass pd 1
device_remove: 'lsio_gpio3', uclass pd 1
device_remove: 'lsio_gpio4', uclass pd 1
device_remove: 'lsio_gpio5', uclass pd 1
device_remove: 'lsio_power_domain', uclass pd 1
device_remove: 'conn_sdhc0', uclass pd 1
device_remove: 'conn_enet1', uclass pd 1
device_remove: 'connectivity_power_domain', uclass pd 1
device_remove: 'dma_lpi2c0', uclass pd 1
device_remove: 'dma_lpi2c1', uclass pd 1
device_remove: 'dma_lpuart2', uclass pd 1
device_remove: 'dma_power_domain', uclass pd 1
device_remove: OFF 'imx8qx-pm', uclass pd 0
device_remove: OFF 'generic_50', uclass pd 0
device_remove: OFF 'i2c at 5a800000', uclass pd 0
device_remove: 'dma_lpi2c0', uclass pd 1
device_remove: OFF 'i2c at 5a810000', uclass pd 0
device_remove: 'dma_lpi2c1', uclass pd 1
device_remove: OFF 'gpio at 5d080000', uclass pd 0
device_remove: 'lsio_gpio0', uclass pd 1
device_remove: OFF 'gpio at 5d090000', uclass pd 0
device_remove: 'lsio_gpio1', uclass pd 1
device_remove: OFF 'gpio at 5d0b0000', uclass pd 0
device_remove: 'lsio_gpio3', uclass pd 1
device_remove: OFF 'gpio at 5d0c0000', uclass pd 0
device_remove: 'lsio_gpio4', uclass pd 1
device_remove: OFF 'gpio at 5d0d0000', uclass pd 0
device_remove: 'lsio_gpio5', uclass pd 1
device_remove: 'serial at 5a080000', uclass pd 0
device_remove: OFF 'usdhc at 5b010000.blk', uclass pd 0
device_remove: OFF 'usdhc at 5b010000', uclass pd 0
device_remove: 'conn_sdhc0', uclass pd 1
device_remove: OFF 'ethernet at 5b050000', uclass pd 0
device_remove: 'conn_enet1', uclass pd 1
device_remove: OFF 'run', uclass pd 0
device_remove: OFF 'flt', uclass pd 0
device_remove: OFF 'svc', uclass pd 0
device_remove: OFF 'com1_tx', uclass pd 0
device_remove: OFF 'com1_rx', uclass pd 0
device_remove: OFF 'com2_tx', uclass pd 0
device_remove: OFF 'com2_rx', uclass pd 0
device_remove: OFF 'cloud', uclass pd 0
device_remove: OFF 'wlan', uclass pd 0
device_remove: OFF 'dbg1', uclass pd 0
device_remove: OFF 'dbg2', uclass pd 0
device_remove: OFF 'dbg3', uclass pd 0
device_remove: OFF 'dbg4', uclass pd 0
device_remove: OFF 'leds', uclass pd 0
device_remove: OFF 'root_driver', uclass pd 0

My original patch v3 had this additional condition for power domain off:

 (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN)

This was dropped in the merged patch for some reason, I don't know why.

--
Anatolij

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14 10:01       ` Anatolij Gustschin
@ 2020-02-14 10:14         ` Anatolij Gustschin
  2020-02-14 10:22         ` Lokesh Vutla
  2020-02-14 10:50         ` Oliver Graute
  2 siblings, 0 replies; 21+ messages in thread
From: Anatolij Gustschin @ 2020-02-14 10:14 UTC (permalink / raw)
  To: u-boot

On Fri, 14 Feb 2020 11:01:54 +0100
Anatolij Gustschin agust at denx.de wrote:
...
> My original patch v3 had this additional condition for power domain off:
> 
>  (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN)

The debug log generated without the above condition:

device_remove: OFF 'clk', uclass pd 0
device_remove: OFF 'gpioledsgrp', uclass pd 0
device_remove: OFF 'lpi2c0grp', uclass pd 0
device_remove: OFF 'lpi2c1grp', uclass pd 0
device_remove: OFF 'lpuart2grp', uclass pd 0
device_remove: OFF 'usdhc1grp', uclass pd 0
device_remove: OFF 'fec2grp', uclass pd 0
device_remove: OFF 'imx8qxp-som', uclass pd 0
device_remove: OFF 'iomuxc', uclass pd 0
device_remove: OFF 'mu at 5d1c0000', uclass pd 0
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
device_remove: OFF 'lsio_gpio0', uclass pd 1
...
Here it is stuck in an endless recursion for lsio_gpio0 device remove.

--
Anatolij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14 10:01       ` Anatolij Gustschin
  2020-02-14 10:14         ` Anatolij Gustschin
@ 2020-02-14 10:22         ` Lokesh Vutla
  2020-02-14 10:50         ` Oliver Graute
  2 siblings, 0 replies; 21+ messages in thread
From: Lokesh Vutla @ 2020-02-14 10:22 UTC (permalink / raw)
  To: u-boot



On 14/02/20 3:31 PM, Anatolij Gustschin wrote:
> On Fri, 14 Feb 2020 09:50:54 +0530
> Lokesh Vutla lokeshvutla at ti.com wrote:
> 
>> On 13/02/20 10:42 PM, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 03/02/2020 14:59, Oliver Graute wrote:  
>>>> The conga-imx8 board isn't booting without this revert. Can someone tell me
>>>> what I need to Do so that this revert is not necessary?  
>>
>> Can you give more details on where the failure is happening?(logs would really
>> help).
> 
> On i.MX8QXP based SoM running U-Boot v2020.04-rc2 with below patch the
> v4.14.98 kernel from NXP BSP boots:
> 
> diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
> index 65c8ac1a7e..cf79a12f42 100644
> --- a/arch/arm/mach-imx/imx8/fdt.c
> +++ b/arch/arm/mach-imx/imx8/fdt.c
> @@ -280,7 +280,9 @@ int ft_system_setup(void *blob, bd_t *bd)
>  {
>  	int ret;
>  
> +	/*
>  	update_fdt_with_owned_resources(blob);
> +	*/
>  
>  	if (is_imx8qm()) {
>  		ret = config_smmu_fdt(blob);
> 
> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> index 444e34b492..a218f481b5 100644
> --- a/drivers/core/device-remove.c
> +++ b/drivers/core/device-remove.c
> @@ -194,9 +194,18 @@ int device_remove(struct udevice *dev, uint flags)
>  		}
>  	}
>  
> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> -	    (dev != gd->cur_serial_dev))
> +	if (!(dev->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> +	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
> +	    (dev != gd->cur_serial_dev)) {
> +		dm_warn("%s: OFF '%s', uclass pd %d\n",
> +			__func__, dev->name,
> +			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
>  		dev_power_domain_off(dev);
> +	} else {
> +		dm_warn("%s: '%s', uclass pd %d\n",
> +			__func__, dev->name,
> +			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
> +	}
>  
>  	if (flags_remove(flags, drv->flags)) {
>  		device_free(dev);
> 
> The generated debug log:
> 
> Starting kernel ...
> 
> device_remove: OFF 'clk', uclass pd 0
> device_remove: OFF 'gpioledsgrp', uclass pd 0
> device_remove: OFF 'lpi2c0grp', uclass pd 0
> device_remove: OFF 'lpi2c1grp', uclass pd 0
> device_remove: OFF 'lpuart2grp', uclass pd 0
> device_remove: OFF 'usdhc1grp', uclass pd 0
> device_remove: OFF 'fec2grp', uclass pd 0
> device_remove: OFF 'imx8qxp-som', uclass pd 0
> device_remove: OFF 'iomuxc', uclass pd 0
> device_remove: OFF 'mu at 5d1c0000', uclass pd 0
> device_remove: 'lsio_gpio0', uclass pd 1
> device_remove: 'lsio_gpio1', uclass pd 1
> device_remove: 'lsio_gpio3', uclass pd 1
> device_remove: 'lsio_gpio4', uclass pd 1
> device_remove: 'lsio_gpio5', uclass pd 1
> device_remove: 'lsio_power_domain', uclass pd 1
> device_remove: 'conn_sdhc0', uclass pd 1
> device_remove: 'conn_enet1', uclass pd 1
> device_remove: 'connectivity_power_domain', uclass pd 1
> device_remove: 'dma_lpi2c0', uclass pd 1
> device_remove: 'dma_lpi2c1', uclass pd 1
> device_remove: 'dma_lpuart2', uclass pd 1
> device_remove: 'dma_power_domain', uclass pd 1
> device_remove: OFF 'imx8qx-pm', uclass pd 0
> device_remove: OFF 'generic_50', uclass pd 0
> device_remove: OFF 'i2c at 5a800000', uclass pd 0
> device_remove: 'dma_lpi2c0', uclass pd 1
> device_remove: OFF 'i2c at 5a810000', uclass pd 0
> device_remove: 'dma_lpi2c1', uclass pd 1
> device_remove: OFF 'gpio at 5d080000', uclass pd 0
> device_remove: 'lsio_gpio0', uclass pd 1
> device_remove: OFF 'gpio at 5d090000', uclass pd 0
> device_remove: 'lsio_gpio1', uclass pd 1
> device_remove: OFF 'gpio at 5d0b0000', uclass pd 0
> device_remove: 'lsio_gpio3', uclass pd 1
> device_remove: OFF 'gpio at 5d0c0000', uclass pd 0
> device_remove: 'lsio_gpio4', uclass pd 1
> device_remove: OFF 'gpio at 5d0d0000', uclass pd 0
> device_remove: 'lsio_gpio5', uclass pd 1
> device_remove: 'serial at 5a080000', uclass pd 0
> device_remove: OFF 'usdhc at 5b010000.blk', uclass pd 0
> device_remove: OFF 'usdhc at 5b010000', uclass pd 0
> device_remove: 'conn_sdhc0', uclass pd 1
> device_remove: OFF 'ethernet at 5b050000', uclass pd 0
> device_remove: 'conn_enet1', uclass pd 1
> device_remove: OFF 'run', uclass pd 0
> device_remove: OFF 'flt', uclass pd 0
> device_remove: OFF 'svc', uclass pd 0
> device_remove: OFF 'com1_tx', uclass pd 0
> device_remove: OFF 'com1_rx', uclass pd 0
> device_remove: OFF 'com2_tx', uclass pd 0
> device_remove: OFF 'com2_rx', uclass pd 0
> device_remove: OFF 'cloud', uclass pd 0
> device_remove: OFF 'wlan', uclass pd 0
> device_remove: OFF 'dbg1', uclass pd 0
> device_remove: OFF 'dbg2', uclass pd 0
> device_remove: OFF 'dbg3', uclass pd 0
> device_remove: OFF 'dbg4', uclass pd 0
> device_remove: OFF 'leds', uclass pd 0
> device_remove: OFF 'root_driver', uclass pd 0
> 
> My original patch v3 had this additional condition for power domain off:
> 
>  (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN)
> 
> This was dropped in the merged patch for some reason, I don't know why.

power_domain_get_by_index() handles this case. It tries to read power-domains in
the node, if not found it will fall back. I am not sure why it should be an
issue in this case.

I am not saying the above condition is wrong but it is already taken care the
power_domain_off.

Thanks and regards,
Lokesh

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  9:30         ` Lokesh Vutla
@ 2020-02-14 10:30           ` Oliver Graute
  0 siblings, 0 replies; 21+ messages in thread
From: Oliver Graute @ 2020-02-14 10:30 UTC (permalink / raw)
  To: u-boot

On 14/02/20, Lokesh Vutla wrote:
> 
> 
> On 14/02/20 2:48 PM, Oliver Graute wrote:
> > On 14/02/20, Lokesh Vutla wrote:
> >>
> >>
> >> On 13/02/20 10:42 PM, Neil Armstrong wrote:
> >>> Hi,
> >>>
> >>> On 03/02/2020 14:59, Oliver Graute wrote:
> >>>> The conga-imx8 board isn't booting without this revert. Can someone tell me
> >>>> what I need to Do so that this revert is not necessary?
> >>
> >> Can you give more details on where the failure is happening?(logs would really
> >> help).
> > 
> > without that revert patch u-boot is stuck at "Starting kernel ..."
> > Is there a way to get more details here? currently I don't know howto
> > debug that power-domain stuff deeper.
> 
> Can you enable debug prints in:
> - drivers/power/domain/power-domain-uclass.c
> - drivers/power/domain/imx8-power-domain*.c
> 
> and provide the logs? this will help which power-domain is causing the issue.

thx a lot that helped. So it looks like the board is in some endless
loop with lsio_power_domain.

here the log:

Loading: #####
         2 MiB/s
done
Bytes transferred = 21224 (52e8 hex)
## Flattened Device Tree blob at 83000000
   Booting using the fdt blob at 0x83000000
   Using Device Tree in place at 0000000083000000, end 00000000830082e7

Starting kernel ...

power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdae0058)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdae0058)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdae0058)
power_domain_off() power_domain_off(power_domain=00000000fdae0058)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdae0058)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadff48)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadff48)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadff48)
power_domain_off() power_domain_off(power_domain=00000000fdadff48)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadff48)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadfe38)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadfe38)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadfe38)
power_domain_off() power_domain_off(power_domain=00000000fdadfe38)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadfe38)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadfd28)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadfd28)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadfd28)
power_domain_off() power_domain_off(power_domain=00000000fdadfd28)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadfd28)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadfc18)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadfc18)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadfc18)
power_domain_off() power_domain_off(power_domain=00000000fdadfc18)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadfc18)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadfb08)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadfb08)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadfb08)
power_domain_off() power_domain_off(power_domain=00000000fdadfb08)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadfb08)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf9f8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf9f8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf9f8)
power_domain_off() power_domain_off(power_domain=00000000fdadf9f8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf9f8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf8e8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf8e8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf8e8)
power_domain_off() power_domain_off(power_domain=00000000fdadf8e8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf8e8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf7d8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf7d8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf7d8)
power_domain_off() power_domain_off(power_domain=00000000fdadf7d8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf7d8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf6c8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf6c8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf6c8)
power_domain_off() power_domain_off(power_domain=00000000fdadf6c8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf6c8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf5b8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf5b8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf5b8)
power_domain_off() power_domain_off(power_domain=00000000fdadf5b8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf5b8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf4a8)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdadf4a8)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdadf4a8)
power_domain_off() power_domain_off(power_domain=00000000fdadf4a8)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdadf4a8)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_power_domain, state_on 1
imx8_power_domain_off() Can't power off the node of dev lsio_power_domain, ret = -1
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdae88f0, power_domain=00000000fdadf398)

---snipped off--

Best Regards,

Oliver

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14 10:01       ` Anatolij Gustschin
  2020-02-14 10:14         ` Anatolij Gustschin
  2020-02-14 10:22         ` Lokesh Vutla
@ 2020-02-14 10:50         ` Oliver Graute
  2 siblings, 0 replies; 21+ messages in thread
From: Oliver Graute @ 2020-02-14 10:50 UTC (permalink / raw)
  To: u-boot

On 14/02/20, Anatolij Gustschin wrote:
> On Fri, 14 Feb 2020 09:50:54 +0530
> Lokesh Vutla lokeshvutla at ti.com wrote:
> 
> > On 13/02/20 10:42 PM, Neil Armstrong wrote:
> > > Hi,
> > > 
> > > On 03/02/2020 14:59, Oliver Graute wrote:  
> > >> The conga-imx8 board isn't booting without this revert. Can someone tell me
> > >> what I need to Do so that this revert is not necessary?  
> > 
> > Can you give more details on where the failure is happening?(logs would really
> > help).
> 
> On i.MX8QXP based SoM running U-Boot v2020.04-rc2 with below patch the
> v4.14.98 kernel from NXP BSP boots:
> 
> diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
> index 65c8ac1a7e..cf79a12f42 100644
> --- a/arch/arm/mach-imx/imx8/fdt.c
> +++ b/arch/arm/mach-imx/imx8/fdt.c
> @@ -280,7 +280,9 @@ int ft_system_setup(void *blob, bd_t *bd)
>  {
>  	int ret;
>  
> +	/*
>  	update_fdt_with_owned_resources(blob);
> +	*/
>  
>  	if (is_imx8qm()) {
>  		ret = config_smmu_fdt(blob);
> 
> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> index 444e34b492..a218f481b5 100644
> --- a/drivers/core/device-remove.c
> +++ b/drivers/core/device-remove.c
> @@ -194,9 +194,18 @@ int device_remove(struct udevice *dev, uint flags)
>  		}
>  	}
>  
> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> -	    (dev != gd->cur_serial_dev))
> +	if (!(dev->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> +	    (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
> +	    (dev != gd->cur_serial_dev)) {
> +		dm_warn("%s: OFF '%s', uclass pd %d\n",
> +			__func__, dev->name,
> +			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
>  		dev_power_domain_off(dev);
> +	} else {
> +		dm_warn("%s: '%s', uclass pd %d\n",
> +			__func__, dev->name,
> +			device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN);
> +	}
>  
>  	if (flags_remove(flags, drv->flags)) {
>  		device_free(dev);
> 
> The generated debug log:

thx I did the same as Anatolij on my imx8qm congatec board:

done
Bytes transferred = 21224 (52e8 hex)
## Flattened Device Tree blob at 83000000
   Booting using the fdt blob at 0x83000000
   Using Device Tree in place at 0000000083000000, end 00000000830082e7

Starting kernel ...

device_remove: OFF 'clk', uclass pd 0
device_remove: OFF 'hoggrp', uclass pd 0
device_remove: OFF 'fec1grp', uclass pd 0
device_remove: OFF 'lpuart0grp', uclass pd 0
device_remove: OFF 'usdhc1grp', uclass pd 0
device_remove: OFF 'usdhc2grpgpio', uclass pd 0
device_remove: OFF 'usdhc2grp', uclass pd 0
device_remove: OFF 'usdhc3grpgpio', uclass pd 0
device_remove: OFF 'usdhc3grp', uclass pd 0
device_remove: OFF 'imx8qm-qmx8', uclass pd 0
device_remove: OFF 'iomuxc', uclass pd 0
device_remove: OFF 'mu at 5d1c0000', uclass pd 0
device_remove: 'lsio_gpio0', uclass pd 1
device_remove: 'lsio_gpio1', uclass pd 1
device_remove: 'lsio_gpio2', uclass pd 1
device_remove: 'lsio_gpio4', uclass pd 1
device_remove: 'lsio_gpio5', uclass pd 1
device_remove: 'lsio_power_domain', uclass pd 1
device_remove: 'conn_sdhc0', uclass pd 1
device_remove: 'conn_sdhc1', uclass pd 1
device_remove: 'conn_sdhc2', uclass pd 1
device_remove: 'conn_enet0', uclass pd 1
device_remove: 'connectivity_power_domain', uclass pd 1
device_remove: 'dma_lpuart0', uclass pd 1
device_remove: 'dma_power_domain', uclass pd 1
device_remove: OFF 'imx8qm-pm', uclass pd 0
device_remove: OFF 'gpio at 5d080000', uclass pd 0
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdaea0f0, power_domain=00000000fdae0118)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdae0118)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdae0118)
power_domain_off() power_domain_off(power_domain=00000000fdae0118)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdae0118)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_gpio0, state_on 1
imx8_power_domain_off_node() lsio_gpio0 is powered off
imx8_power_domain_off_parentnodes() imx8_power_domain_off_parentnodes, lsio_power_domain, state_on 1
imx8_power_domain_off_parentnodes() sibling lsio_gpio1, state_on 1
device_remove: 'lsio_gpio0', uclass pd 1
device_remove: OFF 'gpio at 5d090000', uclass pd 0
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdaea1d0, power_domain=00000000fdae0118)
imx8_power_domain_of_xlate() imx8_power_domain_of_xlate(power_domain=00000000fdae0118)
imx8_power_domain_request() imx8_power_domain_request(power_domain=00000000fdae0118)
power_domain_off() power_domain_off(power_domain=00000000fdae0118)
imx8_power_domain_off() imx8_power_domain_off(power_domain=00000000fdae0118)
imx8_power_domain_off_node() imx8_power_domain_off_node, lsio_gpio1, state_on 1
imx8_power_domain_off_node() lsio_gpio1 is powered off
imx8_power_domain_off_parentnodes() imx8_power_domain_off_parentnodes, lsio_power_domain, state_on 1
imx8_power_domain_off_parentnodes() sibling lsio_gpio2, state_on 1
device_remove: 'lsio_gpio1', uclass pd 1
device_remove: OFF 'gpio at 5d0a0000', uclass pd 0
power_domain_get_by_index() power_domain_get_by_index(dev=00000000fdaea2b0, power_domain=00000000fdae0118)

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  4:20     ` Lokesh Vutla
  2020-02-14  9:18       ` Oliver Graute
  2020-02-14 10:01       ` Anatolij Gustschin
@ 2020-02-17  8:55       ` Neil Armstrong
  2020-02-17 13:17       ` Anatolij Gustschin
  3 siblings, 0 replies; 21+ messages in thread
From: Neil Armstrong @ 2020-02-17  8:55 UTC (permalink / raw)
  To: u-boot

On 14/02/2020 05:20, Lokesh Vutla wrote:
> 
> 
> On 13/02/20 10:42 PM, Neil Armstrong wrote:
>> Hi,
>>
>> On 03/02/2020 14:59, Oliver Graute wrote:
>>> The conga-imx8 board isn't booting without this revert. Can someone tell me
>>> what I need to Do so that this revert is not necessary?
> 
> Can you give more details on where the failure is happening?(logs would really
> help).
> 
>>>
>>> This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
>>> ---
>>>  drivers/core/device-remove.c | 5 -----
>>>  1 file changed, 5 deletions(-)
>>>
>>> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
>>> index 5c8dc4ad70..586fadee0a 100644
>>> --- a/drivers/core/device-remove.c
>>> +++ b/drivers/core/device-remove.c
>>> @@ -16,7 +16,6 @@
>>>  #include <dm/uclass.h>
>>>  #include <dm/uclass-internal.h>
>>>  #include <dm/util.h>
>>> -#include <power-domain.h>
>>>  
>>>  int device_chld_unbind(struct udevice *dev, struct driver *drv)
>>>  {
>>> @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
>>>  		}
>>>  	}
>>>  
>>> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
>>> -	    (dev != gd->cur_serial_dev))
>>> -		dev_power_domain_off(dev);
>>> -
>>>  	if (flags_remove(flags, drv->flags)) {
>>>  		device_free(dev);
>>>  
>>>
>>
>> It also breaks amlogic boards with video, since we can't tell we want
>> to keep the power domains up after boot, it cuts the power domains and
>> thus defeats all the goal of u-boot video..
>> The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
>> aswell, reverting to manual power domain enable.
> 
> This doesn't mean U-boot must leave the all power-domains un handled before
> jumping to kernel. Please use DM_FLAG_DEFAULT_PD_CTRL_OFF in you driver and
> enable power_domain in your probe. Your case is exactly the reason why
> DM_FLAG_DEFAULT_PD_CTRL_OFF is introduced.

This changed the behavior of the power domain core, and this is wrong.

Reverting to manually handling the power domain in the probe defeats the initial
goal of automatic handling of power domain at probe, and the current
DM_FLAG_DEFAULT_PD_CTRL_OF doesn't mean anything, it's not explicit at all,
and doesn't mean the power domain won't be enabled at probe. We must read
the code to understand it.

Please avoid breaking stuff and adding fuzzy flags without a proper behavior.

The use-case of the flag would be to keep the power domain enabled at linux boot
instead of never probing it.

Neil

> 
> Thanks and regards,
> Lokesh
> 

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-13 17:12   ` Neil Armstrong
  2020-02-14  4:20     ` Lokesh Vutla
@ 2020-02-17 13:05     ` Anatolij Gustschin
  2020-02-17 13:37       ` Lokesh Vutla
  1 sibling, 1 reply; 21+ messages in thread
From: Anatolij Gustschin @ 2020-02-17 13:05 UTC (permalink / raw)
  To: u-boot

On Thu, 13 Feb 2020 18:12:12 +0100
Neil Armstrong narmstrong at baylibre.com wrote:

> Hi,
> 
> On 03/02/2020 14:59, Oliver Graute wrote:
> > The conga-imx8 board isn't booting without this revert. Can someone tell me
> > what I need to Do so that this revert is not necessary?
> > 
> > This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
> > ---
> >  drivers/core/device-remove.c | 5 -----
> >  1 file changed, 5 deletions(-)
> > 
> > diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> > index 5c8dc4ad70..586fadee0a 100644
> > --- a/drivers/core/device-remove.c
> > +++ b/drivers/core/device-remove.c
> > @@ -16,7 +16,6 @@
> >  #include <dm/uclass.h>
> >  #include <dm/uclass-internal.h>
> >  #include <dm/util.h>
> > -#include <power-domain.h>
> >  
> >  int device_chld_unbind(struct udevice *dev, struct driver *drv)
> >  {
> > @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
> >  		}
> >  	}
> >  
> > -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> > -	    (dev != gd->cur_serial_dev))
> > -		dev_power_domain_off(dev);
> > -
> >  	if (flags_remove(flags, drv->flags)) {
> >  		device_free(dev);
> >  
> >   
> 
> It also breaks amlogic boards with video, since we can't tell we want
> to keep the power domains up after boot, it cuts the power domains and
> thus defeats all the goal of u-boot video...
> 
> The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
> aswell, reverting to manual power domain enable.

Yes, in some special cases manual power domain enable is required,
this is the reason why this flag has been introduced. This flag is
not for controlling power off for auto-enabled domains.

My original patch v3 [1] suggested another flag DM_FLAG_REMOVE_WITH_PD_ON,
but in the subsequent patch (which was then merged) Lokesh replaced this
with another flag DM_FLAG_DEFAULT_PD_CTRL_OFF for different purpose and
dropped DM_FLAG_REMOVE_WITH_PD_ON.

Unfortunately Lokesh copied the commit message from my patch v3 to
the updated patch without modification and so this merged commit doesn't
correctly describe the code changes. Unfortunately I didn't have
time to properly review and test this merged patch back then.

[1] https://patchwork.ozlabs.org/patch/1140138

--
Anatolij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-14  4:20     ` Lokesh Vutla
                         ` (2 preceding siblings ...)
  2020-02-17  8:55       ` Neil Armstrong
@ 2020-02-17 13:17       ` Anatolij Gustschin
  3 siblings, 0 replies; 21+ messages in thread
From: Anatolij Gustschin @ 2020-02-17 13:17 UTC (permalink / raw)
  To: u-boot

On Fri, 14 Feb 2020 09:50:54 +0530
Lokesh Vutla lokeshvutla at ti.com wrote:

> On 13/02/20 10:42 PM, Neil Armstrong wrote:
> > Hi,
> > 
> > On 03/02/2020 14:59, Oliver Graute wrote:  
> >> The conga-imx8 board isn't booting without this revert. Can someone tell me
> >> what I need to Do so that this revert is not necessary?  
> 
> Can you give more details on where the failure is happening?(logs would really
> help).
> 
> >>
> >> This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
> >> ---
> >>  drivers/core/device-remove.c | 5 -----
> >>  1 file changed, 5 deletions(-)
> >>
> >> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> >> index 5c8dc4ad70..586fadee0a 100644
> >> --- a/drivers/core/device-remove.c
> >> +++ b/drivers/core/device-remove.c
> >> @@ -16,7 +16,6 @@
> >>  #include <dm/uclass.h>
> >>  #include <dm/uclass-internal.h>
> >>  #include <dm/util.h>
> >> -#include <power-domain.h>
> >>  
> >>  int device_chld_unbind(struct udevice *dev, struct driver *drv)
> >>  {
> >> @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
> >>  		}
> >>  	}
> >>  
> >> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
> >> -	    (dev != gd->cur_serial_dev))
> >> -		dev_power_domain_off(dev);
> >> -
> >>  	if (flags_remove(flags, drv->flags)) {
> >>  		device_free(dev);
> >>  
> >>  
> > 
> > It also breaks amlogic boards with video, since we can't tell we want
> > to keep the power domains up after boot, it cuts the power domains and
> > thus defeats all the goal of u-boot video..
> > The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
> > aswell, reverting to manual power domain enable.  
> 
> This doesn't mean U-boot must leave the all power-domains un handled before
> jumping to kernel. Please use DM_FLAG_DEFAULT_PD_CTRL_OFF in you driver and
> enable power_domain in your probe.

No, DM_FLAG_DEFAULT_PD_CTRL_OFF is only for very special cases where
manual power domain handling is required.

> Your case is exactly the reason why
> DM_FLAG_DEFAULT_PD_CTRL_OFF is introduced.

No. For this case the flag DM_FLAG_REMOVE_WITH_PD_ON has been introduced
in my v3 patch, but it was dropped in the merged patch. I've submitted a
new patch for this: http://patchwork.ozlabs.org/patch/1239143

--
Anatolij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal"
  2020-02-17 13:05     ` Anatolij Gustschin
@ 2020-02-17 13:37       ` Lokesh Vutla
  0 siblings, 0 replies; 21+ messages in thread
From: Lokesh Vutla @ 2020-02-17 13:37 UTC (permalink / raw)
  To: u-boot



On 17/02/20 6:35 PM, Anatolij Gustschin wrote:
> On Thu, 13 Feb 2020 18:12:12 +0100
> Neil Armstrong narmstrong at baylibre.com wrote:
> 
>> Hi,
>>
>> On 03/02/2020 14:59, Oliver Graute wrote:
>>> The conga-imx8 board isn't booting without this revert. Can someone tell me
>>> what I need to Do so that this revert is not necessary?
>>>
>>> This reverts commit 52edfed65de967a86983a55c51ba0727090efc43.
>>> ---
>>>  drivers/core/device-remove.c | 5 -----
>>>  1 file changed, 5 deletions(-)
>>>
>>> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
>>> index 5c8dc4ad70..586fadee0a 100644
>>> --- a/drivers/core/device-remove.c
>>> +++ b/drivers/core/device-remove.c
>>> @@ -16,7 +16,6 @@
>>>  #include <dm/uclass.h>
>>>  #include <dm/uclass-internal.h>
>>>  #include <dm/util.h>
>>> -#include <power-domain.h>
>>>  
>>>  int device_chld_unbind(struct udevice *dev, struct driver *drv)
>>>  {
>>> @@ -193,10 +192,6 @@ int device_remove(struct udevice *dev, uint flags)
>>>  		}
>>>  	}
>>>  
>>> -	if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
>>> -	    (dev != gd->cur_serial_dev))
>>> -		dev_power_domain_off(dev);
>>> -
>>>  	if (flags_remove(flags, drv->flags)) {
>>>  		device_free(dev);
>>>  
>>>   
>>
>> It also breaks amlogic boards with video, since we can't tell we want
>> to keep the power domains up after boot, it cuts the power domains and
>> thus defeats all the goal of u-boot video...
>>
>> The problem is DM_FLAG_DEFAULT_PD_CTRL_OFF disables auto power domain on
>> aswell, reverting to manual power domain enable.
> 
> Yes, in some special cases manual power domain enable is required,
> this is the reason why this flag has been introduced. This flag is
> not for controlling power off for auto-enabled domains.
> 
> My original patch v3 [1] suggested another flag DM_FLAG_REMOVE_WITH_PD_ON,
> but in the subsequent patch (which was then merged) Lokesh replaced this
> with another flag DM_FLAG_DEFAULT_PD_CTRL_OFF for different purpose and
> dropped DM_FLAG_REMOVE_WITH_PD_ON.

May be you should see the patch that introduces the specific flag[0] :). Flag
DM_FLAG_REMOVE_WITH_PD_ON[1] does not have any users at that point. Why would we
introduce it without any users?. Even with the patch it would be breaking the
above driver unless explicitly enabled.

IMHO, it is dm core controlling the PD or not. Why will it control just the
enabling part. May be I am wrong, but anyways Ill let Simon and Tom to have a
decision on it.

[0] https://patchwork.ozlabs.org/patch/1168343/
[1] https://patchwork.ozlabs.org/patch/1140138/

Thanks and regards,
Lokesh

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH v2] imx: support for conga-QMX8 board
  2020-02-03 13:59 [PATCH v2] imx: support for conga-QMX8 board Oliver Graute
  2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
  2020-02-03 13:59 ` [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal" Oliver Graute
@ 2020-05-04  7:40 ` Stefano Babic
  2020-05-04 14:25   ` Oliver Graute
  2 siblings, 1 reply; 21+ messages in thread
From: Stefano Babic @ 2020-05-04  7:40 UTC (permalink / raw)
  To: u-boot

Hi Oliver,

this was quite lost under the flood of other patches, sorry for that.
What about to rebase and repost it ?

Regards,
Stefano

On 03.02.20 14:59, Oliver Graute wrote:
> Add i.MX8QM qmx8 congatec board support
> 
> U-Boot 2020.01-00003-g99c15cc616 (Feb 03 2020 - 14:28:07 +0100)
> 
> CPU:   NXP i.MX8QM RevB A53 at 1200 MHz
> 
> Model: Congatec QMX8 Qseven series
> Board: conga-QMX8
> Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF d6451cc
> Boot:  SD2
> DRAM:  6 GiB
> Device 'gpio at 5d090000': seq 0 is in use by 'gpio at 5d080000'
> Device 'gpio at 5d0a0000': seq 1 is in use by 'gpio at 5d090000'
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> In:    serial at 5a060000
> Out:   serial at 5a060000
> Err:   serial at 5a060000
> switch to partitions #0, OK
> mmc2 is current device
> Net:   eth0: ethernet at 5b040000
> Hit any key to stop autoboot:  0
> 
> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Ye Li <ye.li@nxp.com>
> Cc: uboot-imx <uboot-imx@nxp.com>
> ---
> 
> These changes are based on this vendor tree:
> git.congatec.com/imx8_early_access/imx8_uboot_internal.git
> 
> Changes for v2:
>  - added USDHC3_BASE_ADDR
>  - replaced CONFIG_FSL_ESDHC with CONFIG_FSL_ESDHC_IMX
>  - set CONFIG_FEC_MXC_PHYADDR to -1
>  - moved CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to defconfig
> 
>  arch/arm/dts/Makefile               |   1 +
>  arch/arm/dts/imx8qm-cgtqmx8.dts     | 427 +++++++++++++++++++++++++
>  arch/arm/mach-imx/Kconfig           |   2 +-
>  arch/arm/mach-imx/imx8/Kconfig      |   7 +
>  board/congatec/cgtqmx8/Kconfig      |  14 +
>  board/congatec/cgtqmx8/MAINTAINERS  |   6 +
>  board/congatec/cgtqmx8/Makefile     |  11 +
>  board/congatec/cgtqmx8/README       |  15 +
>  board/congatec/cgtqmx8/cgtqmx8.c    | 478 ++++++++++++++++++++++++++++
>  board/congatec/cgtqmx8/imximage.cfg |  21 ++
>  board/congatec/cgtqmx8/spl.c        |  75 +++++
>  board/congatec/common/Kconfig       |  48 +++
>  board/congatec/common/Makefile      |  23 ++
>  board/congatec/common/mmc.c         |  50 +++
>  configs/cgtqmx8_defconfig           |  82 +++++
>  include/configs/cgtqmx8.h           | 196 ++++++++++++
>  16 files changed, 1455 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts
>  create mode 100644 board/congatec/cgtqmx8/Kconfig
>  create mode 100644 board/congatec/cgtqmx8/MAINTAINERS
>  create mode 100644 board/congatec/cgtqmx8/Makefile
>  create mode 100644 board/congatec/cgtqmx8/README
>  create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c
>  create mode 100644 board/congatec/cgtqmx8/imximage.cfg
>  create mode 100644 board/congatec/cgtqmx8/spl.c
>  create mode 100644 board/congatec/common/Kconfig
>  create mode 100644 board/congatec/common/Makefile
>  create mode 100644 board/congatec/common/mmc.c
>  create mode 100644 configs/cgtqmx8_defconfig
>  create mode 100644 include/configs/cgtqmx8.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0127a91a82..4e13640a33 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -664,6 +664,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>  dtb-$(CONFIG_ARCH_IMX8) += \
>  	fsl-imx8qm-apalis.dtb \
>  	fsl-imx8qm-mek.dtb \
> +	imx8qm-cgtqmx8.dtb \
>  	imx8qm-rom7720-a1.dtb \
>  	fsl-imx8qxp-ai_ml.dtb \
>  	fsl-imx8qxp-colibri.dtb \
> diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
> new file mode 100644
> index 0000000000..79a99ddb10
> --- /dev/null
> +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
> @@ -0,0 +1,427 @@
> +// SPDX-License-Identifier:	GPL-2.0+
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + * Copyright 2017 congatec AG
> + * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
> + */
> +
> +/dts-v1/;
> +
> +/* First 128KB is for PSCI ATF. */
> +/memreserve/ 0x80000000 0x00020000;
> +
> +#include "fsl-imx8qm.dtsi"
> +
> +/ {
> +	model = "Congatec QMX8 Qseven series";
> +	compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
> +
> +	chosen {
> +		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
> +		stdout-path = &lpuart0;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg_usdhc2_vmmc: usdhc2_vmmc {
> +			compatible = "regulator-fixed";
> +			regulator-name = "sw-3p3-sd1";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			off-on-delay-us = <3000>;
> +		};
> +
> +		reg_usdhc3_vmmc: usdhc3_vmmc {
> +			compatible = "regulator-fixed";
> +			regulator-name = "sw-3p3-sd2";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +			off-on-delay-us = <3000>;
> +		};
> +	};
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	fsl,magic-packet;
> +	fsl,rgmii_txc_dly;
> +	fsl,rgmii_rxc_dly;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy at 0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <6>;
> +			at803x,eee-disabled;
> +			at803x,vddio-1p8v;
> +		};
> +	};
> +};
> +
> +&gpio2 {
> +	status = "okay";
> +};
> +
> +&gpio5 {
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c0>;
> +	clock-frequency = <100000>;
> +	status = "okay";
> +
> +	rtc_ext: m41t62 at 68 {
> +		compatible = "st,m41t62";
> +		reg = <0x68>;
> +	};
> +};
> +
> +&i2c1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c1>;
> +	status = "okay";
> +
> +	wm8904: wm8904 at 1a {
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;
> +
> +		clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
> +		clock-names = "mclk";
> +		wlf,shared-lrclk;
> +		/* power-domains = <&pd_mclk_out0>; */
> +
> +		assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
> +				<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
> +				<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
> +				<&clk IMX8QM_AUD_MCLKOUT0>;
> +
> +		assigned-clock-rates = <786432000>, <49152000>, <24576000>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx8qm-qmx8 {
> +
> +		pinctrl_hog: hoggrp{
> +			fsl,pins = <
> +				SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09		0x00000021
> +				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x00000021
> +				SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08		0x00000021
> +				SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021
> +				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15			0x00000021
> +				SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31		0x00000021
> +				SC_P_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021
> +				SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00		0x00000021
> +				SC_P_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021
> +			>;
> +		};
> +
> +		pinctrl_fec1: fec1grp {
> +			fsl,pins = <
> +				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
> +				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
> +				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
> +				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
> +				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
> +				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
> +				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
> +				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
> +				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
> +				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
> +				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
> +				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
> +				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
> +				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
> +			>;
> +		};
> +
> +		pinctrl_lpi2c0: lpi2c0grp {
> +			fsl,pins = <
> +				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0xc600004c
> +				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0xc600004c
> +			>;
> +		};
> +
> +		pinctrl_lpi2c1: lpi2c1grp {
> +			fsl,pins = <
> +				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
> +				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
> +			>;
> +		};
> +
> +		pinctrl_lpuart0: lpuart0grp {
> +			fsl,pins = <
> +				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
> +				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
> +			>;
> +		};
> +
> +		pinctrl_lpuart1: lpuart1grp {
> +			fsl,pins = <
> +				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
> +				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
> +				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
> +				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
> +			>;
> +		};
> +
> +		pinctrl_lpuart3: lpuart3grp {
> +			fsl,pins = <
> +				SC_P_M41_GPIO0_00_DMA_UART3_RX		0x06000020
> +				SC_P_M41_GPIO0_01_DMA_UART3_TX		0x06000020
> +			>;
> +		};
> +
> +		pinctrl_mlb: mlbgrp {
> +			fsl,pins = <
> +				SC_P_MLB_SIG_CONN_MLB_SIG		0x21
> +				SC_P_MLB_CLK_CONN_MLB_CLK		0x21
> +				SC_P_MLB_DATA_CONN_MLB_DATA		0x21
> +			>;
> +		};
> +
> +		pinctrl_isl29023: isl29023grp {
> +			fsl,pins = <
> +				SC_P_ADC_IN2_LSIO_GPIO3_IO20		0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc1: usdhc1grp {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +			fsl,pins = <
> +				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
> +				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
> +				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_gpio: usdhc3grpgpio {
> +			fsl,pins = <
> +				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09	0x00000021
> +				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
> +				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
> +				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
> +				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
> +				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
> +				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
> +				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +			fsl,pins = <
> +				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
> +				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
> +				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
> +				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
> +				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
> +				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
> +				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +			fsl,pins = <
> +				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
> +				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
> +				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
> +				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
> +				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
> +				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
> +				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
> +			>;
> +		};
> +/*
> +		pinctrl_usbotg1: usbotg1 {
> +			fsl,pins = <
> +				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
> +			>;
> +		};
> +*/
> +	};
> +};
> +
> +&lpuart0 { /* console */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart0>;
> +	status = "okay";
> +};
> +
> +&lpuart1 { /* Q7 connector */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart1>;
> +	status = "okay";
> +};
> +
> +&pd_dma_lpuart0 {
> +	debug_console;
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +	bus-width = <4>;
> +	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	fsl,tuning-start-tap = <20>;
> +	fsl,tuning-step= <2>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
> +	bus-width = <4>;
> +	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
> +	vmmc-supply = <&reg_usdhc3_vmmc>;
> +	fsl,tuning-start-tap = <20>;
> +	fsl,tuning-step= <2>;
> +	status = "okay";
> +};
> +/*
> +&usbotg1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg1>;
> +	srp-disable;
> +	hnp-disable;
> +	adp-disable;
> +	power-polarity-active-high;
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> +*/
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 4ce2799b72..957d4e6b16 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -23,7 +23,7 @@ config IMX_RDC
>  
>  config IMX_BOOTAUX
>  	bool "Support boot auxiliary core"
> -	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
> +	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8
>  	help
>  	  bootaux [addr] to boot auxiliary core.
>  
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index cdb78afacf..9930ce12ef 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -60,6 +60,12 @@ config TARGET_IMX8QM_MEK
>  	select BOARD_LATE_INIT
>  	select IMX8QM
>  
> +config TARGET_CONGA_QMX8
> +	bool "Support congatec conga-QMX8 board"
> +	select BOARD_LATE_INIT
> +	select SUPPORT_SPL
> +	select IMX8QM
> +
>  config TARGET_IMX8QM_ROM7720_A1
>  	bool "Support i.MX8QM ROM-7720-A1"
>  	select BOARD_LATE_INIT
> @@ -75,6 +81,7 @@ endchoice
>  
>  source "board/freescale/imx8qm_mek/Kconfig"
>  source "board/freescale/imx8qxp_mek/Kconfig"
> +source "board/congatec/cgtqmx8/Kconfig"
>  source "board/advantech/imx8qm_rom7720_a1/Kconfig"
>  source "board/toradex/apalis-imx8/Kconfig"
>  source "board/toradex/colibri-imx8x/Kconfig"
> diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig
> new file mode 100644
> index 0000000000..7273039261
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/Kconfig
> @@ -0,0 +1,14 @@
> +if TARGET_CONGA_QMX8
> +
> +config SYS_BOARD
> +	default "cgtqmx8"
> +
> +config SYS_VENDOR
> +	default "congatec"
> +
> +config SYS_CONFIG_NAME
> +	default "cgtqmx8"
> +
> +source "board/congatec/common/Kconfig"
> +
> +endif
> diff --git a/board/congatec/cgtqmx8/MAINTAINERS b/board/congatec/cgtqmx8/MAINTAINERS
> new file mode 100644
> index 0000000000..a242e534c8
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8QM CGTQMX8 BOARD
> +M:	Oliver Graute <oliver.graute@kococonnector.com>
> +S:	Maintained
> +F:	board/congatec/cgtqmx8/
> +F:	include/configs/cgtqmx8.h
> +F:	configs/cgtqmx8_defconfig
> diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile
> new file mode 100644
> index 0000000000..4b59dbb6bc
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/Makefile
> @@ -0,0 +1,11 @@
> +#
> +# Copyright 2017 NXP
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y += cgtqmx8.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/congatec/cgtqmx8/README b/board/congatec/cgtqmx8/README
> new file mode 100644
> index 0000000000..5724eb89f7
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/README
> @@ -0,0 +1,15 @@
> +Build U-Boot
> +============
> +
> +$ export ATF_LOAD_ADDR=0x80000000
> +$ export BL33_LOAD_ADDR=0x80020000
> +$ make cgtqmx8_defconfig
> +$ make u-boot.bin
> +$ make flash.bin
> +
> +Flash the binary into the SD card
> +=================================
> +
> +Burn the flash.bin binary to SD card offset 32KB:
> +
> +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
> diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
> new file mode 100644
> index 0000000000..921f6184cb
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/cgtqmx8.c
> @@ -0,0 +1,478 @@
> +//SPDX-License-Identifier:	GPL-2.0+
> +/*
> + * Copyright 2018 congatec AG
> + * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
> + */
> +#include <common.h>
> +#include <errno.h>
> +#include <linux/libfdt.h>
> +#include <fsl_esdhc.h>
> +
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <usb.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <power-domain.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +static iomux_cfg_t uart0_pads[] = {
> +	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
> +}
> +
> +int board_early_init_f(void)
> +{
> +	/* sc_ipc_t ipcHndl = 0; */
> +	sc_err_t sciErr = 0;
> +
> +	/* When start u-boot in XEN VM, directly return */
> +	/* if (IS_ENABLED(CONFIG_XEN)) */
> +		/* return 0; */
> +
> +	/* ipcHndl = gd->arch.ipc_channel_handle; */
> +
> +	/* Power up UART0, this is very early while power domain is not working */
> +	sciErr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
> +	if (sciErr != SC_ERR_NONE)
> +		return 0;
> +
> +	/* Set UART0 clock root to 80 MHz */
> +	sc_pm_clock_rate_t rate = 80000000;
> +	sciErr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
> +	if (sciErr != SC_ERR_NONE)
> +		return 0;
> +
> +	/* Enable UART0 clock root */
> +	sciErr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
> +	if (sciErr != SC_ERR_NONE)
> +		return 0;
> +
> +	setup_iomux_uart();
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC_IMX
> +
> +#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
> +#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
> +	{USDHC1_BASE_ADDR, 0, 8},
> +	{USDHC2_BASE_ADDR, 0, 4},
> +	{USDHC3_BASE_ADDR, 0, 4},
> +};
> +
> +static iomux_cfg_t emmc0[] = {
> +	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
> +	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};
> +
> +static iomux_cfg_t usdhc1_sd[] = {
> +	SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
> +	SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};
> +
> +static iomux_cfg_t usdhc2_sd[] = {
> +	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
> +	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	int i, ret;
> +	struct power_domain pd;
> +
> +	/*
> +	 * According to the board_mmc_init() the following map is done:
> +	 * (U-Boot device node)    (Physical Port)
> +	 * mmc0 (onboard eMMC)     USDHC1
> +	 * mmc1 (external SD card) USDHC2
> +	 * mmc2 (onboard ?SD)      USDHC3
> +	 */
> +	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> +		switch (i) {
> +		case 0:
> +		  /* onboard eMMC */
> +			if (!power_domain_lookup_name("conn_sdhc0", &pd))
> +				power_domain_on(&pd);
> +
> +			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
> +			init_clk_usdhc(0);
> +			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +			break;
> +		case 1:
> +		  /* external SD card */
> +			if (!power_domain_lookup_name("conn_sdhc1", &pd))
> +				power_domain_on(&pd);
> +
> +			imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
> +			init_clk_usdhc(1);
> +			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> +			gpio_request(USDHC1_CD_GPIO, "sd1_cd");
> +			gpio_direction_input(USDHC1_CD_GPIO);
> +			break;
> +		case 2:
> +		  /* onboard ?SD */
> +			if (!power_domain_lookup_name("conn_sdhc2", &pd))
> +				power_domain_on(&pd);
> +
> +			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
> +			init_clk_usdhc(2);
> +			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
> +			gpio_direction_input(USDHC2_CD_GPIO);
> +			break;
> +		default:
> +			printf("Warning: you configured more USDHC controllers"
> +				"(%d) than supported by the board\n", i + 1);
> +			return 0;
> +		}
> +		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> +		if (ret) {
> +			printf("Warning: failed to initialize mmc dev %d\n", i);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret = 0;
> +
> +	switch (cfg->esdhc_base) {
> +	case USDHC1_BASE_ADDR:
> +		ret = 1;
> +		break;
> +	case USDHC2_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC1_CD_GPIO);
> +		break;
> +	case USDHC3_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +#endif /* CONFIG_FSL_ESDHC_IMX */
> +
> +#ifdef CONFIG_FEC_MXC
> +#include <miiphy.h>
> +
> +static iomux_cfg_t pad_enet0[] = {
> +	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> +	imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
> +}
> +
> +static void enet_device_phy_reset(void)
> +{
> +	gpio_set_value(FEC0_RESET, 0);
> +	udelay(50);
> +	gpio_set_value(FEC0_RESET, 1);
> +
> +	/* The board has a long delay for this reset to become stable */
> +	mdelay(200);
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +	int ret;
> +	struct power_domain pd0;
> +
> +	/* if (!power_domain_lookup_name(FEC0_PDOMAIN, &pd0)) */
> +	  /* power_domain_on(&pd0); */
> +
> +	setup_iomux_fec();
> +
> +	/* ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, */
> +		/* CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); */
> +	if (ret)
> +		printf("FEC0 MXC: %s:failed\n", __func__);
> +
> +	return ret;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +
> +static int setup_fec(void)
> +{
> +	/* Reset ENET PHY */
> +	enet_device_phy_reset();
> +
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_MXC_GPIO
> +
> +#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
> +#define BKL_ENABLE  IMX_GPIO_NR(1, 7)
> +
> +static iomux_cfg_t board_gpios[] = {
> +	SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +	SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +	SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +};
> +
> +static void board_gpio_init(void)
> +{
> +	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
> +
> +	/* enable LVDS */
> +	gpio_request(LVDS_ENABLE, "lvds_enable");
> +	gpio_direction_output(LVDS_ENABLE, 1);
> +
> +	/* enable backlight */
> +	gpio_request(BKL_ENABLE, "bkl_enable");
> +	gpio_direction_output(BKL_ENABLE, 1);
> +
> +	/* ethernet reset */
> +	gpio_request(FEC0_RESET, "enet0_reset");
> +	gpio_direction_output(FEC0_RESET, 1);
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> +	puts("Board: conga-QMX8\n");
> +
> +	build_info();
> +	print_bootinfo();
> +
> +	/* Note:  After reloc, ipcHndl will no longer be valid.  If handle
> +	 *        returned by sc_ipc_open matches SC_IPC_CH, use this
> +	 *        macro (valid after reloc) for subsequent SCI calls.
> +	 */
> +	/*
> +	if (gd->arch.ipc_channel_handle != SC_IPC_CH) {
> +		printf("\nSCI error! Invalid handle\n");
> +	}
> +	*/
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	if (IS_ENABLED(CONFIG_XEN))
> +		return 0;
> +
> +#ifdef CONFIG_MXC_GPIO
> +	board_gpio_init();
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +	setup_fec();
> +#endif
> +
> +	return 0;
> +}
> +
> +void detail_board_ddr_info(void)
> +{
> +	puts("\nDDR    ");
> +}
> +
> +/*
> + * Board specific reset that is system reset.
> + */
> +void reset_cpu(ulong addr)
> +{
> +/*
> +	puts("SCI reboot request");
> +	sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
> +	while (1)
> +		putc('.');
> +*/
> +	/* TODO */
> +}
> +
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +	return 0;
> +}
> +#endif
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	/* Use EMMC */
> +	if (IS_ENABLED(CONFIG_XEN))
> +		return 0;
> +
> +	return devno;
> +}
> +
> +int mmc_map_to_kernel_blk(int dev_no)
> +{
> +	/* Use EMMC */
> +	if (IS_ENABLED(CONFIG_XEN))
> +		return 0;
> +
> +	return dev_no;
> +}
> +
> +extern uint32_t _end_ofs;
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +	env_set("board_name", "QMX8");
> +	env_set("board_rev", "iMX8QM");
> +#endif
> +
> +	env_set("sec_boot", "no");
> +#ifdef CONFIG_AHAB_BOOT
> +	env_set("sec_boot", "yes");
> +#endif
> +
> +#ifdef CONFIG_ENV_IS_IN_MMC
> +	board_late_mmc_env_init();
> +#endif
> +
> +#ifdef IMX_LOAD_HDMI_FIMRWARE
> +	char *end_of_uboot;
> +	char command[256];
> +	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
> +	end_of_uboot += 9;
> +
> +	/* load hdmitxfw.bin and hdmirxfw.bin*/
> +	memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
> +			IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
> +
> +	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
> +	run_command(command, 0);
> +
> +	sprintf(command, "hdprx load 0x%x",
> +			IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
> +	run_command(command, 0);
> +#endif
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_FSL_FASTBOOT
> +#ifdef CONFIG_ANDROID_RECOVERY
> +int is_recovery_key_pressing(void)
> +{
> +	return 0; /*TODO*/
> +}
> +#endif /*CONFIG_ANDROID_RECOVERY*/
> +#endif /*CONFIG_FSL_FASTBOOT*/
> +
> +/* Only Enable USB3 resources currently */
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg
> new file mode 100644
> index 0000000000..e324c7ca37
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/imximage.cfg
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier:	GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM SD 0x400
> +/* SoC type IMX8QM */
> +SOC_TYPE IMX8QM
> +/* Append seco container image */
> +APPEND mx8qm-ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */
> +IMAGE SCU mx8qm-val-scfw-tcm.bin
> +/* Add ATF image with exec attribute */
> +IMAGE A35 bl31.bin 0x80000000
> +/* Add U-Boot image with load attribute */
> +DATA A35 u-boot-dtb.bin 0x80020000
> diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c
> new file mode 100644
> index 0000000000..95ce9f37e8
> --- /dev/null
> +++ b/board/congatec/cgtqmx8/spl.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <spl.h>
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void spl_board_init(void)
> +{
> +	struct udevice *dev;
> +	int offset;
> +
> +	uclass_find_first_device(UCLASS_MISC, &dev);
> +
> +	for (; dev; uclass_find_next_device(&dev)) {
> +		if (device_probe(dev))
> +			continue;
> +	}
> +
> +	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
> +	while (offset != -FDT_ERR_NOTFOUND) {
> +		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
> +			       NULL, true);
> +		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
> +						       "nxp,imx8-pd");
> +	}
> +
> +	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
> +
> +	for (; dev; uclass_find_next_device(&dev)) {
> +		if (device_probe(dev))
> +			continue;
> +	}
> +
> +	arch_cpu_init();
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	/* Clear global data */
> +	memset((void *)gd, 0, sizeof(gd_t));
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	board_init_r(NULL, 0);
> +}
> diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig
> new file mode 100644
> index 0000000000..5c205bd830
> --- /dev/null
> +++ b/board/congatec/common/Kconfig
> @@ -0,0 +1,48 @@
> +if !ARCH_IMX8M && !ARCH_IMX8
> +
> +config CHAIN_OF_TRUST
> +	depends on !FIT_SIGNATURE && SECURE_BOOT
> +	imply CMD_BLOB
> +	imply CMD_HASH if ARM
> +	select FSL_CAAM
> +	select SPL_BOARD_INIT if (ARM && SPL)
> +	select SHA_HW_ACCEL
> +	select SHA_PROG_HW_ACCEL
> +	select ENV_IS_NOWHERE
> +	select CMD_EXT4 if ARM
> +	select CMD_EXT4_WRITE if ARM
> +	bool
> +	default y
> +
> +config CMD_ESBC_VALIDATE
> +	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
> +	default y if CHAIN_OF_TRUST
> +	help
> +	  This option enables two commands used for secure booting:
> +
> +	    esbc_validate - validate signature using RSA verification
> +	    esbc_halt - put the core in spin loop (Secure Boot Only)
> +
> +endif
> +
> +config VOL_MONITOR_LTC3882_READ
> +	depends on VID
> +	bool "Enable the LTC3882 voltage monitor read"
> +	default n
> +	help
> +	 This option enables LTC3882 voltage monitor read
> +	 functionality. It is used by common VID driver.
> +
> +config VOL_MONITOR_LTC3882_SET
> +	depends on VID
> +	bool "Enable the LTC3882 voltage monitor set"
> +	default n
> +	help
> +	 This option enables LTC3882 voltage monitor set
> +	 functionality. It is used by common VID driver.
> +
> +config USB_TCPC
> +	bool "USB Typec port controller simple driver"
> +	default n
> +	help
> +	  Enable USB type-c port controller (TCPC) driver
> diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile
> new file mode 100644
> index 0000000000..d4ddfbf971
> --- /dev/null
> +++ b/board/congatec/common/Makefile
> @@ -0,0 +1,23 @@
> +#
> +# (C) Copyright 2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +MINIMAL=
> +
> +ifdef CONFIG_SPL_BUILD
> +ifdef CONFIG_SPL_INIT_MINIMAL
> +MINIMAL=y
> +endif
> +endif
> +
> +ifdef MINIMAL
> +# necessary to create built-in.o
> +obj- := __dummy__.o
> +else
> +
> +obj-y				+= mmc.o
> +
> +endif
> diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c
> new file mode 100644
> index 0000000000..9fc3e68728
> --- /dev/null
> +++ b/board/congatec/common/mmc.c
> @@ -0,0 +1,50 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +#include <common.h>
> +#include <asm/arch/sys_proto.h>
> +#include <linux/errno.h>
> +#include <asm/io.h>
> +#include <stdbool.h>
> +#include <mmc.h>
> +
> +static int check_mmc_autodetect(void)
> +{
> +	char *autodetect_str = env_get("mmcautodetect");
> +
> +	if ((autodetect_str != NULL) &&
> +		(strcmp(autodetect_str, "yes") == 0)) {
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +/* This should be defined for each board */
> +__weak int mmc_map_to_kernel_blk(int dev_no)
> +{
> +	return dev_no;
> +}
> +
> +void board_late_mmc_env_init(void)
> +{
> +	char cmd[32];
> +	char mmcblk[32];
> +	u32 dev_no = mmc_get_env_dev();
> +
> +	if (!check_mmc_autodetect())
> +		return;
> +
> +	env_set_ulong("mmcdev", dev_no);
> +
> +	/* Set mmcblk env */
> +	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
> +		mmc_map_to_kernel_blk(dev_no));
> +	env_set("mmcroot", mmcblk);
> +
> +	sprintf(cmd, "mmc dev %d", dev_no);
> +	run_command(cmd, 0);
> +}
> diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
> new file mode 100644
> index 0000000000..21c788cb98
> --- /dev/null
> +++ b/configs/cgtqmx8_defconfig
> @@ -0,0 +1,82 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_TARGET_CONGA_QMX8=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_SPL=y
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg"
> +CONFIG_BOOTDELAY=3
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_LOG=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_POWER_DOMAIN=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_CMD_CPU=y
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_I2C_MUX=y
> +CONFIG_I2C_MUX_PCA954x=y
> +CONFIG_MISC=y
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_SPL_TINY_MEMSET=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
> new file mode 100644
> index 0000000000..51f325e875
> --- /dev/null
> +++ b/include/configs/cgtqmx8.h
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier:	GPL-2.0+
> +/*
> + * Copyright 2017-2018 NXP
> + * Copyright 2018 congatec AG
> + *
> + */
> +
> +#ifndef __CGTQMX8_H
> +#define __CGTQMX8_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_TEXT_BASE				0x0
> +#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
> +
> +#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK		0x013E000
> +#define CONFIG_SPL_BSS_START_ADDR	0x00128000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
> +#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
> +#define CONFIG_MALLOC_F_ADDR		0x00120000
> +
> +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#define CONFIG_OF_EMBED
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +
> +#define CONFIG_SYS_FSL_ESDHC_ADDR       0
> +#define USDHC1_BASE_ADDR                0x5B010000
> +#define USDHC2_BASE_ADDR                0x5B020000
> +#define USDHC3_BASE_ADDR                0x5B030000
> +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +/* FUSE command */
> +#define CONFIG_CMD_FUSE
> +
> +/* Boot M4 */
> +#define M4_BOOT_ENV \
> +	"m4_0_image=m4_0.bin\0" \
> +	"m4_1_image=m4_1.bin\0" \
> +	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
> +	"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
> +	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
> +	"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
> +
> +#ifdef CONFIG_NAND_BOOT
> +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
> +#else
> +#define MFG_NAND_PARTITION ""
> +#endif
> +#define FEC0_RESET IMX_GPIO_NR(2, 5)
> +#define FEC0_PDOMAIN "conn_enet0"
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> +	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> +		"rdinit=/linuxrc " \
> +		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
> +		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
> +		"g_mass_storage.iSerialNumber=\"\" "\
> +		MFG_NAND_PARTITION \
> +		"clk_ignore_unused "\
> +		"\0" \
> +	"initrd_addr=0x83800000\0" \
> +	"initrd_high=0xffffffffffffffff\0" \
> +	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	CONFIG_MFG_ENV_SETTINGS \
> +	M4_BOOT_ENV \
> +	"script=boot.scr\0" \
> +	"image=Image\0" \
> +	"panel=NULL\0" \
> +	"console=ttyLP0\0" \
> +	"fdt_addr=0x83000000\0"			\
> +	"fdt_high=0xffffffffffffffff\0"		\
> +	"boot_fdt=try\0" \
> +	"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
> +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +	"mmcautodetect=yes\0" \
> +	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"echo wait for boot; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs;  " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"booti; " \
> +		"fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loadimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x80280000
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
> +
> +/* Default environment is in SD */
> +#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
> +#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
> +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE		0x80000000
> +#define PHYS_SDRAM_1			0x80000000
> +#define PHYS_SDRAM_2			0x880000000
> +#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
> +#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE			115200
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY		8000000	/* 8MHz */
> +
> +/* Networking */
> +#define CONFIG_FEC_MXC_PHYADDR		-1
> +#define CONFIG_FEC_XCV_TYPE		RGMII
> +#define FEC_QUIRK_ENET_MAC
> +
> +#endif /* __CGTQMX8_H */
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH v2] imx: support for conga-QMX8 board
  2020-05-04  7:40 ` [PATCH v2] imx: support for conga-QMX8 board Stefano Babic
@ 2020-05-04 14:25   ` Oliver Graute
  0 siblings, 0 replies; 21+ messages in thread
From: Oliver Graute @ 2020-05-04 14:25 UTC (permalink / raw)
  To: u-boot

On 04/05/20, Stefano Babic wrote:
> Hi Oliver,
> 
> this was quite lost under the flood of other patches, sorry for that.
> What about to rebase and repost it ?
> 

will rebase and rework that patch, as soon as I'am back in office and
get access to that board again.

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2020-05-04 14:25 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-03 13:59 [PATCH v2] imx: support for conga-QMX8 board Oliver Graute
2020-02-03 13:59 ` [RFC 1/2] hack to boot with 2020.01 Oliver Graute
2020-02-03 17:15   ` Simon Glass
2020-02-04 17:07   ` Tom Rini
2020-02-05  8:48     ` Oliver Graute
2020-02-03 13:59 ` [RFC 2/2] Revert "dm: core: device: switch off power domain after device removal" Oliver Graute
2020-02-13 17:12   ` Neil Armstrong
2020-02-14  4:20     ` Lokesh Vutla
2020-02-14  9:18       ` Oliver Graute
2020-02-14  9:30         ` Lokesh Vutla
2020-02-14 10:30           ` Oliver Graute
2020-02-14 10:01       ` Anatolij Gustschin
2020-02-14 10:14         ` Anatolij Gustschin
2020-02-14 10:22         ` Lokesh Vutla
2020-02-14 10:50         ` Oliver Graute
2020-02-17  8:55       ` Neil Armstrong
2020-02-17 13:17       ` Anatolij Gustschin
2020-02-17 13:05     ` Anatolij Gustschin
2020-02-17 13:37       ` Lokesh Vutla
2020-05-04  7:40 ` [PATCH v2] imx: support for conga-QMX8 board Stefano Babic
2020-05-04 14:25   ` Oliver Graute

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