From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v14 0/7] Refactor Gen11+ SAGV support
Date: Mon, 3 Feb 2020 16:06:25 +0200 [thread overview]
Message-ID: <20200203140636.22529-1-stanislav.lisovskiy@intel.com> (raw)
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (7):
drm/i915: Start passing latency as parameter
drm/i915: Introduce skl_plane_wm_level accessor.
drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Added required new PCode commands
drm/i915: Restrict qgv points which don't have enough bandwidth.
drm/i915: Enable SAGV support for Gen12
drivers/gpu/drm/i915/display/intel_bw.c | 193 ++++--
drivers/gpu/drm/i915/display/intel_bw.h | 24 +
drivers/gpu/drm/i915/display/intel_display.c | 131 +++-
.../drm/i915/display/intel_display_types.h | 8 +
.../gpu/drm/i915/display/intel_global_state.c | 30 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 562 +++++++++++++++---
drivers/gpu/drm/i915/intel_pm.h | 4 +-
drivers/gpu/drm/i915/intel_sideband.c | 2 +
10 files changed, 814 insertions(+), 147 deletions(-)
--
2.24.1.485.gad05a3d8e5
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next reply other threads:[~2020-02-03 14:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-03 14:06 Stanislav Lisovskiy [this message]
2020-02-03 14:07 [Intel-gfx] [PATCH v14 0/7] Refactor Gen11+ SAGV support Stanislav Lisovskiy
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