[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

No engine can be missed when verifying that a rogue user cannot cause a
denial-of-service with nohangcheck.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b1ae65774..2a16357a4 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -42,6 +42,7 @@
 
 #include "igt_dummyload.h"
 #include "igt_sysfs.h"
+#include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
 
@@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
 
 static void nohangcheck_hostile(int i915)
 {
-	int64_t timeout = NSEC_PER_SEC / 2;
-	igt_spin_t *spin;
+	int64_t timeout = MSEC_PER_SEC / 2;
 	igt_hang_t hang;
+	int fence = -1;
 	uint32_t ctx;
 	int err = 0;
 	int dir;
@@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
 
 	igt_require(__enable_hangcheck(dir, false));
 
-	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
+	for_each_physical_engine(e, i915) {
+		igt_spin_t *spin;
+
+		spin = igt_spin_new(i915, ctx,
+				    .engine = eb_ring(e),
+				    .flags = (IGT_SPIN_NO_PREEMPTION |
+					      IGT_SPIN_FENCE_OUT));
+
+		igt_assert(spin->out_fence != -1);
+		if (fence < 0) {
+			fence = spin->out_fence;
+			spin->out_fence = -1;
+		} else {
+			int new;
+
+			new = sync_fence_merge(fence, spin->out_fence);
+			close(fence);
+
+			fence = new;
+		}
+	}
 	gem_context_destroy(i915, ctx);
+	igt_assert(fence != -1);
 
-	if (gem_wait(i915, spin->handle, &timeout)) {
+	if (sync_fence_wait(fence, timeout)) {
 		igt_debugfs_dump(i915, "i915_engine_info");
 		err = -ETIME;
 	}
 
-	igt_spin_free(i915, spin);
-
 	__enable_hangcheck(dir, true);
 	gem_quiescent_gpu(i915);
 	igt_disallow_hang(i915, hang);
@@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
 	igt_assert_f(err == 0,
 		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
 
+	igt_assert_eq(sync_fence_status(fence), -EIO);
+	close(fence);
+
 	close(dir);
 }
 
-- 
2.25.0

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[igt-dev] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

No engine can be missed when verifying that a rogue user cannot cause a
denial-of-service with nohangcheck.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b1ae65774..2a16357a4 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -42,6 +42,7 @@
 
 #include "igt_dummyload.h"
 #include "igt_sysfs.h"
+#include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
 
@@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
 
 static void nohangcheck_hostile(int i915)
 {
-	int64_t timeout = NSEC_PER_SEC / 2;
-	igt_spin_t *spin;
+	int64_t timeout = MSEC_PER_SEC / 2;
 	igt_hang_t hang;
+	int fence = -1;
 	uint32_t ctx;
 	int err = 0;
 	int dir;
@@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
 
 	igt_require(__enable_hangcheck(dir, false));
 
-	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
+	for_each_physical_engine(e, i915) {
+		igt_spin_t *spin;
+
+		spin = igt_spin_new(i915, ctx,
+				    .engine = eb_ring(e),
+				    .flags = (IGT_SPIN_NO_PREEMPTION |
+					      IGT_SPIN_FENCE_OUT));
+
+		igt_assert(spin->out_fence != -1);
+		if (fence < 0) {
+			fence = spin->out_fence;
+			spin->out_fence = -1;
+		} else {
+			int new;
+
+			new = sync_fence_merge(fence, spin->out_fence);
+			close(fence);
+
+			fence = new;
+		}
+	}
 	gem_context_destroy(i915, ctx);
+	igt_assert(fence != -1);
 
-	if (gem_wait(i915, spin->handle, &timeout)) {
+	if (sync_fence_wait(fence, timeout)) {
 		igt_debugfs_dump(i915, "i915_engine_info");
 		err = -ETIME;
 	}
 
-	igt_spin_free(i915, spin);
-
 	__enable_hangcheck(dir, true);
 	gem_quiescent_gpu(i915);
 	igt_disallow_hang(i915, hang);
@@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
 	igt_assert_f(err == 0,
 		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
 
+	igt_assert_eq(sync_fence_status(fence), -EIO);
+	close(fence);
+
 	close(dir);
 }
 
-- 
2.25.0

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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Tvrtko Ursulin]

On 04/02/2020 15:24, Chris Wilson wrote:
> No engine can be missed when verifying that a rogue user cannot cause a
> denial-of-service with nohangcheck.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
>   1 file changed, 29 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> index b1ae65774..2a16357a4 100644
> --- a/tests/i915/gem_ctx_exec.c
> +++ b/tests/i915/gem_ctx_exec.c
> @@ -42,6 +42,7 @@
>   
>   #include "igt_dummyload.h"
>   #include "igt_sysfs.h"
> +#include "sw_sync.h"
>   
>   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
>   
> @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
>   
>   static void nohangcheck_hostile(int i915)
>   {
> -	int64_t timeout = NSEC_PER_SEC / 2;
> -	igt_spin_t *spin;
> +	int64_t timeout = MSEC_PER_SEC / 2;
>   	igt_hang_t hang;
> +	int fence = -1;
>   	uint32_t ctx;
>   	int err = 0;
>   	int dir;
> @@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
>   
>   	igt_require(__enable_hangcheck(dir, false));
>   
> -	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> +	for_each_physical_engine(e, i915) {

I think we shouldn't add more of for_each_physical_engine, but to use 
new style need to think where we are with the overall design of 
iterators and stuff.

> +		igt_spin_t *spin;
> +
> +		spin = igt_spin_new(i915, ctx,
> +				    .engine = eb_ring(e),
> +				    .flags = (IGT_SPIN_NO_PREEMPTION |
> +					      IGT_SPIN_FENCE_OUT));
> +
> +		igt_assert(spin->out_fence != -1);

 >= 0 would be more correct. Or your beloved igt_assert_fd. ;)

> +		if (fence < 0) {
> +			fence = spin->out_fence;
> +			spin->out_fence = -1;
> +		} else {
> +			int new;
> +
> +			new = sync_fence_merge(fence, spin->out_fence);
> +			close(fence);
> +
> +			fence = new;
> +		}
> +	}
>   	gem_context_destroy(i915, ctx);
> +	igt_assert(fence != -1);
>   
> -	if (gem_wait(i915, spin->handle, &timeout)) {
> +	if (sync_fence_wait(fence, timeout)) {
>   		igt_debugfs_dump(i915, "i915_engine_info");
>   		err = -ETIME;
>   	}
>   
> -	igt_spin_free(i915, spin);

Could keep last for completeness.

> -
>   	__enable_hangcheck(dir, true);
>   	gem_quiescent_gpu(i915);
>   	igt_disallow_hang(i915, hang);
> @@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
>   	igt_assert_f(err == 0,
>   		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
>   
> +	igt_assert_eq(sync_fence_status(fence), -EIO);

With composite fences I have a feeling -EIO could mean any fence 
signalled -EIO and we want to check all have, no? At least I hope both 
my assumptions are correct.

> +	close(fence);
> +
>   	close(dir);
>   }
>   
> 

Regards,

Tvrtko
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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Tvrtko Ursulin]

On 04/02/2020 15:24, Chris Wilson wrote:
> No engine can be missed when verifying that a rogue user cannot cause a
> denial-of-service with nohangcheck.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
>   1 file changed, 29 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> index b1ae65774..2a16357a4 100644
> --- a/tests/i915/gem_ctx_exec.c
> +++ b/tests/i915/gem_ctx_exec.c
> @@ -42,6 +42,7 @@
>   
>   #include "igt_dummyload.h"
>   #include "igt_sysfs.h"
> +#include "sw_sync.h"
>   
>   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
>   
> @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
>   
>   static void nohangcheck_hostile(int i915)
>   {
> -	int64_t timeout = NSEC_PER_SEC / 2;
> -	igt_spin_t *spin;
> +	int64_t timeout = MSEC_PER_SEC / 2;
>   	igt_hang_t hang;
> +	int fence = -1;
>   	uint32_t ctx;
>   	int err = 0;
>   	int dir;
> @@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
>   
>   	igt_require(__enable_hangcheck(dir, false));
>   
> -	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> +	for_each_physical_engine(e, i915) {

I think we shouldn't add more of for_each_physical_engine, but to use 
new style need to think where we are with the overall design of 
iterators and stuff.

> +		igt_spin_t *spin;
> +
> +		spin = igt_spin_new(i915, ctx,
> +				    .engine = eb_ring(e),
> +				    .flags = (IGT_SPIN_NO_PREEMPTION |
> +					      IGT_SPIN_FENCE_OUT));
> +
> +		igt_assert(spin->out_fence != -1);

 >= 0 would be more correct. Or your beloved igt_assert_fd. ;)

> +		if (fence < 0) {
> +			fence = spin->out_fence;
> +			spin->out_fence = -1;
> +		} else {
> +			int new;
> +
> +			new = sync_fence_merge(fence, spin->out_fence);
> +			close(fence);
> +
> +			fence = new;
> +		}
> +	}
>   	gem_context_destroy(i915, ctx);
> +	igt_assert(fence != -1);
>   
> -	if (gem_wait(i915, spin->handle, &timeout)) {
> +	if (sync_fence_wait(fence, timeout)) {
>   		igt_debugfs_dump(i915, "i915_engine_info");
>   		err = -ETIME;
>   	}
>   
> -	igt_spin_free(i915, spin);

Could keep last for completeness.

> -
>   	__enable_hangcheck(dir, true);
>   	gem_quiescent_gpu(i915);
>   	igt_disallow_hang(i915, hang);
> @@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
>   	igt_assert_f(err == 0,
>   		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
>   
> +	igt_assert_eq(sync_fence_status(fence), -EIO);

With composite fences I have a feeling -EIO could mean any fence 
signalled -EIO and we want to check all have, no? At least I hope both 
my assumptions are correct.

> +	close(fence);
> +
>   	close(dir);
>   }
>   
> 

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-02-04 15:57:23)
> 
> On 04/02/2020 15:24, Chris Wilson wrote:
> > No engine can be missed when verifying that a rogue user cannot cause a
> > denial-of-service with nohangcheck.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >   tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
> >   1 file changed, 29 insertions(+), 6 deletions(-)
> > 
> > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > index b1ae65774..2a16357a4 100644
> > --- a/tests/i915/gem_ctx_exec.c
> > +++ b/tests/i915/gem_ctx_exec.c
> > @@ -42,6 +42,7 @@
> >   
> >   #include "igt_dummyload.h"
> >   #include "igt_sysfs.h"
> > +#include "sw_sync.h"
> >   
> >   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> >   
> > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> >   
> >   static void nohangcheck_hostile(int i915)
> >   {
> > -     int64_t timeout = NSEC_PER_SEC / 2;
> > -     igt_spin_t *spin;
> > +     int64_t timeout = MSEC_PER_SEC / 2;
> >       igt_hang_t hang;
> > +     int fence = -1;
> >       uint32_t ctx;
> >       int err = 0;
> >       int dir;
> > @@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
> >   
> >       igt_require(__enable_hangcheck(dir, false));
> >   
> > -     spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > +     for_each_physical_engine(e, i915) {
> 
> I think we shouldn't add more of for_each_physical_engine, but to use 
> new style need to think where we are with the overall design of 
> iterators and stuff.

i915 = gem_reopen_driver(i915);
__for_each_physical_engine(i915, backwardse)

> > +             igt_spin_t *spin;
> > +
> > +             spin = igt_spin_new(i915, ctx,
> > +                                 .engine = eb_ring(e),
> > +                                 .flags = (IGT_SPIN_NO_PREEMPTION |
> > +                                           IGT_SPIN_FENCE_OUT));
> > +
> > +             igt_assert(spin->out_fence != -1);
> 
>  >= 0 would be more correct. Or your beloved igt_assert_fd. ;)
> 
> > +             if (fence < 0) {
> > +                     fence = spin->out_fence;
> > +                     spin->out_fence = -1;
> > +             } else {
> > +                     int new;
> > +
> > +                     new = sync_fence_merge(fence, spin->out_fence);
> > +                     close(fence);
> > +
> > +                     fence = new;
> > +             }
> > +     }
> >       gem_context_destroy(i915, ctx);
> > +     igt_assert(fence != -1);
> >   
> > -     if (gem_wait(i915, spin->handle, &timeout)) {
> > +     if (sync_fence_wait(fence, timeout)) {
> >               igt_debugfs_dump(i915, "i915_engine_info");
> >               err = -ETIME;
> >       }
> >   
> > -     igt_spin_free(i915, spin);
> 
> Could keep last for completeness.

We need to walk over the list. So I decided to leak for simplicity.

> >       __enable_hangcheck(dir, true);
> >       gem_quiescent_gpu(i915);
> >       igt_disallow_hang(i915, hang);
> > @@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
> >       igt_assert_f(err == 0,
> >                    "Hostile unpreemptable context was not cancelled immediately upon closure\n");
> >   
> > +     igt_assert_eq(sync_fence_status(fence), -EIO);
> 
> With composite fences I have a feeling -EIO could mean any fence 
> signalled -EIO and we want to check all have, no? At least I hope both 
> my assumptions are correct.

That is true (first error on any fence is promoted to the composite
fence). The way we check that they were all cancelled is by the
timeout. Hangcheck is disabled, they are infinite unstoppable batches, so
the only way out is by an engine reset or worse.
[In gem_ctx_persistence we look to see that only the engine is reset
without collateral damage, here we just make sure the system isn't lost
because of the i915.hangcheck modparam.]
-Chris
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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-02-04 15:57:23)
> 
> On 04/02/2020 15:24, Chris Wilson wrote:
> > No engine can be missed when verifying that a rogue user cannot cause a
> > denial-of-service with nohangcheck.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >   tests/i915/gem_ctx_exec.c | 35 +++++++++++++++++++++++++++++------
> >   1 file changed, 29 insertions(+), 6 deletions(-)
> > 
> > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > index b1ae65774..2a16357a4 100644
> > --- a/tests/i915/gem_ctx_exec.c
> > +++ b/tests/i915/gem_ctx_exec.c
> > @@ -42,6 +42,7 @@
> >   
> >   #include "igt_dummyload.h"
> >   #include "igt_sysfs.h"
> > +#include "sw_sync.h"
> >   
> >   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> >   
> > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> >   
> >   static void nohangcheck_hostile(int i915)
> >   {
> > -     int64_t timeout = NSEC_PER_SEC / 2;
> > -     igt_spin_t *spin;
> > +     int64_t timeout = MSEC_PER_SEC / 2;
> >       igt_hang_t hang;
> > +     int fence = -1;
> >       uint32_t ctx;
> >       int err = 0;
> >       int dir;
> > @@ -223,16 +224,35 @@ static void nohangcheck_hostile(int i915)
> >   
> >       igt_require(__enable_hangcheck(dir, false));
> >   
> > -     spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > +     for_each_physical_engine(e, i915) {
> 
> I think we shouldn't add more of for_each_physical_engine, but to use 
> new style need to think where we are with the overall design of 
> iterators and stuff.

i915 = gem_reopen_driver(i915);
__for_each_physical_engine(i915, backwardse)

> > +             igt_spin_t *spin;
> > +
> > +             spin = igt_spin_new(i915, ctx,
> > +                                 .engine = eb_ring(e),
> > +                                 .flags = (IGT_SPIN_NO_PREEMPTION |
> > +                                           IGT_SPIN_FENCE_OUT));
> > +
> > +             igt_assert(spin->out_fence != -1);
> 
>  >= 0 would be more correct. Or your beloved igt_assert_fd. ;)
> 
> > +             if (fence < 0) {
> > +                     fence = spin->out_fence;
> > +                     spin->out_fence = -1;
> > +             } else {
> > +                     int new;
> > +
> > +                     new = sync_fence_merge(fence, spin->out_fence);
> > +                     close(fence);
> > +
> > +                     fence = new;
> > +             }
> > +     }
> >       gem_context_destroy(i915, ctx);
> > +     igt_assert(fence != -1);
> >   
> > -     if (gem_wait(i915, spin->handle, &timeout)) {
> > +     if (sync_fence_wait(fence, timeout)) {
> >               igt_debugfs_dump(i915, "i915_engine_info");
> >               err = -ETIME;
> >       }
> >   
> > -     igt_spin_free(i915, spin);
> 
> Could keep last for completeness.

We need to walk over the list. So I decided to leak for simplicity.

> >       __enable_hangcheck(dir, true);
> >       gem_quiescent_gpu(i915);
> >       igt_disallow_hang(i915, hang);
> > @@ -240,6 +260,9 @@ static void nohangcheck_hostile(int i915)
> >       igt_assert_f(err == 0,
> >                    "Hostile unpreemptable context was not cancelled immediately upon closure\n");
> >   
> > +     igt_assert_eq(sync_fence_status(fence), -EIO);
> 
> With composite fences I have a feeling -EIO could mean any fence 
> signalled -EIO and we want to check all have, no? At least I hope both 
> my assumptions are correct.

That is true (first error on any fence is promoted to the composite
fence). The way we check that they were all cancelled is by the
timeout. Hangcheck is disabled, they are infinite unstoppable batches, so
the only way out is by an engine reset or worse.
[In gem_ctx_persistence we look to see that only the engine is reset
without collateral damage, here we just make sure the system isn't lost
because of the i915.hangcheck modparam.]
-Chris
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[Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

No engine can be missed when verifying that a rogue user cannot cause a
denial-of-service with nohangcheck.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
__for_each_physical_engine, keep the leaks
---
 tests/i915/gem_ctx_exec.c | 38 ++++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b1ae65774..aeb8d2976 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -42,6 +42,7 @@
 
 #include "igt_dummyload.h"
 #include "igt_sysfs.h"
+#include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
 
@@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
 
 static void nohangcheck_hostile(int i915)
 {
-	int64_t timeout = NSEC_PER_SEC / 2;
-	igt_spin_t *spin;
+	const struct intel_execution_engine2 *e;
 	igt_hang_t hang;
+	int fence = -1;
 	uint32_t ctx;
 	int err = 0;
 	int dir;
@@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
 	 * we forcibly terminate that context.
 	 */
 
+	i915 = gem_reopen_driver(i915);
+
 	dir = igt_sysfs_open_parameters(i915);
 	igt_require(dir != -1);
 
@@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
 
 	igt_require(__enable_hangcheck(dir, false));
 
-	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
+	__for_each_physical_engine(i915, e) {
+		igt_spin_t *spin;
+
+		spin = igt_spin_new(i915, ctx,
+				    .engine = e->flags,
+				    .flags = (IGT_SPIN_NO_PREEMPTION |
+					      IGT_SPIN_FENCE_OUT));
+
+		igt_assert(spin->out_fence != -1);
+		if (fence < 0) {
+			fence = spin->out_fence;
+			spin->out_fence = -1;
+		} else {
+			int new;
+
+			new = sync_fence_merge(fence, spin->out_fence);
+			close(fence);
+
+			fence = new;
+		}
+	}
 	gem_context_destroy(i915, ctx);
+	igt_assert(fence != -1);
 
-	if (gem_wait(i915, spin->handle, &timeout)) {
+	if (sync_fence_wait(fence, MSEC_PER_SEC / 2)) {
 		igt_debugfs_dump(i915, "i915_engine_info");
 		err = -ETIME;
 	}
 
-	igt_spin_free(i915, spin);
-
 	__enable_hangcheck(dir, true);
 	gem_quiescent_gpu(i915);
 	igt_disallow_hang(i915, hang);
@@ -240,7 +262,11 @@ static void nohangcheck_hostile(int i915)
 	igt_assert_f(err == 0,
 		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
 
+	igt_assert_eq(sync_fence_status(fence), -EIO);
+	close(fence);
+
 	close(dir);
+	close(i915);
 }
 
 igt_main
-- 
2.25.0

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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Tvrtko Ursulin]

On 04/02/2020 16:19, Chris Wilson wrote:
> No engine can be missed when verifying that a rogue user cannot cause a
> denial-of-service with nohangcheck.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> __for_each_physical_engine, keep the leaks
> ---
>   tests/i915/gem_ctx_exec.c | 38 ++++++++++++++++++++++++++++++++------
>   1 file changed, 32 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> index b1ae65774..aeb8d2976 100644
> --- a/tests/i915/gem_ctx_exec.c
> +++ b/tests/i915/gem_ctx_exec.c
> @@ -42,6 +42,7 @@
>   
>   #include "igt_dummyload.h"
>   #include "igt_sysfs.h"
> +#include "sw_sync.h"
>   
>   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
>   
> @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
>   
>   static void nohangcheck_hostile(int i915)
>   {
> -	int64_t timeout = NSEC_PER_SEC / 2;
> -	igt_spin_t *spin;
> +	const struct intel_execution_engine2 *e;
>   	igt_hang_t hang;
> +	int fence = -1;
>   	uint32_t ctx;
>   	int err = 0;
>   	int dir;
> @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
>   	 * we forcibly terminate that context.
>   	 */
>   
> +	i915 = gem_reopen_driver(i915);
> +
>   	dir = igt_sysfs_open_parameters(i915);
>   	igt_require(dir != -1);
>   
> @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
>   
>   	igt_require(__enable_hangcheck(dir, false));
>   
> -	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> +	__for_each_physical_engine(i915, e) {
> +		igt_spin_t *spin;
> +
> +		spin = igt_spin_new(i915, ctx,
> +				    .engine = e->flags,
> +				    .flags = (IGT_SPIN_NO_PREEMPTION |
> +					      IGT_SPIN_FENCE_OUT));
> +
> +		igt_assert(spin->out_fence != -1);
> +		if (fence < 0) {
> +			fence = spin->out_fence;
> +			spin->out_fence = -1;
> +		} else {
> +			int new;
> +
> +			new = sync_fence_merge(fence, spin->out_fence);
> +			close(fence);
> +
> +			fence = new;
> +		}
> +	}
>   	gem_context_destroy(i915, ctx);
> +	igt_assert(fence != -1);
>   
> -	if (gem_wait(i915, spin->handle, &timeout)) {
> +	if (sync_fence_wait(fence, MSEC_PER_SEC / 2)) {
>   		igt_debugfs_dump(i915, "i915_engine_info");
>   		err = -ETIME;
>   	}
>   
> -	igt_spin_free(i915, spin);
> -
>   	__enable_hangcheck(dir, true);
>   	gem_quiescent_gpu(i915);
>   	igt_disallow_hang(i915, hang);
> @@ -240,7 +262,11 @@ static void nohangcheck_hostile(int i915)
>   	igt_assert_f(err == 0,
>   		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
>   
> +	igt_assert_eq(sync_fence_status(fence), -EIO);
> +	close(fence);
> +
>   	close(dir);
> +	close(i915);
>   }
>   
>   igt_main
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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[igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_exec: Cover all engines for nohangcheck

[Patchwork]

== Series Details ==

Series: i915/gem_ctx_exec: Cover all engines for nohangcheck
URL   : https://patchwork.freedesktop.org/series/72980/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7864 -> IGTPW_4092
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html

Known issues
------------

  Here are the changes found in IGTPW_4092 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][1] -> [INCOMPLETE][2] ([i915#45])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-byt-j1900/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_suspend@basic-s0:
    - fi-cml-s:           [PASS][3] -> [FAIL][4] ([fdo#103375])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-cml-s/igt@gem_exec_suspend@basic-s0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-cml-s/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-skl-6770hq:      [PASS][5] -> [INCOMPLETE][6] ([i915#151])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-skl-6770hq/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-skl-6770hq/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8700k:       [PASS][7] -> [INCOMPLETE][8] ([i915#424])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][9] -> [FAIL][10] ([fdo#111096] / [i915#323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-icl-y:           [DMESG-FAIL][11] ([fdo#108569]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-icl-y/igt@i915_selftest@live_execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-icl-y/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_gtt:
    - fi-skl-6600u:       [TIMEOUT][13] ([fdo#111732] / [fdo#112271]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-skl-6600u/igt@i915_selftest@live_gtt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-skl-6600u/igt@i915_selftest@live_gtt.html

  * igt@i915_selftest@live_perf:
    - fi-apl-guc:         [INCOMPLETE][15] ([fdo#103927]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-apl-guc/igt@i915_selftest@live_perf.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-apl-guc/igt@i915_selftest@live_perf.html

  
#### Warnings ####

  * igt@gem_exec_parallel@contexts:
    - fi-byt-n2820:       [TIMEOUT][17] ([fdo#112271]) -> [FAIL][18] ([i915#694])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-byt-n2820/igt@gem_exec_parallel@contexts.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-cml-s:           [INCOMPLETE][19] ([i915#1078] / [i915#283]) -> [INCOMPLETE][20] ([i915#283])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-cml-s/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][21] ([i915#725]) -> [DMESG-FAIL][22] ([i915#553] / [i915#725])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1078]: https://gitlab.freedesktop.org/drm/intel/issues/1078
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
  [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725


Participating hosts (50 -> 47)
------------------------------

  Additional (3): fi-skl-lmem fi-glk-dsi fi-snb-2520m 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5417 -> IGTPW_4092

  CI-20190529: 20190529
  CI_DRM_7864: 5a140e2fc771e4c8b10d14e2db7bfb4996ee9d8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4092: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html
  IGT_5417: 33cc93c8ba5daa0b7498f297a4f626844d895d06 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Tvrtko Ursulin]

On 04/02/2020 16:19, Chris Wilson wrote:
> No engine can be missed when verifying that a rogue user cannot cause a
> denial-of-service with nohangcheck.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> __for_each_physical_engine, keep the leaks
> ---
>   tests/i915/gem_ctx_exec.c | 38 ++++++++++++++++++++++++++++++++------
>   1 file changed, 32 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> index b1ae65774..aeb8d2976 100644
> --- a/tests/i915/gem_ctx_exec.c
> +++ b/tests/i915/gem_ctx_exec.c
> @@ -42,6 +42,7 @@
>   
>   #include "igt_dummyload.h"
>   #include "igt_sysfs.h"
> +#include "sw_sync.h"
>   
>   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
>   
> @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
>   
>   static void nohangcheck_hostile(int i915)
>   {
> -	int64_t timeout = NSEC_PER_SEC / 2;
> -	igt_spin_t *spin;
> +	const struct intel_execution_engine2 *e;
>   	igt_hang_t hang;
> +	int fence = -1;
>   	uint32_t ctx;
>   	int err = 0;
>   	int dir;
> @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
>   	 * we forcibly terminate that context.
>   	 */
>   
> +	i915 = gem_reopen_driver(i915);
> +
>   	dir = igt_sysfs_open_parameters(i915);
>   	igt_require(dir != -1);
>   
> @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
>   
>   	igt_require(__enable_hangcheck(dir, false));
>   
> -	spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> +	__for_each_physical_engine(i915, e) {
> +		igt_spin_t *spin;
> +
> +		spin = igt_spin_new(i915, ctx,
> +				    .engine = e->flags,

Ouch, I missed a mismatch between ctx and e->flags here. Thanks to 
Sreedhar for reporting it.

We either need gem_context_set_all_engines back or to rethink a cleaner 
strategy.

Regards,

Tvrtko

> +				    .flags = (IGT_SPIN_NO_PREEMPTION |
> +					      IGT_SPIN_FENCE_OUT));
> +
> +		igt_assert(spin->out_fence != -1);
> +		if (fence < 0) {
> +			fence = spin->out_fence;
> +			spin->out_fence = -1;
> +		} else {
> +			int new;
> +
> +			new = sync_fence_merge(fence, spin->out_fence);
> +			close(fence);
> +
> +			fence = new;
> +		}
> +	}
>   	gem_context_destroy(i915, ctx);
> +	igt_assert(fence != -1);
>   
> -	if (gem_wait(i915, spin->handle, &timeout)) {
> +	if (sync_fence_wait(fence, MSEC_PER_SEC / 2)) {
>   		igt_debugfs_dump(i915, "i915_engine_info");
>   		err = -ETIME;
>   	}
>   
> -	igt_spin_free(i915, spin);
> -
>   	__enable_hangcheck(dir, true);
>   	gem_quiescent_gpu(i915);
>   	igt_disallow_hang(i915, hang);
> @@ -240,7 +262,11 @@ static void nohangcheck_hostile(int i915)
>   	igt_assert_f(err == 0,
>   		     "Hostile unpreemptable context was not cancelled immediately upon closure\n");
>   
> +	igt_assert_eq(sync_fence_status(fence), -EIO);
> +	close(fence);
> +
>   	close(dir);
> +	close(i915);
>   }
>   
>   igt_main
> 
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-02-05 11:48:42)
> 
> On 04/02/2020 16:19, Chris Wilson wrote:
> > No engine can be missed when verifying that a rogue user cannot cause a
> > denial-of-service with nohangcheck.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > __for_each_physical_engine, keep the leaks
> > ---
> >   tests/i915/gem_ctx_exec.c | 38 ++++++++++++++++++++++++++++++++------
> >   1 file changed, 32 insertions(+), 6 deletions(-)
> > 
> > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > index b1ae65774..aeb8d2976 100644
> > --- a/tests/i915/gem_ctx_exec.c
> > +++ b/tests/i915/gem_ctx_exec.c
> > @@ -42,6 +42,7 @@
> >   
> >   #include "igt_dummyload.h"
> >   #include "igt_sysfs.h"
> > +#include "sw_sync.h"
> >   
> >   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> >   
> > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> >   
> >   static void nohangcheck_hostile(int i915)
> >   {
> > -     int64_t timeout = NSEC_PER_SEC / 2;
> > -     igt_spin_t *spin;
> > +     const struct intel_execution_engine2 *e;
> >       igt_hang_t hang;
> > +     int fence = -1;
> >       uint32_t ctx;
> >       int err = 0;
> >       int dir;
> > @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
> >        * we forcibly terminate that context.
> >        */
> >   
> > +     i915 = gem_reopen_driver(i915);
> > +
> >       dir = igt_sysfs_open_parameters(i915);
> >       igt_require(dir != -1);
> >   
> > @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
> >   
> >       igt_require(__enable_hangcheck(dir, false));
> >   
> > -     spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > +     __for_each_physical_engine(i915, e) {
> > +             igt_spin_t *spin;
> > +
> > +             spin = igt_spin_new(i915, ctx,
> > +                                 .engine = e->flags,
> 
> Ouch, I missed a mismatch between ctx and e->flags here. Thanks to 
> Sreedhar for reporting it.
> 
> We either need gem_context_set_all_engines back or to rethink a cleaner 
> strategy.

Copy engines, or pass the ctx into __for_each_physical_engine.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck

[Chris Wilson]

Quoting Chris Wilson (2020-02-05 11:52:11)
> Quoting Tvrtko Ursulin (2020-02-05 11:48:42)
> > 
> > On 04/02/2020 16:19, Chris Wilson wrote:
> > > No engine can be missed when verifying that a rogue user cannot cause a
> > > denial-of-service with nohangcheck.
> > > 
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > > __for_each_physical_engine, keep the leaks
> > > ---
> > >   tests/i915/gem_ctx_exec.c | 38 ++++++++++++++++++++++++++++++++------
> > >   1 file changed, 32 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > > index b1ae65774..aeb8d2976 100644
> > > --- a/tests/i915/gem_ctx_exec.c
> > > +++ b/tests/i915/gem_ctx_exec.c
> > > @@ -42,6 +42,7 @@
> > >   
> > >   #include "igt_dummyload.h"
> > >   #include "igt_sysfs.h"
> > > +#include "sw_sync.h"
> > >   
> > >   IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> > >   
> > > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> > >   
> > >   static void nohangcheck_hostile(int i915)
> > >   {
> > > -     int64_t timeout = NSEC_PER_SEC / 2;
> > > -     igt_spin_t *spin;
> > > +     const struct intel_execution_engine2 *e;
> > >       igt_hang_t hang;
> > > +     int fence = -1;
> > >       uint32_t ctx;
> > >       int err = 0;
> > >       int dir;
> > > @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
> > >        * we forcibly terminate that context.
> > >        */
> > >   
> > > +     i915 = gem_reopen_driver(i915);
> > > +
> > >       dir = igt_sysfs_open_parameters(i915);
> > >       igt_require(dir != -1);
> > >   
> > > @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
> > >   
> > >       igt_require(__enable_hangcheck(dir, false));
> > >   
> > > -     spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > > +     __for_each_physical_engine(i915, e) {
> > > +             igt_spin_t *spin;
> > > +
> > > +             spin = igt_spin_new(i915, ctx,
> > > +                                 .engine = e->flags,
> > 
> > Ouch, I missed a mismatch between ctx and e->flags here. Thanks to 
> > Sreedhar for reporting it.
> > 
> > We either need gem_context_set_all_engines back or to rethink a cleaner 
> > strategy.
> 
> Copy engines, or pass the ctx into __for_each_physical_engine.

Which [copy engines] reveals a bug... More missing tests in
gem_ctx_persistence.
-Chris
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[igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_ctx_exec: Cover all engines for nohangcheck

[Patchwork]

== Series Details ==

Series: i915/gem_ctx_exec: Cover all engines for nohangcheck
URL   : https://patchwork.freedesktop.org/series/72980/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7864_full -> IGTPW_4092_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4092_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4092_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4092_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-hsw:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw4/igt@gem_ctx_exec@basic-nohangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw6/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@runner@aborted:
    - shard-hsw:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw4/igt@runner@aborted.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7864_full and IGTPW_4092_full:

### New IGT tests (5) ###

  * igt@gem_ctx_sseu@engines:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_ctx_sseu@ggtt-args:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_sseu@invalid-args:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_sseu@invalid-sseu:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_media_vme:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.04, 0.19] s

  

Known issues
------------

  Here are the changes found in IGTPW_4092_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#112080]) +10 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb4/igt@gem_busy@busy-vcs1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb5/igt@gem_busy@busy-vcs1.html

  * igt@gem_exec_schedule@pi-userfault-bsd:
    - shard-iclb:         [PASS][6] -> [SKIP][7] ([i915#677])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb3/igt@gem_exec_schedule@pi-userfault-bsd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb2/igt@gem_exec_schedule@pi-userfault-bsd.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#112146]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#109276]) +20 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][12] -> [FAIL][13] ([i915#644])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([i915#413])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb5/igt@i915_pm_rps@waitboost.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb7/igt@i915_pm_rps@waitboost.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +9 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][18] -> [FAIL][19] ([i915#72])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#478])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-snb4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-snb1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-apl:          [PASS][22] -> [FAIL][23] ([i915#79])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-apl:          [PASS][24] -> [FAIL][25] ([i915#49])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-apl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
    - shard-kbl:          [PASS][26] -> [FAIL][27] ([i915#49])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-tglb:         [PASS][28] -> [SKIP][29] ([i915#668]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109642] / [fdo#111068])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb4/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][32] -> [SKIP][33] ([fdo#109441]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-hsw:          [PASS][34] -> [INCOMPLETE][35] ([i915#61]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw1/igt@perf_pmu@cpu-hotplug.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw4/igt@perf_pmu@cpu-hotplug.html

  
#### Possible fixes ####

  * igt@gem_busy@extended-parallel-vcs1:
    - shard-iclb:         [SKIP][36] ([fdo#112080]) -> [PASS][37] +14 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html

  * igt@gem_exec_schedule@pi-distinct-iova-bsd:
    - shard-iclb:         [SKIP][38] ([i915#677]) -> [PASS][39] +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb3/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][40] ([fdo#112146]) -> [PASS][41] +6 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_mmap_gtt@big-copy-odd:
    - shard-snb:          [DMESG-WARN][42] ([i915#478]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-snb6/igt@gem_mmap_gtt@big-copy-odd.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-snb2/igt@gem_mmap_gtt@big-copy-odd.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-hsw:          [FAIL][44] ([i915#694]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw7/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][46] ([i915#180]) -> [PASS][47] +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-apl6/igt@gem_softpin@noreloc-s3.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-apl8/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_blits@interruptible:
    - shard-hsw:          [FAIL][48] ([i915#818]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw2/igt@gem_tiled_blits@interruptible.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw8/igt@gem_tiled_blits@interruptible.html

  * igt@i915_selftest@live_blt:
    - shard-hsw:          [DMESG-FAIL][50] ([i915#725]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw7/igt@i915_selftest@live_blt.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw6/igt@i915_selftest@live_blt.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
    - shard-iclb:         [SKIP][52] ([i915#1140]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb7/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][54] ([i915#180]) -> [PASS][55] +3 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][56] ([i915#79]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-glk:          [FAIL][58] ([i915#899]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][60] ([fdo#109441]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][62] ([i915#31]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-apl2/igt@kms_setmode@basic.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-apl2/igt@kms_setmode@basic.html

  * igt@prime_mmap_coherency@ioctl-errors:
    - shard-hsw:          [FAIL][64] ([i915#831]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-hsw5/igt@prime_mmap_coherency@ioctl-errors.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-hsw8/igt@prime_mmap_coherency@ioctl-errors.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][66] ([fdo#109276]) -> [PASS][67] +18 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][68] ([fdo#109349]) -> [DMESG-WARN][69] ([fdo#107724])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7864/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1140]: https://gitlab.freedesktop.org/drm/intel/issues/1140
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
  [i915#831]: https://gitlab.freedesktop.org/drm/intel/issues/831
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899


Participating hosts (10 -> 8)
------------------------------

  Missing    (2): pig-skl-6260u pig-glk-j5005 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5417 -> IGTPW_4092
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_7864: 5a140e2fc771e4c8b10d14e2db7bfb4996ee9d8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4092: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html
  IGT_5417: 33cc93c8ba5daa0b7498f297a4f626844d895d06 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4092/index.html
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