From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7
Date: Thu, 6 Feb 2020 22:08:27 +0000 [thread overview]
Message-ID: <20200206220827.2677474-3-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200206220827.2677474-1-chris@chris-wilson.co.uk>
Trust that the HW does the right thing after simply updating the
PD_DIR_BASE?
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index c4e6bad5e6dc..b1694741556f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1346,14 +1346,10 @@ static int load_pd_dir(struct i915_request *rq,
const struct intel_engine_cs * const engine = rq->engine;
u32 *cs;
- cs = intel_ring_begin(rq, 12);
+ cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
- *cs++ = valid;
-
*cs++ = MI_LOAD_REGISTER_IMM(1);
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
@@ -1364,10 +1360,6 @@ static int load_pd_dir(struct i915_request *rq,
*cs++ = intel_gt_scratch_offset(engine->gt,
INTEL_GT_SCRATCH_FIELD_DEFAULT);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
- *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
-
intel_ring_advance(rq, cs);
return rq->engine->emit_flush(rq, EMIT_FLUSH);
--
2.25.0
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next prev parent reply other threads:[~2020-02-06 22:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 22:08 [Intel-gfx] [CI 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-06 22:08 ` [Intel-gfx] [CI 2/3] drm/i915/gt: Split the gen7 rcs flush into phases Chris Wilson
2020-02-06 22:08 ` Chris Wilson [this message]
2020-02-07 0:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
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