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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/48] target/arm: Update timer access for VHE
Date: Fri,  7 Feb 2020 14:33:22 +0000	[thread overview]
Message-ID: <20200207143343.30322-28-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 81 insertions(+), 21 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 996865a3a20..992ab2a15f1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2324,10 +2324,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
      * Writable only at the highest implemented exception level.
      */
     int el = arm_current_el(env);
+    uint64_t hcr;
+    uint32_t cntkctl;
 
     switch (el) {
     case 0:
-        if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
+        hcr = arm_hcr_el2_eff(env);
+        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+            cntkctl = env->cp15.cnthctl_el2;
+        } else {
+            cntkctl = env->cp15.c14_cntkctl;
+        }
+        if (!extract32(cntkctl, 0, 2)) {
             return CP_ACCESS_TRAP;
         }
         break;
@@ -2355,17 +2363,47 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
 {
     unsigned int cur_el = arm_current_el(env);
     bool secure = arm_is_secure(env);
+    uint64_t hcr = arm_hcr_el2_eff(env);
 
-    /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
-    if (cur_el == 0 &&
-        !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
-        return CP_ACCESS_TRAP;
-    }
+    switch (cur_el) {
+    case 0:
+        /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
+        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+            return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
+                    ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
+        }
 
-    if (arm_feature(env, ARM_FEATURE_EL2) &&
-        timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
-        !extract32(env->cp15.cnthctl_el2, 0, 1)) {
-        return CP_ACCESS_TRAP_EL2;
+        /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
+        if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
+            return CP_ACCESS_TRAP;
+        }
+
+        /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
+        if (hcr & HCR_E2H) {
+            if (timeridx == GTIMER_PHYS &&
+                !extract32(env->cp15.cnthctl_el2, 10, 1)) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+        } else {
+            /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
+            if (arm_feature(env, ARM_FEATURE_EL2) &&
+                timeridx == GTIMER_PHYS && !secure &&
+                !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+        }
+        break;
+
+    case 1:
+        /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
+        if (arm_feature(env, ARM_FEATURE_EL2) &&
+            timeridx == GTIMER_PHYS && !secure &&
+            (hcr & HCR_E2H
+             ? !extract32(env->cp15.cnthctl_el2, 10, 1)
+             : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        break;
     }
     return CP_ACCESS_OK;
 }
@@ -2375,19 +2413,41 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
 {
     unsigned int cur_el = arm_current_el(env);
     bool secure = arm_is_secure(env);
+    uint64_t hcr = arm_hcr_el2_eff(env);
 
-    /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
-     * EL0[PV]TEN is zero.
-     */
-    if (cur_el == 0 &&
-        !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
-        return CP_ACCESS_TRAP;
-    }
+    switch (cur_el) {
+    case 0:
+        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+            /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
+            return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
+                    ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
+        }
 
-    if (arm_feature(env, ARM_FEATURE_EL2) &&
-        timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
-        !extract32(env->cp15.cnthctl_el2, 1, 1)) {
-        return CP_ACCESS_TRAP_EL2;
+        /*
+         * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
+         * EL0 if EL0[PV]TEN is zero.
+         */
+        if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
+            return CP_ACCESS_TRAP;
+        }
+        /* fall through */
+
+    case 1:
+        if (arm_feature(env, ARM_FEATURE_EL2) &&
+            timeridx == GTIMER_PHYS && !secure) {
+            if (hcr & HCR_E2H) {
+                /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
+                if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
+                    return CP_ACCESS_TRAP_EL2;
+                }
+            } else {
+                /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
+                if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
+                    return CP_ACCESS_TRAP_EL2;
+                }
+            }
+        }
+        break;
     }
     return CP_ACCESS_OK;
 }
-- 
2.20.1



  parent reply	other threads:[~2020-02-07 14:54 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-07 14:32 [PULL 00/48] target-arm queue Peter Maydell
2020-02-07 14:32 ` [PULL 01/48] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none Peter Maydell
2020-02-07 14:32 ` [PULL 02/48] target/arm: Define isar_feature_aa64_vh Peter Maydell
2020-02-07 14:32 ` [PULL 03/48] target/arm: Enable HCR_E2H for VHE Peter Maydell
2020-02-07 14:32 ` [PULL 04/48] target/arm: Add CONTEXTIDR_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 05/48] target/arm: Add TTBR1_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 06/48] target/arm: Update CNTVCT_EL0 for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 07/48] target/arm: Split out vae1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 08/48] target/arm: Split out alle1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives Peter Maydell
2020-02-07 14:33 ` [PULL 10/48] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Peter Maydell
2020-02-07 14:33 ` [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Peter Maydell
2020-02-07 14:33 ` [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Peter Maydell
2020-02-07 14:33 ` [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Peter Maydell
2020-02-07 14:33 ` [PULL 14/48] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Peter Maydell
2020-02-07 14:33 ` [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Peter Maydell
2020-02-07 14:33 ` [PULL 16/48] target/arm: Recover 4 bits from TBFLAGs Peter Maydell
2020-02-07 14:33 ` [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Peter Maydell
2020-02-07 14:33 ` [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit Peter Maydell
2020-02-07 14:33 ` [PULL 19/48] target/arm: Tidy ARMMMUIdx m-profile definitions Peter Maydell
2020-02-07 14:33 ` [PULL 20/48] target/arm: Reorganize ARMMMUIdx Peter Maydell
2020-02-07 14:33 ` [PULL 21/48] target/arm: Add regime_has_2_ranges Peter Maydell
2020-02-07 14:33 ` [PULL 22/48] target/arm: Update arm_mmu_idx for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 23/48] target/arm: Update arm_sctlr " Peter Maydell
2020-02-07 14:33 ` [PULL 24/48] target/arm: Update aa64_zva_access for EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 25/48] target/arm: Update ctr_el0_access " Peter Maydell
2020-02-07 14:33 ` [PULL 26/48] target/arm: Add the hypervisor virtual counter Peter Maydell
2020-02-07 14:33 ` Peter Maydell [this message]
2020-02-07 14:33 ` [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 29/48] target/arm: Add VHE system register redirection and aliasing Peter Maydell
2020-02-07 14:33 ` [PULL 30/48] target/arm: Add VHE timer " Peter Maydell
2020-02-07 14:33 ` [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Peter Maydell
2020-02-07 14:33 ` [PULL 32/48] target/arm: Flush tlbs for E2&0 " Peter Maydell
2020-02-07 14:33 ` [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE Peter Maydell
2020-02-07 14:33 ` [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps Peter Maydell
2020-02-07 14:33 ` [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 " Peter Maydell
2020-02-07 14:33 ` [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max Peter Maydell
2020-02-07 14:33 ` [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c Peter Maydell
2020-02-07 14:33 ` [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked Peter Maydell
2020-02-07 14:33 ` [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked Peter Maydell
2020-02-07 14:33 ` [PULL 42/48] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Peter Maydell
2020-02-07 14:33 ` [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode Peter Maydell
2020-02-07 14:33 ` [PULL 44/48] bcm2835_dma: Re-initialize xlen " Peter Maydell
2020-02-07 14:33 ` [PULL 45/48] docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer Peter Maydell
2020-02-07 14:33 ` [PULL 46/48] armv7m_systick: delay timer_new to avoid memleaks Peter Maydell
2020-02-07 14:33 ` [PULL 47/48] stm32f2xx_timer: " Peter Maydell
2020-02-07 14:33 ` [PULL 48/48] stellaris: " Peter Maydell
2020-02-10 12:06 ` [PULL 00/48] target-arm queue Peter Maydell

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