From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E39C2BA83 for ; Fri, 7 Feb 2020 17:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF74C2082E for ; Fri, 7 Feb 2020 17:28:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="nZPxdgD/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727502AbgBGR2w (ORCPT ); Fri, 7 Feb 2020 12:28:52 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:38454 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726874AbgBGR2v (ORCPT ); Fri, 7 Feb 2020 12:28:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=UEBTS0XrdoJSJQl95vSpuczU7JlSfYzUjvPMMXXJ5c4=; b=nZPxdgD/cUEFic5JI75m8v0Xr7 CzOliGBTSnBDBIgGpIokFggKL4yrT8Bccvx0sDAVG0BcwajXoK9KPtsWyzptxfB3FBdxfIx8Ofc6/ 75s/hj9xZVa9oGxqU0yOIiT/04ftNIyXOmS9EE6zR/V1CQgvKi6M/zCYiY5bqEtEPJas=; Received: from andrew by vps0.lunn.ch with local (Exim 4.93) (envelope-from ) id 1j07Qq-0004lY-If; Fri, 07 Feb 2020 18:28:44 +0100 Date: Fri, 7 Feb 2020 18:28:44 +0100 From: Andrew Lunn To: Linus Walleij Cc: christopher.s.hall@intel.com, Mika Westerberg , Andy Shevchenko , netdev , "linux-kernel@vger.kernel.org" , Thomas Gleixner , "H. Peter Anvin" , Ingo Molnar , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , jacob.e.keller@intel.com, Richard Cochran , "David S. Miller" , sean.v.kelley@intel.com Subject: Re: [Intel PMC TGPIO Driver 5/5] drivers/ptp: Add PMC Time-Aware GPIO Driver Message-ID: <20200207172844.GC19213@lunn.ch> References: <20191211214852.26317-1-christopher.s.hall@intel.com> <20191211214852.26317-6-christopher.s.hall@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 07, 2020 at 06:10:46PM +0100, Linus Walleij wrote: > OK this looks like some GPIO registers... > > Then there is a bunch of PTP stuff I don't understand I suppose > related to the precision time protocol. Hi Linus I understand your confusion. The first time this was posted to netdev, i asked it to be renamed because it has very little to do with GPIO https://lore.kernel.org/netdev/20190719132021.GC24930@lunn.ch/ Andrew