From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFB26C35242 for ; Sun, 9 Feb 2020 00:01:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1FD12072A for ; Sun, 9 Feb 2020 00:01:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tsY6c8Zp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727543AbgBIABF (ORCPT ); Sat, 8 Feb 2020 19:01:05 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35749 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727073AbgBIABE (ORCPT ); Sat, 8 Feb 2020 19:01:04 -0500 Received: by mail-pg1-f196.google.com with SMTP id l24so1835923pgk.2 for ; Sat, 08 Feb 2020 16:01:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=KWYuYSQscJFjEOwJSH3DjqreOwAqOvNwuPxdqRtzkyQ=; b=tsY6c8Zp34BFWVlO3JnG99l/nv2GxJEIYPNYCJeVPEdmpzAgBvVD/d98DcL2DPJ1E8 1owKgkk198flFbdTlEDw2yUcI6MWJKIq8ydFRJW6fBp00zwBIDtE7Pzw6nyR+Qck10VO lQzO5qBNnOdKWn3Y61SCHqAxkkZf1EkvLrQDHlavWfQiNi0lUjQMNpYDM7fF8Rzw+zqQ amqTFnRjGKcGRGHW1yi+eUbOHM3t8cu3/rcI71EwTlH05H+F2b5IYN6Lu4de+Og3NCk6 H5J7+cEkkvyIP1pTvE+fTQTR3TsXvDNOvX61hK8eIBoSe6fLYYveggHJocO2G4bDWWZe y2+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=KWYuYSQscJFjEOwJSH3DjqreOwAqOvNwuPxdqRtzkyQ=; b=WMas1UnNtGbqnpsXZ1IhEH+mNdoVjRVE5PPkX9l3ma1wzBu5Ft7CCKqKLh9WGcwXeR /z+nFPLa2Wy+8M5x1SFvoGy1ztXBn9eOb2OnBMRQrjTPxJdTQa7TFxZNNwat0dRymLZq OAl6X77m0WjQMHNwXEu97ndJPa8s5hLBDmscX5lqBviJ1qjeMGvYESwZfEprxTljxlnA Ia8E63iioHAunUpjC8YVB5hGJpouHoGB3+c31wwHhJrV2sfZ0c7IYAvTjUDSMb26fZHf 0LbRlhSPP98MM51glBzvw+cHecaiKgCPphV/KKx/iZgDKIhbljWvIwzYJrilWvsXSkzR 5/iA== X-Gm-Message-State: APjAAAVHkBn5V7uXSh66YS448UGIE0ZFP3X1umGjOD+c7gkyFXSirKct lcz9N8C7RzzIzZjgD26HoVu7aw== X-Google-Smtp-Source: APXvYqzR0flCofwFqUkheDzbGPVFJIBJyNBgBn7Z4+U50I3hGaNFRhfapXdIj2fQ490UigbTwQpbDg== X-Received: by 2002:a63:d207:: with SMTP id a7mr6908057pgg.225.1581206464258; Sat, 08 Feb 2020 16:01:04 -0800 (PST) Received: from ripper (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id l15sm5955972pgi.31.2020.02.08.16.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 16:01:03 -0800 (PST) Date: Sat, 8 Feb 2020 16:00:17 -0800 From: Bjorn Andersson To: Sai Prakash Ranjan Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephen Boyd , Matthias Kaehlcke , Rajendra Nayak , Tomasz Figa Subject: Re: [PATCH 1/2] iommu: arm-smmu-impl: Convert to a generic reset implementation Message-ID: <20200209000017.GD955802@ripper> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 22 Jan 03:48 PST 2020, Sai Prakash Ranjan wrote: > Currently the QCOM specific smmu reset implementation is very > specific to SDM845 SoC and has a wait-for-safe logic which > may not be required for other SoCs. So move the SDM845 specific > logic to its specific reset function. Also add SC7180 SMMU > compatible for calling into QCOM specific implementation. > > Signed-off-by: Sai Prakash Ranjan Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm-smmu-impl.c | 8 +++++--- > drivers/iommu/arm-smmu-qcom.c | 16 +++++++++++++--- > 2 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c > index 74d97a886e93..c75b9d957b70 100644 > --- a/drivers/iommu/arm-smmu-impl.c > +++ b/drivers/iommu/arm-smmu-impl.c > @@ -150,6 +150,8 @@ static const struct arm_smmu_impl arm_mmu500_impl = { > > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > { > + const struct device_node *np = smmu->dev->of_node; > + > /* > * We will inevitably have to combine model-specific implementation > * quirks with platform-specific integration quirks, but everything > @@ -166,11 +168,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > break; > } > > - if (of_property_read_bool(smmu->dev->of_node, > - "calxeda,smmu-secure-config-access")) > + if (of_property_read_bool(np, "calxeda,smmu-secure-config-access")) > smmu->impl = &calxeda_impl; > > - if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500")) > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || > + of_device_is_compatible(np, "qcom,sc7180-smmu-500")) > return qcom_smmu_impl_init(smmu); > > return smmu; > diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c > index 24c071c1d8b0..64a4ab270ab7 100644 > --- a/drivers/iommu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm-smmu-qcom.c > @@ -15,8 +15,6 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > { > int ret; > > - arm_mmu500_reset(smmu); > - > /* > * To address performance degradation in non-real time clients, > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, > @@ -30,8 +28,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > return ret; > } > > +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + arm_mmu500_reset(smmu); > + > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) > + return qcom_sdm845_smmu500_reset(smmu); > + > + return 0; > +} > + > static const struct arm_smmu_impl qcom_smmu_impl = { > - .reset = qcom_sdm845_smmu500_reset, > + .reset = qcom_smmu500_reset, > }; > > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD802C35242 for ; Sun, 9 Feb 2020 00:01:08 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B0C22072A for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id l15sm5955972pgi.31.2020.02.08.16.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 16:01:03 -0800 (PST) Date: Sat, 8 Feb 2020 16:00:17 -0800 From: Bjorn Andersson To: Sai Prakash Ranjan Subject: Re: [PATCH 1/2] iommu: arm-smmu-impl: Convert to a generic reset implementation Message-ID: <20200209000017.GD955802@ripper> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: Rajendra Nayak , Will Deacon , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke , linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed 22 Jan 03:48 PST 2020, Sai Prakash Ranjan wrote: > Currently the QCOM specific smmu reset implementation is very > specific to SDM845 SoC and has a wait-for-safe logic which > may not be required for other SoCs. So move the SDM845 specific > logic to its specific reset function. Also add SC7180 SMMU > compatible for calling into QCOM specific implementation. > > Signed-off-by: Sai Prakash Ranjan Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm-smmu-impl.c | 8 +++++--- > drivers/iommu/arm-smmu-qcom.c | 16 +++++++++++++--- > 2 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c > index 74d97a886e93..c75b9d957b70 100644 > --- a/drivers/iommu/arm-smmu-impl.c > +++ b/drivers/iommu/arm-smmu-impl.c > @@ -150,6 +150,8 @@ static const struct arm_smmu_impl arm_mmu500_impl = { > > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > { > + const struct device_node *np = smmu->dev->of_node; > + > /* > * We will inevitably have to combine model-specific implementation > * quirks with platform-specific integration quirks, but everything > @@ -166,11 +168,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > break; > } > > - if (of_property_read_bool(smmu->dev->of_node, > - "calxeda,smmu-secure-config-access")) > + if (of_property_read_bool(np, "calxeda,smmu-secure-config-access")) > smmu->impl = &calxeda_impl; > > - if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500")) > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || > + of_device_is_compatible(np, "qcom,sc7180-smmu-500")) > return qcom_smmu_impl_init(smmu); > > return smmu; > diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c > index 24c071c1d8b0..64a4ab270ab7 100644 > --- a/drivers/iommu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm-smmu-qcom.c > @@ -15,8 +15,6 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > { > int ret; > > - arm_mmu500_reset(smmu); > - > /* > * To address performance degradation in non-real time clients, > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, > @@ -30,8 +28,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > return ret; > } > > +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + arm_mmu500_reset(smmu); > + > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) > + return qcom_sdm845_smmu500_reset(smmu); > + > + return 0; > +} > + > static const struct arm_smmu_impl qcom_smmu_impl = { > - .reset = qcom_sdm845_smmu500_reset, > + .reset = qcom_smmu500_reset, > }; > > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC08EC35242 for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id l15sm5955972pgi.31.2020.02.08.16.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 16:01:03 -0800 (PST) Date: Sat, 8 Feb 2020 16:00:17 -0800 From: Bjorn Andersson To: Sai Prakash Ranjan Subject: Re: [PATCH 1/2] iommu: arm-smmu-impl: Convert to a generic reset implementation Message-ID: <20200209000017.GD955802@ripper> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200208_160107_743555_7C86F590 X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Tomasz Figa , Rajendra Nayak , Will Deacon , Joerg Roedel , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jordan Crouse , Matthias Kaehlcke , linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed 22 Jan 03:48 PST 2020, Sai Prakash Ranjan wrote: > Currently the QCOM specific smmu reset implementation is very > specific to SDM845 SoC and has a wait-for-safe logic which > may not be required for other SoCs. So move the SDM845 specific > logic to its specific reset function. Also add SC7180 SMMU > compatible for calling into QCOM specific implementation. > > Signed-off-by: Sai Prakash Ranjan Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm-smmu-impl.c | 8 +++++--- > drivers/iommu/arm-smmu-qcom.c | 16 +++++++++++++--- > 2 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c > index 74d97a886e93..c75b9d957b70 100644 > --- a/drivers/iommu/arm-smmu-impl.c > +++ b/drivers/iommu/arm-smmu-impl.c > @@ -150,6 +150,8 @@ static const struct arm_smmu_impl arm_mmu500_impl = { > > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > { > + const struct device_node *np = smmu->dev->of_node; > + > /* > * We will inevitably have to combine model-specific implementation > * quirks with platform-specific integration quirks, but everything > @@ -166,11 +168,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > break; > } > > - if (of_property_read_bool(smmu->dev->of_node, > - "calxeda,smmu-secure-config-access")) > + if (of_property_read_bool(np, "calxeda,smmu-secure-config-access")) > smmu->impl = &calxeda_impl; > > - if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500")) > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || > + of_device_is_compatible(np, "qcom,sc7180-smmu-500")) > return qcom_smmu_impl_init(smmu); > > return smmu; > diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c > index 24c071c1d8b0..64a4ab270ab7 100644 > --- a/drivers/iommu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm-smmu-qcom.c > @@ -15,8 +15,6 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > { > int ret; > > - arm_mmu500_reset(smmu); > - > /* > * To address performance degradation in non-real time clients, > * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, > @@ -30,8 +28,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) > return ret; > } > > +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + arm_mmu500_reset(smmu); > + > + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) > + return qcom_sdm845_smmu500_reset(smmu); > + > + return 0; > +} > + > static const struct arm_smmu_impl qcom_smmu_impl = { > - .reset = qcom_sdm845_smmu500_reset, > + .reset = qcom_smmu500_reset, > }; > > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel