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* [PATCHv6 0/5] Odroid n2 using eMMC would fail to boot up
@ 2020-02-09 11:05 ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

Here are some small changes to fix booting of Odroid N2 using eMMC.
Fixed the clk tunnig during mmc initialization.
Added two new patches to fix warning

Build and tested on top of below patches
[0] https://patchwork.ozlabs.org/patch/1213648/
[1] https://patchwork.ozlabs.org/patch/1213650/

Tested on below eMMC module on Odroid N2 and C2
new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
old back   - eMMC CGND3R 58.2 GiB MMC 5.0

Prevoius changes: 
Fixed the clk tuning as per mainline kernel

[3]v1 https://patchwork.ozlabs.org/cover/1201206/
[4]v2 https://patchwork.ozlabs.org/cover/1215217/
[5]v3 https://www.mail-archive.com/u-boot at lists.denx.de/msg351859.html
[6]v4 https://patchwork.ozlabs.org/cover/1227205/
[7]v5 https://patchwork.ozlabs.org/cover/1232879/

-Anand

Anand Moon (5):
  mmc: meson-gx: Fix clk phase tuning for MMC
  mmc: meson-gx: Use proper compatible string as per the dts
  arm: dts: gx: Move common nodes to the -u-boot.dtsi
  arm: dts: g12: Move common nodes to the -u-boot.dtsi
  arm: dts: s400: Move common nodes to the -u-boot.dtsi

 arch/arm/dts/meson-axg-s400-u-boot.dtsi       | 16 +++++
 arch/arm/dts/meson-axg-s400.dts               |  9 ---
 arch/arm/dts/meson-g12-common-u-boot.dtsi     | 12 ++++
 arch/arm/dts/meson-g12a-sei510.dts            |  9 ---
 arch/arm/dts/meson-g12a-u200.dts              |  9 ---
 arch/arm/dts/meson-g12b-odroid-n2.dts         |  9 ---
 arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++
 arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---
 arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---
 arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 --
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----
 arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----
 arch/arm/dts/meson-khadas-vim3.dtsi           |  9 ---
 arch/arm/dts/meson-sm1-sei610.dts             |  9 ---
 arch/arm/include/asm/arch-meson/sd_emmc.h     | 31 +++++++---
 drivers/mmc/meson_gx_mmc.c                    | 58 ++++++++++++++++---
 19 files changed, 114 insertions(+), 143 deletions(-)

-- 
2.25.0

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 0/5] Odroid n2 using eMMC would fail to boot up
@ 2020-02-09 11:05 ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Here are some small changes to fix booting of Odroid N2 using eMMC.
Fixed the clk tunnig during mmc initialization.
Added two new patches to fix warning

Build and tested on top of below patches
[0] https://patchwork.ozlabs.org/patch/1213648/
[1] https://patchwork.ozlabs.org/patch/1213650/

Tested on below eMMC module on Odroid N2 and C2
new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
old back   - eMMC CGND3R 58.2 GiB MMC 5.0

Prevoius changes: 
Fixed the clk tuning as per mainline kernel

[3]v1 https://patchwork.ozlabs.org/cover/1201206/
[4]v2 https://patchwork.ozlabs.org/cover/1215217/
[5]v3 https://www.mail-archive.com/u-boot@lists.denx.de/msg351859.html
[6]v4 https://patchwork.ozlabs.org/cover/1227205/
[7]v5 https://patchwork.ozlabs.org/cover/1232879/

-Anand

Anand Moon (5):
  mmc: meson-gx: Fix clk phase tuning for MMC
  mmc: meson-gx: Use proper compatible string as per the dts
  arm: dts: gx: Move common nodes to the -u-boot.dtsi
  arm: dts: g12: Move common nodes to the -u-boot.dtsi
  arm: dts: s400: Move common nodes to the -u-boot.dtsi

 arch/arm/dts/meson-axg-s400-u-boot.dtsi       | 16 +++++
 arch/arm/dts/meson-axg-s400.dts               |  9 ---
 arch/arm/dts/meson-g12-common-u-boot.dtsi     | 12 ++++
 arch/arm/dts/meson-g12a-sei510.dts            |  9 ---
 arch/arm/dts/meson-g12a-u200.dts              |  9 ---
 arch/arm/dts/meson-g12b-odroid-n2.dts         |  9 ---
 arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++
 arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---
 arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---
 arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 --
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----
 arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----
 arch/arm/dts/meson-khadas-vim3.dtsi           |  9 ---
 arch/arm/dts/meson-sm1-sei610.dts             |  9 ---
 arch/arm/include/asm/arch-meson/sd_emmc.h     | 31 +++++++---
 drivers/mmc/meson_gx_mmc.c                    | 58 ++++++++++++++++---
 19 files changed, 114 insertions(+), 143 deletions(-)

-- 
2.25.0


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-09 11:05 ` Anand Moon
@ 2020-02-09 11:05   ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

As per mainline line kernel fix the clk tuning phase for mmc,
set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
As per S905, S905X, AGX and S922X datasheet set the default
values for clk tuning.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Changes from previous
v5  Fix the commit message, configure as per mainline kernel.
    drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.

v4  Fix the update mask value using FIELD_PREP macro.

v3  Fix the initialization of core clk tunning phase as per datasheet.
    Fix the commit message.

v2: Fix the clk phase macro to support PHASE_180
    drop the wrong CLK_CORE_PHASE_MASK macro.

v1: use the mainline kernel tuning for clk tuning.

Fixed the commmit messages.
Patch v1:
https://patchwork.ozlabs.org/patch/1201208/

Before these changes.
    clock is enabled (380953Hz)
    clock is enabled (25000000Hz)
After these changes
    clock is enabled (380953Hz)
    clock is enabled (25000000Hz)
    clock is enabled (52000000Hz)
Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
---
 arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
 drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
 2 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..f4299485dc 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
 #define __SD_EMMC_H__
 
 #include <mmc.h>
+#include <linux/bitops.h>
 
 #define SDIO_PORT_A			0
 #define SDIO_PORT_B			1
@@ -19,15 +20,20 @@
 #define   CLK_MAX_DIV			63
 #define   CLK_SRC_24M			(0 << 6)
 #define   CLK_SRC_DIV2			(1 << 6)
-#define   CLK_CO_PHASE_000		(0 << 8)
-#define   CLK_CO_PHASE_090		(1 << 8)
-#define   CLK_CO_PHASE_180		(2 << 8)
-#define   CLK_CO_PHASE_270		(3 << 8)
-#define   CLK_TX_PHASE_000		(0 << 10)
-#define   CLK_TX_PHASE_090		(1 << 10)
-#define   CLK_TX_PHASE_180		(2 << 10)
-#define   CLK_TX_PHASE_270		(3 << 10)
-#define   CLK_ALWAYS_ON			BIT(24)
+
+#define   CRYSTAL_24MHZ			0
+#define   CLK_PHASE_0			0
+#define   CLK_PHASE_180			2
+
+#define   CLK_DIV_MASK			GENMASK(5, 0)
+#define   CLK_SRC_MASK			GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK		GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASK		GENMASK(11, 10)
+#define   CLK_RX_PHASE_MASK		GENMASK(13, 12)
+
+#define   CLK_V2_ALWAYS_ON		BIT(24)
+
+#define   CLK_V3_ALWAYS_ON		BIT(28)
 
 #define MESON_SD_EMMC_CFG		0x44
 #define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..b013c7c5fb 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -16,6 +16,10 @@
 #include <asm/arch/sd_emmc.h>
 #include <linux/log2.h>
 
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
 static inline void *get_regbase(const struct mmc *mmc)
 {
 	struct meson_mmc_platdata *pdata = mmc->priv;
@@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 	}
 	clk_div = DIV_ROUND_UP(clk, mmc->clock);
 
-	/* 180 phase core clock */
-	meson_mmc_clk |= CLK_CO_PHASE_180;
-
-	/* 180 phase tx clock */
-	meson_mmc_clk |= CLK_TX_PHASE_000;
+	/* Clock divider */
+	meson_mmc_clk |= CLK_DIV_MASK;
+	/* Clock source : Crystal 24MHz */
+	meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
+	/* Core clock phase 2:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+	/* TX clock phase 0:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
+	/* RX clock phase 0:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+
+#ifdef CONFIG_MESON_GX
+	/* clk always on */
+	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+#endif
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
+	/* clk always on */
+	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+#endif
 
 	/* clock settings */
 	meson_mmc_clk |= clk_src;
-- 
2.25.0

^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-09 11:05   ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

As per mainline line kernel fix the clk tuning phase for mmc,
set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
As per S905, S905X, AGX and S922X datasheet set the default
values for clk tuning.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Changes from previous
v5  Fix the commit message, configure as per mainline kernel.
    drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.

v4  Fix the update mask value using FIELD_PREP macro.

v3  Fix the initialization of core clk tunning phase as per datasheet.
    Fix the commit message.

v2: Fix the clk phase macro to support PHASE_180
    drop the wrong CLK_CORE_PHASE_MASK macro.

v1: use the mainline kernel tuning for clk tuning.

Fixed the commmit messages.
Patch v1:
https://patchwork.ozlabs.org/patch/1201208/

Before these changes.
    clock is enabled (380953Hz)
    clock is enabled (25000000Hz)
After these changes
    clock is enabled (380953Hz)
    clock is enabled (25000000Hz)
    clock is enabled (52000000Hz)
Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
---
 arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
 drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
 2 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..f4299485dc 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
 #define __SD_EMMC_H__
 
 #include <mmc.h>
+#include <linux/bitops.h>
 
 #define SDIO_PORT_A			0
 #define SDIO_PORT_B			1
@@ -19,15 +20,20 @@
 #define   CLK_MAX_DIV			63
 #define   CLK_SRC_24M			(0 << 6)
 #define   CLK_SRC_DIV2			(1 << 6)
-#define   CLK_CO_PHASE_000		(0 << 8)
-#define   CLK_CO_PHASE_090		(1 << 8)
-#define   CLK_CO_PHASE_180		(2 << 8)
-#define   CLK_CO_PHASE_270		(3 << 8)
-#define   CLK_TX_PHASE_000		(0 << 10)
-#define   CLK_TX_PHASE_090		(1 << 10)
-#define   CLK_TX_PHASE_180		(2 << 10)
-#define   CLK_TX_PHASE_270		(3 << 10)
-#define   CLK_ALWAYS_ON			BIT(24)
+
+#define   CRYSTAL_24MHZ			0
+#define   CLK_PHASE_0			0
+#define   CLK_PHASE_180			2
+
+#define   CLK_DIV_MASK			GENMASK(5, 0)
+#define   CLK_SRC_MASK			GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK		GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASK		GENMASK(11, 10)
+#define   CLK_RX_PHASE_MASK		GENMASK(13, 12)
+
+#define   CLK_V2_ALWAYS_ON		BIT(24)
+
+#define   CLK_V3_ALWAYS_ON		BIT(28)
 
 #define MESON_SD_EMMC_CFG		0x44
 #define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..b013c7c5fb 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -16,6 +16,10 @@
 #include <asm/arch/sd_emmc.h>
 #include <linux/log2.h>
 
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
 static inline void *get_regbase(const struct mmc *mmc)
 {
 	struct meson_mmc_platdata *pdata = mmc->priv;
@@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 	}
 	clk_div = DIV_ROUND_UP(clk, mmc->clock);
 
-	/* 180 phase core clock */
-	meson_mmc_clk |= CLK_CO_PHASE_180;
-
-	/* 180 phase tx clock */
-	meson_mmc_clk |= CLK_TX_PHASE_000;
+	/* Clock divider */
+	meson_mmc_clk |= CLK_DIV_MASK;
+	/* Clock source : Crystal 24MHz */
+	meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
+	/* Core clock phase 2:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+	/* TX clock phase 0:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
+	/* RX clock phase 0:180 */
+	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+
+#ifdef CONFIG_MESON_GX
+	/* clk always on */
+	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+#endif
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
+	/* clk always on */
+	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+#endif
 
 	/* clock settings */
 	meson_mmc_clk |= clk_src;
-- 
2.25.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
  2020-02-09 11:05 ` Anand Moon
@ 2020-02-09 11:05   ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

Use proper compatible string as per the dts so that mmc driver
could be tuned properly. SoC family S905, S905X have common clk
tuning parameters setting, while AGX and G12 have common clk tuning
parameters setting for mmc driver.

Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
No changes.
---
 arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
 drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
 2 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index f4299485dc..83142d5d3f 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -13,6 +13,12 @@
 #define SDIO_PORT_B			1
 #define SDIO_PORT_C			2
 
+enum mmc_compatible {
+        MMC_COMPATIBLE_GXBB,
+        MMC_COMPATIBLE_GX,
+        MMC_COMPATIBLE_AXG,
+};
+
 #define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
 #define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
 
@@ -87,6 +93,7 @@
 struct meson_mmc_platdata {
 	struct mmc_config cfg;
 	struct mmc mmc;
+	int compat;
 	void *regbase;
 	void *w_buf;
 };
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index b013c7c5fb..1aefe360c4 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
 	writel(val, get_regbase(mmc) + offset);
 }
 
-static void meson_mmc_config_clock(struct mmc *mmc)
+static void meson_mmc_config_clock(struct mmc *mmc,
+				   struct meson_mmc_platdata *pdata)
 {
 	uint32_t meson_mmc_clk = 0;
 	unsigned int clk, clk_src, clk_div;
@@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 	/* RX clock phase 0:180 */
 	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
 
-#ifdef CONFIG_MESON_GX
-	/* clk always on */
-	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
-#endif
-#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
-	/* clk always on */
-	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
-#endif
+	switch (pdata->compat) {
+	case MMC_COMPATIBLE_GXBB:
+	case MMC_COMPATIBLE_GX:
+		/* clk always on */
+		meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+		break;
+	case MMC_COMPATIBLE_AXG:
+		/* clk always on */
+		meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+		break;
+	default:
+		debug("no compatible supported");
+		break;
+	}
 
 	/* clock settings */
 	meson_mmc_clk |= clk_src;
@@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 static int meson_dm_mmc_set_ios(struct udevice *dev)
 {
 	struct mmc *mmc = mmc_get_mmc_dev(dev);
+	struct meson_mmc_platdata *pdata =
+		(struct meson_mmc_platdata *)dev_get_driver_data(dev);
 	uint32_t meson_mmc_cfg;
 
-	meson_mmc_config_clock(mmc);
+	meson_mmc_config_clock(mmc, pdata);
 
 	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
 
@@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
 	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
 }
 
+static const struct meson_mmc_platdata gxbb_data = {
+        .compat = MMC_COMPATIBLE_GXBB,
+};
+
+static const struct meson_mmc_platdata gx_data = {
+        .compat = MMC_COMPATIBLE_GX,
+};
+
+static const struct meson_mmc_platdata axg_data = {
+        .compat = MMC_COMPATIBLE_AXG,
+};
+
 static const struct udevice_id meson_mmc_match[] = {
-	{ .compatible = "amlogic,meson-gx-mmc" },
-	{ .compatible = "amlogic,meson-axg-mmc" },
+	{ .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
+	{ .compatible = "amlogic,meson-gx-mmc",	.data = (ulong)&gx_data },
+	{ .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
 	{ /* sentinel */ }
 };
 
-- 
2.25.0

^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
@ 2020-02-09 11:05   ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Use proper compatible string as per the dts so that mmc driver
could be tuned properly. SoC family S905, S905X have common clk
tuning parameters setting, while AGX and G12 have common clk tuning
parameters setting for mmc driver.

Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
No changes.
---
 arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
 drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
 2 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index f4299485dc..83142d5d3f 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -13,6 +13,12 @@
 #define SDIO_PORT_B			1
 #define SDIO_PORT_C			2
 
+enum mmc_compatible {
+        MMC_COMPATIBLE_GXBB,
+        MMC_COMPATIBLE_GX,
+        MMC_COMPATIBLE_AXG,
+};
+
 #define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
 #define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
 
@@ -87,6 +93,7 @@
 struct meson_mmc_platdata {
 	struct mmc_config cfg;
 	struct mmc mmc;
+	int compat;
 	void *regbase;
 	void *w_buf;
 };
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index b013c7c5fb..1aefe360c4 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
 	writel(val, get_regbase(mmc) + offset);
 }
 
-static void meson_mmc_config_clock(struct mmc *mmc)
+static void meson_mmc_config_clock(struct mmc *mmc,
+				   struct meson_mmc_platdata *pdata)
 {
 	uint32_t meson_mmc_clk = 0;
 	unsigned int clk, clk_src, clk_div;
@@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 	/* RX clock phase 0:180 */
 	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
 
-#ifdef CONFIG_MESON_GX
-	/* clk always on */
-	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
-#endif
-#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
-	/* clk always on */
-	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
-#endif
+	switch (pdata->compat) {
+	case MMC_COMPATIBLE_GXBB:
+	case MMC_COMPATIBLE_GX:
+		/* clk always on */
+		meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+		break;
+	case MMC_COMPATIBLE_AXG:
+		/* clk always on */
+		meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+		break;
+	default:
+		debug("no compatible supported");
+		break;
+	}
 
 	/* clock settings */
 	meson_mmc_clk |= clk_src;
@@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 static int meson_dm_mmc_set_ios(struct udevice *dev)
 {
 	struct mmc *mmc = mmc_get_mmc_dev(dev);
+	struct meson_mmc_platdata *pdata =
+		(struct meson_mmc_platdata *)dev_get_driver_data(dev);
 	uint32_t meson_mmc_cfg;
 
-	meson_mmc_config_clock(mmc);
+	meson_mmc_config_clock(mmc, pdata);
 
 	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
 
@@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
 	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
 }
 
+static const struct meson_mmc_platdata gxbb_data = {
+        .compat = MMC_COMPATIBLE_GXBB,
+};
+
+static const struct meson_mmc_platdata gx_data = {
+        .compat = MMC_COMPATIBLE_GX,
+};
+
+static const struct meson_mmc_platdata axg_data = {
+        .compat = MMC_COMPATIBLE_AXG,
+};
+
 static const struct udevice_id meson_mmc_match[] = {
-	{ .compatible = "amlogic,meson-gx-mmc" },
-	{ .compatible = "amlogic,meson-axg-mmc" },
+	{ .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
+	{ .compatible = "amlogic,meson-gx-mmc",	.data = (ulong)&gx_data },
+	{ .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
 	{ /* sentinel */ }
 };
 
-- 
2.25.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05 ` Anand Moon
@ 2020-02-09 11:05   ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

Move u-boot specific common nodes in the dts files to
meson-gx-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
no changes from previous
---
 arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
 arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
 arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
 arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
 arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
 9 files changed, 15 insertions(+), 71 deletions(-)

diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index b84e5edba4..13be3a7b8f 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -8,6 +8,21 @@
 	soc {
 		u-boot,dm-pre-reloc;
 	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+		serial2 = &uart_AO_B;
+		ethernet0 = &ethmac;
+		spi0 = &spifc;
+		mmc0 = &sd_emmc_a;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &vpu {
diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
index cbe99bd4e0..11690d6c46 100644
--- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
@@ -11,15 +11,6 @@
 / {
 	compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 54954b314a..f8cd76a2ef 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -14,15 +14,6 @@
 	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
 	model = "Hardkernel ODROID-C2";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
index 0be0f2a5d2..c9822e50f9 100644
--- a/arch/arm/dts/meson-gxbb-p20x.dtsi
+++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
@@ -8,15 +8,6 @@
 #include "meson-gxbb.dtsi"
 
 / {
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
index 82b1c48511..4f9072a83e 100644
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -16,16 +16,6 @@
 		     "amlogic,meson-gxl";
 	model = "Libre Computer Board AML-S805X-AC";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-		spi0 = &spifc;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		/*
 		 * The pads are present but no connector is soldered on
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index ceb34afe42..072e4575d2 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -26,11 +26,6 @@
 		};
 	};
 
-	aliases {
-		serial2 = &uart_AO_B;
-		ethernet0 = &ethmac;
-	};
-
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
index a23252efc6..8d3965ab42 100644
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
@@ -15,15 +15,6 @@
 	compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
 	model = "Libre Computer Board AML-S905X-CC";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index a1b31013ab..70f437fc3a 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -13,16 +13,6 @@
 #include "meson-gxl-s905x.dtsi"
 
 / {
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index 782e9edac8..4e68e289d3 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -16,16 +16,6 @@
 	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
 	model = "Khadas VIM2";
 
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-		serial2 = &uart_AO_B;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
-- 
2.25.0

^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 11:05   ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Move u-boot specific common nodes in the dts files to
meson-gx-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
no changes from previous
---
 arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
 arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
 arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
 arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
 arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
 9 files changed, 15 insertions(+), 71 deletions(-)

diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index b84e5edba4..13be3a7b8f 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -8,6 +8,21 @@
 	soc {
 		u-boot,dm-pre-reloc;
 	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+		serial2 = &uart_AO_B;
+		ethernet0 = &ethmac;
+		spi0 = &spifc;
+		mmc0 = &sd_emmc_a;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &vpu {
diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
index cbe99bd4e0..11690d6c46 100644
--- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
@@ -11,15 +11,6 @@
 / {
 	compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 54954b314a..f8cd76a2ef 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -14,15 +14,6 @@
 	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
 	model = "Hardkernel ODROID-C2";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
index 0be0f2a5d2..c9822e50f9 100644
--- a/arch/arm/dts/meson-gxbb-p20x.dtsi
+++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
@@ -8,15 +8,6 @@
 #include "meson-gxbb.dtsi"
 
 / {
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
index 82b1c48511..4f9072a83e 100644
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -16,16 +16,6 @@
 		     "amlogic,meson-gxl";
 	model = "Libre Computer Board AML-S805X-AC";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-		spi0 = &spifc;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		/*
 		 * The pads are present but no connector is soldered on
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index ceb34afe42..072e4575d2 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -26,11 +26,6 @@
 		};
 	};
 
-	aliases {
-		serial2 = &uart_AO_B;
-		ethernet0 = &ethmac;
-	};
-
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
index a23252efc6..8d3965ab42 100644
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
@@ -15,15 +15,6 @@
 	compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
 	model = "Libre Computer Board AML-S905X-CC";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index a1b31013ab..70f437fc3a 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -13,16 +13,6 @@
 #include "meson-gxl-s905x.dtsi"
 
 / {
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index 782e9edac8..4e68e289d3 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -16,16 +16,6 @@
 	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
 	model = "Khadas VIM2";
 
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-		serial2 = &uart_AO_B;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
-- 
2.25.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05 ` Anand Moon
@ 2020-02-09 11:05   ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

Move u-boot specific common nodes in the dts files to
meson-g12-common-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
No changes from previous patch
---
 arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
 arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
 arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
 arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
 arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
 arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
 6 files changed, 12 insertions(+), 45 deletions(-)

diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index 38fd3d3feb..347b8ded22 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -8,6 +8,18 @@
 	soc {
 		u-boot,dm-pre-reloc;
 	};
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		mmc0 = &sd_emmc_a;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &canvas {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
index c7a8736885..c6a48ebbe5 100644
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -28,11 +28,6 @@
 		};
 	};
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
 	mono_dac: audio-codec-0 {
 		compatible = "maxim,max98357a";
 		#sound-dai-cells = <0>;
@@ -49,10 +44,6 @@
 		sound-name-prefix = "MIC";
 	};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 8551fbd4a4..8be7b6985b 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -13,15 +13,6 @@
 	compatible = "amlogic,u200", "amlogic,g12a";
 	model = "Amlogic Meson G12A U200 Development Board";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 42f1540575..a37f66a5e0 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -15,15 +15,6 @@
 	compatible = "hardkernel,odroid-n2", "amlogic,g12b";
 	model = "Hardkernel ODROID-N2";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 8647da7d66..c6b0ce9a88 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -11,15 +11,6 @@
 / {
 	model = "Khadas VIM3";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
index 3435aaa4e8..4372708811 100644
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ b/arch/arm/dts/meson-sm1-sei610.dts
@@ -14,15 +14,6 @@
 	compatible = "seirobotics,sei610", "amlogic,sm1";
 	model = "SEI Robotics SEI610";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	emmc_pwrseq: emmc-pwrseq {
 		compatible = "mmc-pwrseq-emmc";
 		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
-- 
2.25.0

^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 11:05   ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Move u-boot specific common nodes in the dts files to
meson-g12-common-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
No changes from previous patch
---
 arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
 arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
 arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
 arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
 arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
 arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
 6 files changed, 12 insertions(+), 45 deletions(-)

diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index 38fd3d3feb..347b8ded22 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -8,6 +8,18 @@
 	soc {
 		u-boot,dm-pre-reloc;
 	};
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		mmc0 = &sd_emmc_a;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &canvas {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
index c7a8736885..c6a48ebbe5 100644
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -28,11 +28,6 @@
 		};
 	};
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
 	mono_dac: audio-codec-0 {
 		compatible = "maxim,max98357a";
 		#sound-dai-cells = <0>;
@@ -49,10 +44,6 @@
 		sound-name-prefix = "MIC";
 	};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 8551fbd4a4..8be7b6985b 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -13,15 +13,6 @@
 	compatible = "amlogic,u200", "amlogic,g12a";
 	model = "Amlogic Meson G12A U200 Development Board";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	cvbs-connector {
 		compatible = "composite-video-connector";
 
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 42f1540575..a37f66a5e0 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -15,15 +15,6 @@
 	compatible = "hardkernel,odroid-n2", "amlogic,g12b";
 	model = "Hardkernel ODROID-N2";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 8647da7d66..c6b0ce9a88 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -11,15 +11,6 @@
 / {
 	model = "Khadas VIM3";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
index 3435aaa4e8..4372708811 100644
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ b/arch/arm/dts/meson-sm1-sei610.dts
@@ -14,15 +14,6 @@
 	compatible = "seirobotics,sei610", "amlogic,sm1";
 	model = "SEI Robotics SEI610";
 
-	aliases {
-		serial0 = &uart_AO;
-		ethernet0 = &ethmac;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	emmc_pwrseq: emmc-pwrseq {
 		compatible = "mmc-pwrseq-emmc";
 		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
-- 
2.25.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05 ` Anand Moon
@ 2020-02-09 11:05   ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: u-boot

Move u-boot specific common nodes in the dts files to
meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
no changes from previous changes
---
 arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
 arch/arm/dts/meson-axg-s400.dts         |  9 ---------
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
index c46eb3f38d..74241e9fcd 100644
--- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -2,6 +2,22 @@
 /*
  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
  */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
 
 /* wifi module */
 &sd_emmc_b {
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7b..feb84255ad 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -55,11 +55,6 @@
 		};
 	};
 
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-	};
-
 	linein: audio-codec at 0 {
 		#sound-dai-cells = <0>;
 		compatible = "everest,es7241";
@@ -100,10 +95,6 @@
 		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
 	};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory at 0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
-- 
2.25.0

^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 11:05   ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 11:05 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Move u-boot specific common nodes in the dts files to
meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.

mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
no changes from previous changes
---
 arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
 arch/arm/dts/meson-axg-s400.dts         |  9 ---------
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
index c46eb3f38d..74241e9fcd 100644
--- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -2,6 +2,22 @@
 /*
  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
  */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
 
 /* wifi module */
 &sd_emmc_b {
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7b..feb84255ad 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -55,11 +55,6 @@
 		};
 	};
 
-	aliases {
-		serial0 = &uart_AO;
-		serial1 = &uart_A;
-	};
-
 	linein: audio-codec@0 {
 		#sound-dai-cells = <0>;
 		compatible = "everest,es7241";
@@ -100,10 +95,6 @@
 		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
 	};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
-- 
2.25.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

* [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05   ` Anand Moon
@ 2020-02-09 12:58     ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-gx-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1

The mmc aliases are u-boot specific, so only those should be
moved into the meson-gx-u-boot.dtsi.

Please keep the other aliases in the their linux sync'ed files.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> no changes from previous
> ---
>  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
>  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
>  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
>  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
>  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
>  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
>  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
>  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
>  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
>  9 files changed, 15 insertions(+), 71 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
> index b84e5edba4..13be3a7b8f 100644
> --- a/arch/arm/dts/meson-gx-u-boot.dtsi
> +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
> @@ -8,6 +8,21 @@
>  	soc {
>  		u-boot,dm-pre-reloc;
>  	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		serial2 = &uart_AO_B;
> +		ethernet0 = &ethmac;
> +		spi0 = &spifc;
> +		mmc0 = &sd_emmc_a;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
>  };
>  
>  &vpu {
> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> index cbe99bd4e0..11690d6c46 100644
> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> @@ -11,15 +11,6 @@
>  / {
>  	compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
> index 54954b314a..f8cd76a2ef 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> @@ -14,15 +14,6 @@
>  	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
>  	model = "Hardkernel ODROID-C2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
> index 0be0f2a5d2..c9822e50f9 100644
> --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
> +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
> @@ -8,15 +8,6 @@
>  #include "meson-gxbb.dtsi"
>  
>  / {
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> index 82b1c48511..4f9072a83e 100644
> --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> @@ -16,16 +16,6 @@
>  		     "amlogic,meson-gxl";
>  	model = "Libre Computer Board AML-S805X-AC";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -		spi0 = &spifc;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		/*
>  		 * The pads are present but no connector is soldered on
> diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> index ceb34afe42..072e4575d2 100644
> --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> @@ -26,11 +26,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial2 = &uart_AO_B;
> -		ethernet0 = &ethmac;
> -	};
> -
>  	gpio-keys-polled {
>  		compatible = "gpio-keys-polled";
>  		#address-cells = <1>;
> diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> index a23252efc6..8d3965ab42 100644
> --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> @@ -15,15 +15,6 @@
>  	compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
>  	model = "Libre Computer Board AML-S905X-CC";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> index a1b31013ab..70f437fc3a 100644
> --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> @@ -13,16 +13,6 @@
>  #include "meson-gxl-s905x.dtsi"
>  
>  / {
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> index 782e9edac8..4e68e289d3 100644
> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> @@ -16,16 +16,6 @@
>  	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
>  	model = "Khadas VIM2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -		serial2 = &uart_AO_B;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 12:58     ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: Anand Moon, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-gx-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1

The mmc aliases are u-boot specific, so only those should be
moved into the meson-gx-u-boot.dtsi.

Please keep the other aliases in the their linux sync'ed files.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> no changes from previous
> ---
>  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
>  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
>  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
>  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
>  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
>  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
>  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
>  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
>  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
>  9 files changed, 15 insertions(+), 71 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
> index b84e5edba4..13be3a7b8f 100644
> --- a/arch/arm/dts/meson-gx-u-boot.dtsi
> +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
> @@ -8,6 +8,21 @@
>  	soc {
>  		u-boot,dm-pre-reloc;
>  	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		serial2 = &uart_AO_B;
> +		ethernet0 = &ethmac;
> +		spi0 = &spifc;
> +		mmc0 = &sd_emmc_a;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
>  };
>  
>  &vpu {
> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> index cbe99bd4e0..11690d6c46 100644
> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> @@ -11,15 +11,6 @@
>  / {
>  	compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
> index 54954b314a..f8cd76a2ef 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> @@ -14,15 +14,6 @@
>  	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
>  	model = "Hardkernel ODROID-C2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
> index 0be0f2a5d2..c9822e50f9 100644
> --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
> +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
> @@ -8,15 +8,6 @@
>  #include "meson-gxbb.dtsi"
>  
>  / {
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> index 82b1c48511..4f9072a83e 100644
> --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> @@ -16,16 +16,6 @@
>  		     "amlogic,meson-gxl";
>  	model = "Libre Computer Board AML-S805X-AC";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -		spi0 = &spifc;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		/*
>  		 * The pads are present but no connector is soldered on
> diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> index ceb34afe42..072e4575d2 100644
> --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> @@ -26,11 +26,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial2 = &uart_AO_B;
> -		ethernet0 = &ethmac;
> -	};
> -
>  	gpio-keys-polled {
>  		compatible = "gpio-keys-polled";
>  		#address-cells = <1>;
> diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> index a23252efc6..8d3965ab42 100644
> --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> @@ -15,15 +15,6 @@
>  	compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
>  	model = "Libre Computer Board AML-S905X-CC";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> index a1b31013ab..70f437fc3a 100644
> --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> @@ -13,16 +13,6 @@
>  #include "meson-gxl-s905x.dtsi"
>  
>  / {
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> index 782e9edac8..4e68e289d3 100644
> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> @@ -16,16 +16,6 @@
>  	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
>  	model = "Khadas VIM2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -		serial2 = &uart_AO_B;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05   ` Anand Moon
@ 2020-02-09 12:58     ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-g12-common-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1

Same as patch 4.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> No changes from previous patch
> ---
>  arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
>  arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
>  arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
>  arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
>  arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
>  arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
>  6 files changed, 12 insertions(+), 45 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> index 38fd3d3feb..347b8ded22 100644
> --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
> +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> @@ -8,6 +8,18 @@
>  	soc {
>  		u-boot,dm-pre-reloc;
>  	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		ethernet0 = &ethmac;
> +		mmc0 = &sd_emmc_a;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
>  };
>  
>  &canvas {
> diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
> index c7a8736885..c6a48ebbe5 100644
> --- a/arch/arm/dts/meson-g12a-sei510.dts
> +++ b/arch/arm/dts/meson-g12a-sei510.dts
> @@ -28,11 +28,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
>  	mono_dac: audio-codec-0 {
>  		compatible = "maxim,max98357a";
>  		#sound-dai-cells = <0>;
> @@ -49,10 +44,6 @@
>  		sound-name-prefix = "MIC";
>  	};
>  
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
> index 8551fbd4a4..8be7b6985b 100644
> --- a/arch/arm/dts/meson-g12a-u200.dts
> +++ b/arch/arm/dts/meson-g12a-u200.dts
> @@ -13,15 +13,6 @@
>  	compatible = "amlogic,u200", "amlogic,g12a";
>  	model = "Amlogic Meson G12A U200 Development Board";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
> index 42f1540575..a37f66a5e0 100644
> --- a/arch/arm/dts/meson-g12b-odroid-n2.dts
> +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
> @@ -15,15 +15,6 @@
>  	compatible = "hardkernel,odroid-n2", "amlogic,g12b";
>  	model = "Hardkernel ODROID-N2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
> index 8647da7d66..c6b0ce9a88 100644
> --- a/arch/arm/dts/meson-khadas-vim3.dtsi
> +++ b/arch/arm/dts/meson-khadas-vim3.dtsi
> @@ -11,15 +11,6 @@
>  / {
>  	model = "Khadas VIM3";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
> index 3435aaa4e8..4372708811 100644
> --- a/arch/arm/dts/meson-sm1-sei610.dts
> +++ b/arch/arm/dts/meson-sm1-sei610.dts
> @@ -14,15 +14,6 @@
>  	compatible = "seirobotics,sei610", "amlogic,sm1";
>  	model = "SEI Robotics SEI610";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	emmc_pwrseq: emmc-pwrseq {
>  		compatible = "mmc-pwrseq-emmc";
>  		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 12:58     ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: Anand Moon, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-g12-common-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1

Same as patch 4.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> No changes from previous patch
> ---
>  arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
>  arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
>  arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
>  arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
>  arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
>  arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
>  6 files changed, 12 insertions(+), 45 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> index 38fd3d3feb..347b8ded22 100644
> --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
> +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> @@ -8,6 +8,18 @@
>  	soc {
>  		u-boot,dm-pre-reloc;
>  	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		ethernet0 = &ethmac;
> +		mmc0 = &sd_emmc_a;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
>  };
>  
>  &canvas {
> diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
> index c7a8736885..c6a48ebbe5 100644
> --- a/arch/arm/dts/meson-g12a-sei510.dts
> +++ b/arch/arm/dts/meson-g12a-sei510.dts
> @@ -28,11 +28,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
>  	mono_dac: audio-codec-0 {
>  		compatible = "maxim,max98357a";
>  		#sound-dai-cells = <0>;
> @@ -49,10 +44,6 @@
>  		sound-name-prefix = "MIC";
>  	};
>  
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
> index 8551fbd4a4..8be7b6985b 100644
> --- a/arch/arm/dts/meson-g12a-u200.dts
> +++ b/arch/arm/dts/meson-g12a-u200.dts
> @@ -13,15 +13,6 @@
>  	compatible = "amlogic,u200", "amlogic,g12a";
>  	model = "Amlogic Meson G12A U200 Development Board";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	cvbs-connector {
>  		compatible = "composite-video-connector";
>  
> diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
> index 42f1540575..a37f66a5e0 100644
> --- a/arch/arm/dts/meson-g12b-odroid-n2.dts
> +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
> @@ -15,15 +15,6 @@
>  	compatible = "hardkernel,odroid-n2", "amlogic,g12b";
>  	model = "Hardkernel ODROID-N2";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
> index 8647da7d66..c6b0ce9a88 100644
> --- a/arch/arm/dts/meson-khadas-vim3.dtsi
> +++ b/arch/arm/dts/meson-khadas-vim3.dtsi
> @@ -11,15 +11,6 @@
>  / {
>  	model = "Khadas VIM3";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x80000000>;
> diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
> index 3435aaa4e8..4372708811 100644
> --- a/arch/arm/dts/meson-sm1-sei610.dts
> +++ b/arch/arm/dts/meson-sm1-sei610.dts
> @@ -14,15 +14,6 @@
>  	compatible = "seirobotics,sei610", "amlogic,sm1";
>  	model = "SEI Robotics SEI610";
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		ethernet0 = &ethmac;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	emmc_pwrseq: emmc-pwrseq {
>  		compatible = "mmc-pwrseq-emmc";
>  		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
  2020-02-09 11:05   ` Anand Moon
@ 2020-02-09 12:58     ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1


Same as patch 4.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> no changes from previous changes
> ---
>  arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
>  arch/arm/dts/meson-axg-s400.dts         |  9 ---------
>  2 files changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> index c46eb3f38d..74241e9fcd 100644
> --- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> @@ -2,6 +2,22 @@
>  /*
>   * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
>   */
> +/ {
> +	soc {
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
>  
>  /* wifi module */
>  &sd_emmc_b {
> diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
> index 18778ada7b..feb84255ad 100644
> --- a/arch/arm/dts/meson-axg-s400.dts
> +++ b/arch/arm/dts/meson-axg-s400.dts
> @@ -55,11 +55,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -	};
> -
>  	linein: audio-codec at 0 {
>  		#sound-dai-cells = <0>;
>  		compatible = "everest,es7241";
> @@ -100,10 +95,6 @@
>  		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
>  	};
>  
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory at 0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 12:58     ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 12:58 UTC (permalink / raw)
  To: Anand Moon, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Move u-boot specific common nodes in the dts files to
> meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
> dts[i] files up-to-date with the ones in kernel,
> but at the same time allowing the u-boot to add its own
> properties to the existing nodes.
> Also add missing mmc alias to dts nodes to avoid
> below debug warning.
> 
> mmc_bind: alias ret=-2, devnum=-1
> mmc_bind: alias ret=-2, devnum=-1


Same as patch 4.

Neil

> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> no changes from previous changes
> ---
>  arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
>  arch/arm/dts/meson-axg-s400.dts         |  9 ---------
>  2 files changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> index c46eb3f38d..74241e9fcd 100644
> --- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> @@ -2,6 +2,22 @@
>  /*
>   * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
>   */
> +/ {
> +	soc {
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		mmc1 = &sd_emmc_b;
> +		mmc2 = &sd_emmc_c;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
>  
>  /* wifi module */
>  &sd_emmc_b {
> diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
> index 18778ada7b..feb84255ad 100644
> --- a/arch/arm/dts/meson-axg-s400.dts
> +++ b/arch/arm/dts/meson-axg-s400.dts
> @@ -55,11 +55,6 @@
>  		};
>  	};
>  
> -	aliases {
> -		serial0 = &uart_AO;
> -		serial1 = &uart_A;
> -	};
> -
>  	linein: audio-codec@0 {
>  		#sound-dai-cells = <0>;
>  		compatible = "everest,es7241";
> @@ -100,10 +95,6 @@
>  		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
>  	};
>  
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0 0x0 0x40000000>;
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
  2020-02-09 11:05   ` Anand Moon
@ 2020-02-09 13:01     ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 13:01 UTC (permalink / raw)
  To: u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Use proper compatible string as per the dts so that mmc driver
> could be tuned properly. SoC family S905, S905X have common clk
> tuning parameters setting, while AGX and G12 have common clk tuning
> parameters setting for mmc driver.
> 
> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> No changes.
> ---
>  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
>  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
>  2 files changed, 41 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index f4299485dc..83142d5d3f 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -13,6 +13,12 @@
>  #define SDIO_PORT_B			1
>  #define SDIO_PORT_C			2
>  
> +enum mmc_compatible {
> +        MMC_COMPATIBLE_GXBB,
> +        MMC_COMPATIBLE_GX,
> +        MMC_COMPATIBLE_AXG,
> +};
> +
>  #define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
>  #define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
>  
> @@ -87,6 +93,7 @@
>  struct meson_mmc_platdata {
>  	struct mmc_config cfg;
>  	struct mmc mmc;
> +	int compat;
>  	void *regbase;
>  	void *w_buf;
>  };
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index b013c7c5fb..1aefe360c4 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
>  	writel(val, get_regbase(mmc) + offset);
>  }
>  
> -static void meson_mmc_config_clock(struct mmc *mmc)
> +static void meson_mmc_config_clock(struct mmc *mmc,
> +				   struct meson_mmc_platdata *pdata)
>  {
>  	uint32_t meson_mmc_clk = 0;
>  	unsigned int clk, clk_src, clk_div;
> @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  	/* RX clock phase 0:180 */
>  	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>  
> -#ifdef CONFIG_MESON_GX
> -	/* clk always on */
> -	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> -#endif
> -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> -	/* clk always on */
> -	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> -#endif
> +	switch (pdata->compat) {
> +	case MMC_COMPATIBLE_GXBB:
> +	case MMC_COMPATIBLE_GX:
> +		/* clk always on */
> +		meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +		break;
> +	case MMC_COMPATIBLE_AXG:
> +		/* clk always on */
> +		meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +		break;
> +	default:
> +		debug("no compatible supported");
> +		break;
> +	}
>  
>  	/* clock settings */
>  	meson_mmc_clk |= clk_src;
> @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  static int meson_dm_mmc_set_ios(struct udevice *dev)
>  {
>  	struct mmc *mmc = mmc_get_mmc_dev(dev);
> +	struct meson_mmc_platdata *pdata =
> +		(struct meson_mmc_platdata *)dev_get_driver_data(dev);
>  	uint32_t meson_mmc_cfg;
>  
> -	meson_mmc_config_clock(mmc);
> +	meson_mmc_config_clock(mmc, pdata);
>  
>  	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
>  
> @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
>  	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
>  }
>  
> +static const struct meson_mmc_platdata gxbb_data = {
> +        .compat = MMC_COMPATIBLE_GXBB,
> +};
> +
> +static const struct meson_mmc_platdata gx_data = {
> +        .compat = MMC_COMPATIBLE_GX,
> +};
> +
> +static const struct meson_mmc_platdata axg_data = {
> +        .compat = MMC_COMPATIBLE_AXG,
> +};
> +
>  static const struct udevice_id meson_mmc_match[] = {
> -	{ .compatible = "amlogic,meson-gx-mmc" },
> -	{ .compatible = "amlogic,meson-axg-mmc" },
> +	{ .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
> +	{ .compatible = "amlogic,meson-gx-mmc",	.data = (ulong)&gx_data },
> +	{ .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
>  	{ /* sentinel */ }
>  };
>  
> 


It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.

If you move it before, then:

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Neil

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
@ 2020-02-09 13:01     ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 13:01 UTC (permalink / raw)
  To: Anand Moon, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> Use proper compatible string as per the dts so that mmc driver
> could be tuned properly. SoC family S905, S905X have common clk
> tuning parameters setting, while AGX and G12 have common clk tuning
> parameters setting for mmc driver.
> 
> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> No changes.
> ---
>  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
>  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
>  2 files changed, 41 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index f4299485dc..83142d5d3f 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -13,6 +13,12 @@
>  #define SDIO_PORT_B			1
>  #define SDIO_PORT_C			2
>  
> +enum mmc_compatible {
> +        MMC_COMPATIBLE_GXBB,
> +        MMC_COMPATIBLE_GX,
> +        MMC_COMPATIBLE_AXG,
> +};
> +
>  #define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
>  #define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
>  
> @@ -87,6 +93,7 @@
>  struct meson_mmc_platdata {
>  	struct mmc_config cfg;
>  	struct mmc mmc;
> +	int compat;
>  	void *regbase;
>  	void *w_buf;
>  };
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index b013c7c5fb..1aefe360c4 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
>  	writel(val, get_regbase(mmc) + offset);
>  }
>  
> -static void meson_mmc_config_clock(struct mmc *mmc)
> +static void meson_mmc_config_clock(struct mmc *mmc,
> +				   struct meson_mmc_platdata *pdata)
>  {
>  	uint32_t meson_mmc_clk = 0;
>  	unsigned int clk, clk_src, clk_div;
> @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  	/* RX clock phase 0:180 */
>  	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>  
> -#ifdef CONFIG_MESON_GX
> -	/* clk always on */
> -	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> -#endif
> -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> -	/* clk always on */
> -	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> -#endif
> +	switch (pdata->compat) {
> +	case MMC_COMPATIBLE_GXBB:
> +	case MMC_COMPATIBLE_GX:
> +		/* clk always on */
> +		meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +		break;
> +	case MMC_COMPATIBLE_AXG:
> +		/* clk always on */
> +		meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +		break;
> +	default:
> +		debug("no compatible supported");
> +		break;
> +	}
>  
>  	/* clock settings */
>  	meson_mmc_clk |= clk_src;
> @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  static int meson_dm_mmc_set_ios(struct udevice *dev)
>  {
>  	struct mmc *mmc = mmc_get_mmc_dev(dev);
> +	struct meson_mmc_platdata *pdata =
> +		(struct meson_mmc_platdata *)dev_get_driver_data(dev);
>  	uint32_t meson_mmc_cfg;
>  
> -	meson_mmc_config_clock(mmc);
> +	meson_mmc_config_clock(mmc, pdata);
>  
>  	meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
>  
> @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
>  	return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
>  }
>  
> +static const struct meson_mmc_platdata gxbb_data = {
> +        .compat = MMC_COMPATIBLE_GXBB,
> +};
> +
> +static const struct meson_mmc_platdata gx_data = {
> +        .compat = MMC_COMPATIBLE_GX,
> +};
> +
> +static const struct meson_mmc_platdata axg_data = {
> +        .compat = MMC_COMPATIBLE_AXG,
> +};
> +
>  static const struct udevice_id meson_mmc_match[] = {
> -	{ .compatible = "amlogic,meson-gx-mmc" },
> -	{ .compatible = "amlogic,meson-axg-mmc" },
> +	{ .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
> +	{ .compatible = "amlogic,meson-gx-mmc",	.data = (ulong)&gx_data },
> +	{ .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
>  	{ /* sentinel */ }
>  };
>  
> 


It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.

If you move it before, then:

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Neil

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-09 11:05   ` Anand Moon
@ 2020-02-09 13:08     ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 13:08 UTC (permalink / raw)
  To: u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> As per mainline line kernel fix the clk tuning phase for mmc,
> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> As per S905, S905X, AGX and S922X datasheet set the default
> values for clk tuning.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Changes from previous
> v5  Fix the commit message, configure as per mainline kernel.
>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> 
> v4  Fix the update mask value using FIELD_PREP macro.
> 
> v3  Fix the initialization of core clk tunning phase as per datasheet.
>     Fix the commit message.
> 
> v2: Fix the clk phase macro to support PHASE_180
>     drop the wrong CLK_CORE_PHASE_MASK macro.
> 
> v1: use the mainline kernel tuning for clk tuning.
> 
> Fixed the commmit messages.
> Patch v1:
> https://patchwork.ozlabs.org/patch/1201208/
> 
> Before these changes.
>     clock is enabled (380953Hz)
>     clock is enabled (25000000Hz)
> After these changes
>     clock is enabled (380953Hz)
>     clock is enabled (25000000Hz)
>     clock is enabled (52000000Hz)
> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> ---
>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>  2 files changed, 38 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..f4299485dc 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
>  #define __SD_EMMC_H__
>  
>  #include <mmc.h>
> +#include <linux/bitops.h>
>  
>  #define SDIO_PORT_A			0
>  #define SDIO_PORT_B			1
> @@ -19,15 +20,20 @@
>  #define   CLK_MAX_DIV			63
>  #define   CLK_SRC_24M			(0 << 6)
>  #define   CLK_SRC_DIV2			(1 << 6)
> -#define   CLK_CO_PHASE_000		(0 << 8)
> -#define   CLK_CO_PHASE_090		(1 << 8)
> -#define   CLK_CO_PHASE_180		(2 << 8)
> -#define   CLK_CO_PHASE_270		(3 << 8)
> -#define   CLK_TX_PHASE_000		(0 << 10)
> -#define   CLK_TX_PHASE_090		(1 << 10)
> -#define   CLK_TX_PHASE_180		(2 << 10)
> -#define   CLK_TX_PHASE_270		(3 << 10)
> -#define   CLK_ALWAYS_ON			BIT(24)
> +
> +#define   CRYSTAL_24MHZ			0
> +#define   CLK_PHASE_0			0
> +#define   CLK_PHASE_180			2
> +
> +#define   CLK_DIV_MASK			GENMASK(5, 0)
> +#define   CLK_SRC_MASK			GENMASK(7, 6)
> +#define   CLK_CORE_PHASE_MASK		GENMASK(9, 8)
> +#define   CLK_TX_PHASE_MASK		GENMASK(11, 10)
> +#define   CLK_RX_PHASE_MASK		GENMASK(13, 12)
> +
> +#define   CLK_V2_ALWAYS_ON		BIT(24)
> +
> +#define   CLK_V3_ALWAYS_ON		BIT(28)
>  
>  #define MESON_SD_EMMC_CFG		0x44
>  #define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..b013c7c5fb 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -16,6 +16,10 @@
>  #include <asm/arch/sd_emmc.h>
>  #include <linux/log2.h>
>  
> +#include <linux/bitops.h>
> +#include <linux/compat.h>
> +#include <linux/bitfield.h>
> +
>  static inline void *get_regbase(const struct mmc *mmc)
>  {
>  	struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  	}
>  	clk_div = DIV_ROUND_UP(clk, mmc->clock);
>  
> -	/* 180 phase core clock */
> -	meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> -	/* 180 phase tx clock */
> -	meson_mmc_clk |= CLK_TX_PHASE_000;
> +	/* Clock divider */
> +	meson_mmc_clk |= CLK_DIV_MASK;

This will set the max divider, whatever the value of clk_div, so the following statement:
meson_mmc_clk |= clk_div;
will have no effect.


> +	/* Clock source : Crystal 24MHz */
> +	meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);

You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
meson_mmc_clk |= clk_src;

In conclusion your change forces the 24MHz crystal and max divider whatever the
freq asked by the mmc core !

> +	/* Core clock phase 2:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> +	/* TX clock phase 0:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> +	/* RX clock phase 0:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);

These are ok, but it's exactly the same as before with a different style.

> +
> +#ifdef CONFIG_MESON_GX
> +	/* clk always on */
> +	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +#endif
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> +	/* clk always on */
> +	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +#endif

Why not, not sure about the effect.

>  
>  	/* clock settings */
>  	meson_mmc_clk |= clk_src;
> 

Neil

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-09 13:08     ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-09 13:08 UTC (permalink / raw)
  To: Anand Moon, Jerome Brunet, Peng Fan, Jaehoon Chung,
	u-boot-amlogic, u-boot

Hi,

Le 09/02/2020 à 12:05, Anand Moon a écrit :
> As per mainline line kernel fix the clk tuning phase for mmc,
> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> As per S905, S905X, AGX and S922X datasheet set the default
> values for clk tuning.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Changes from previous
> v5  Fix the commit message, configure as per mainline kernel.
>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> 
> v4  Fix the update mask value using FIELD_PREP macro.
> 
> v3  Fix the initialization of core clk tunning phase as per datasheet.
>     Fix the commit message.
> 
> v2: Fix the clk phase macro to support PHASE_180
>     drop the wrong CLK_CORE_PHASE_MASK macro.
> 
> v1: use the mainline kernel tuning for clk tuning.
> 
> Fixed the commmit messages.
> Patch v1:
> https://patchwork.ozlabs.org/patch/1201208/
> 
> Before these changes.
>     clock is enabled (380953Hz)
>     clock is enabled (25000000Hz)
> After these changes
>     clock is enabled (380953Hz)
>     clock is enabled (25000000Hz)
>     clock is enabled (52000000Hz)
> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> ---
>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>  2 files changed, 38 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..f4299485dc 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
>  #define __SD_EMMC_H__
>  
>  #include <mmc.h>
> +#include <linux/bitops.h>
>  
>  #define SDIO_PORT_A			0
>  #define SDIO_PORT_B			1
> @@ -19,15 +20,20 @@
>  #define   CLK_MAX_DIV			63
>  #define   CLK_SRC_24M			(0 << 6)
>  #define   CLK_SRC_DIV2			(1 << 6)
> -#define   CLK_CO_PHASE_000		(0 << 8)
> -#define   CLK_CO_PHASE_090		(1 << 8)
> -#define   CLK_CO_PHASE_180		(2 << 8)
> -#define   CLK_CO_PHASE_270		(3 << 8)
> -#define   CLK_TX_PHASE_000		(0 << 10)
> -#define   CLK_TX_PHASE_090		(1 << 10)
> -#define   CLK_TX_PHASE_180		(2 << 10)
> -#define   CLK_TX_PHASE_270		(3 << 10)
> -#define   CLK_ALWAYS_ON			BIT(24)
> +
> +#define   CRYSTAL_24MHZ			0
> +#define   CLK_PHASE_0			0
> +#define   CLK_PHASE_180			2
> +
> +#define   CLK_DIV_MASK			GENMASK(5, 0)
> +#define   CLK_SRC_MASK			GENMASK(7, 6)
> +#define   CLK_CORE_PHASE_MASK		GENMASK(9, 8)
> +#define   CLK_TX_PHASE_MASK		GENMASK(11, 10)
> +#define   CLK_RX_PHASE_MASK		GENMASK(13, 12)
> +
> +#define   CLK_V2_ALWAYS_ON		BIT(24)
> +
> +#define   CLK_V3_ALWAYS_ON		BIT(28)
>  
>  #define MESON_SD_EMMC_CFG		0x44
>  #define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..b013c7c5fb 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -16,6 +16,10 @@
>  #include <asm/arch/sd_emmc.h>
>  #include <linux/log2.h>
>  
> +#include <linux/bitops.h>
> +#include <linux/compat.h>
> +#include <linux/bitfield.h>
> +
>  static inline void *get_regbase(const struct mmc *mmc)
>  {
>  	struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>  	}
>  	clk_div = DIV_ROUND_UP(clk, mmc->clock);
>  
> -	/* 180 phase core clock */
> -	meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> -	/* 180 phase tx clock */
> -	meson_mmc_clk |= CLK_TX_PHASE_000;
> +	/* Clock divider */
> +	meson_mmc_clk |= CLK_DIV_MASK;

This will set the max divider, whatever the value of clk_div, so the following statement:
meson_mmc_clk |= clk_div;
will have no effect.


> +	/* Clock source : Crystal 24MHz */
> +	meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);

You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
meson_mmc_clk |= clk_src;

In conclusion your change forces the 24MHz crystal and max divider whatever the
freq asked by the mmc core !

> +	/* Core clock phase 2:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> +	/* TX clock phase 0:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> +	/* RX clock phase 0:180 */
> +	meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);

These are ok, but it's exactly the same as before with a different style.

> +
> +#ifdef CONFIG_MESON_GX
> +	/* clk always on */
> +	meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +#endif
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> +	/* clk always on */
> +	meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +#endif

Why not, not sure about the effect.

>  
>  	/* clock settings */
>  	meson_mmc_clk |= clk_src;
> 

Neil

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-09 13:08     ` Neil Armstrong
@ 2020-02-09 17:22       ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:22 UTC (permalink / raw)
  To: u-boot

Hi Neil,

Thanks for you review comments.

On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > As per mainline line kernel fix the clk tuning phase for mmc,
> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> > As per S905, S905X, AGX and S922X datasheet set the default
> > values for clk tuning.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > Changes from previous
> > v5  Fix the commit message, configure as per mainline kernel.
> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >
> > v4  Fix the update mask value using FIELD_PREP macro.
> >
> > v3  Fix the initialization of core clk tunning phase as per datasheet.
> >     Fix the commit message.
> >
> > v2: Fix the clk phase macro to support PHASE_180
> >     drop the wrong CLK_CORE_PHASE_MASK macro.
> >
> > v1: use the mainline kernel tuning for clk tuning.
> >
> > Fixed the commmit messages.
> > Patch v1:
> > https://patchwork.ozlabs.org/patch/1201208/
> >
> > Before these changes.
> >     clock is enabled (380953Hz)
> >     clock is enabled (25000000Hz)
> > After these changes
> >     clock is enabled (380953Hz)
> >     clock is enabled (25000000Hz)
> >     clock is enabled (52000000Hz)
> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> > ---
> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >  2 files changed, 38 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..f4299485dc 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> >  #define __SD_EMMC_H__
> >
> >  #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> >  #define SDIO_PORT_A                  0
> >  #define SDIO_PORT_B                  1
> > @@ -19,15 +20,20 @@
> >  #define   CLK_MAX_DIV                        63
> >  #define   CLK_SRC_24M                        (0 << 6)
> >  #define   CLK_SRC_DIV2                       (1 << 6)
> > -#define   CLK_CO_PHASE_000           (0 << 8)
> > -#define   CLK_CO_PHASE_090           (1 << 8)
> > -#define   CLK_CO_PHASE_180           (2 << 8)
> > -#define   CLK_CO_PHASE_270           (3 << 8)
> > -#define   CLK_TX_PHASE_000           (0 << 10)
> > -#define   CLK_TX_PHASE_090           (1 << 10)
> > -#define   CLK_TX_PHASE_180           (2 << 10)
> > -#define   CLK_TX_PHASE_270           (3 << 10)
> > -#define   CLK_ALWAYS_ON                      BIT(24)
> > +
> > +#define   CRYSTAL_24MHZ                      0
> > +#define   CLK_PHASE_0                        0
> > +#define   CLK_PHASE_180                      2
> > +
> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> > +
> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
> > +
> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >
> >  #define MESON_SD_EMMC_CFG            0x44
> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..b013c7c5fb 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -16,6 +16,10 @@
> >  #include <asm/arch/sd_emmc.h>
> >  #include <linux/log2.h>
> >
> > +#include <linux/bitops.h>
> > +#include <linux/compat.h>
> > +#include <linux/bitfield.h>
> > +
> >  static inline void *get_regbase(const struct mmc *mmc)
> >  {
> >       struct meson_mmc_platdata *pdata = mmc->priv;
> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >       }
> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > -     /* 180 phase core clock */
> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > -     /* 180 phase tx clock */
> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
> > +     /* Clock divider */
> > +     meson_mmc_clk |= CLK_DIV_MASK;
>
> This will set the max divider, whatever the value of clk_div, so the following statement:
> meson_mmc_clk |= clk_div;
> will have no effect.

As per the datasheet S905 and S922X max divider is 63.
CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
                                        Frequency = clock source/cfg_div
                                        Clock off: cfg_div==0, the
clock is disabled
                                        Divider bypass: cfg_div==1,
clock source is used as core clock without divider
                                        Maximum divider 63

So here is the log of clk_div and clk_freq at my end.

MMC Device 0 not found
no mmc device at slot 0
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
Card did not respond to voltage select!
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
clock is enabled (25000000Hz)
......clk_div : 40
......clk_div : 40
clock is enabled (52000000Hz)
......clk_div : 20
switch to partitions #0, OK
mmc2(part 0) is current device
Scanning mmc 2:1...
Found U-Boot script /boot/boot.scr

>
>
> > +     /* Clock source : Crystal 24MHz */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>
> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> meson_mmc_clk |= clk_src;
>
> In conclusion your change forces the 24MHz crystal and max divider whatever the
> freq asked by the mmc core !
>
As per the datasheet S905 and S922X
Cfg_src:             Clock source
                          0: Crystal 24MHz or other frequencies
selected by clock reset test control register.
                          1: Fix PLL, 1000MHz
                          Recommended value: 1

Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
some how break the clk_freq tuning setting in my testing,
see the logs below.

MMC Device 0 not found
no mmc device at slot 0
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
Card did not respond to voltage select!
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
starting USB...

No emmc will get discovered,
*This is the real issue I faced for failure of eMMC not getting detected.*

> > +     /* Core clock phase 2:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> > +     /* TX clock phase 0:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> > +     /* RX clock phase 0:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>
> These are ok, but it's exactly the same as before with a different style.
>
> > +
> > +#ifdef CONFIG_MESON_GX
> > +     /* clk always on */
> > +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +#endif
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > +     /* clk always on */
> > +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +#endif
>
> Why not, not sure about the effect.

Ok, I will changes these to  FIELD_PREP for consultancy.

>
> >
> >       /* clock settings */
> >       meson_mmc_clk |= clk_src;
> >
>
> Neil

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-09 17:22       ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:22 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Neil,

Thanks for you review comments.

On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > As per mainline line kernel fix the clk tuning phase for mmc,
> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> > As per S905, S905X, AGX and S922X datasheet set the default
> > values for clk tuning.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > Changes from previous
> > v5  Fix the commit message, configure as per mainline kernel.
> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >
> > v4  Fix the update mask value using FIELD_PREP macro.
> >
> > v3  Fix the initialization of core clk tunning phase as per datasheet.
> >     Fix the commit message.
> >
> > v2: Fix the clk phase macro to support PHASE_180
> >     drop the wrong CLK_CORE_PHASE_MASK macro.
> >
> > v1: use the mainline kernel tuning for clk tuning.
> >
> > Fixed the commmit messages.
> > Patch v1:
> > https://patchwork.ozlabs.org/patch/1201208/
> >
> > Before these changes.
> >     clock is enabled (380953Hz)
> >     clock is enabled (25000000Hz)
> > After these changes
> >     clock is enabled (380953Hz)
> >     clock is enabled (25000000Hz)
> >     clock is enabled (52000000Hz)
> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> > ---
> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >  2 files changed, 38 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..f4299485dc 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> >  #define __SD_EMMC_H__
> >
> >  #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> >  #define SDIO_PORT_A                  0
> >  #define SDIO_PORT_B                  1
> > @@ -19,15 +20,20 @@
> >  #define   CLK_MAX_DIV                        63
> >  #define   CLK_SRC_24M                        (0 << 6)
> >  #define   CLK_SRC_DIV2                       (1 << 6)
> > -#define   CLK_CO_PHASE_000           (0 << 8)
> > -#define   CLK_CO_PHASE_090           (1 << 8)
> > -#define   CLK_CO_PHASE_180           (2 << 8)
> > -#define   CLK_CO_PHASE_270           (3 << 8)
> > -#define   CLK_TX_PHASE_000           (0 << 10)
> > -#define   CLK_TX_PHASE_090           (1 << 10)
> > -#define   CLK_TX_PHASE_180           (2 << 10)
> > -#define   CLK_TX_PHASE_270           (3 << 10)
> > -#define   CLK_ALWAYS_ON                      BIT(24)
> > +
> > +#define   CRYSTAL_24MHZ                      0
> > +#define   CLK_PHASE_0                        0
> > +#define   CLK_PHASE_180                      2
> > +
> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> > +
> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
> > +
> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >
> >  #define MESON_SD_EMMC_CFG            0x44
> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..b013c7c5fb 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -16,6 +16,10 @@
> >  #include <asm/arch/sd_emmc.h>
> >  #include <linux/log2.h>
> >
> > +#include <linux/bitops.h>
> > +#include <linux/compat.h>
> > +#include <linux/bitfield.h>
> > +
> >  static inline void *get_regbase(const struct mmc *mmc)
> >  {
> >       struct meson_mmc_platdata *pdata = mmc->priv;
> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >       }
> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > -     /* 180 phase core clock */
> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > -     /* 180 phase tx clock */
> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
> > +     /* Clock divider */
> > +     meson_mmc_clk |= CLK_DIV_MASK;
>
> This will set the max divider, whatever the value of clk_div, so the following statement:
> meson_mmc_clk |= clk_div;
> will have no effect.

As per the datasheet S905 and S922X max divider is 63.
CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
                                        Frequency = clock source/cfg_div
                                        Clock off: cfg_div==0, the
clock is disabled
                                        Divider bypass: cfg_div==1,
clock source is used as core clock without divider
                                        Maximum divider 63

So here is the log of clk_div and clk_freq at my end.

MMC Device 0 not found
no mmc device at slot 0
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
Card did not respond to voltage select!
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
clock is enabled (25000000Hz)
......clk_div : 40
......clk_div : 40
clock is enabled (52000000Hz)
......clk_div : 20
switch to partitions #0, OK
mmc2(part 0) is current device
Scanning mmc 2:1...
Found U-Boot script /boot/boot.scr

>
>
> > +     /* Clock source : Crystal 24MHz */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>
> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> meson_mmc_clk |= clk_src;
>
> In conclusion your change forces the 24MHz crystal and max divider whatever the
> freq asked by the mmc core !
>
As per the datasheet S905 and S922X
Cfg_src:             Clock source
                          0: Crystal 24MHz or other frequencies
selected by clock reset test control register.
                          1: Fix PLL, 1000MHz
                          Recommended value: 1

Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
some how break the clk_freq tuning setting in my testing,
see the logs below.

MMC Device 0 not found
no mmc device at slot 0
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
Card did not respond to voltage select!
clock is disabled (0Hz)
clock is enabled (380953Hz)
......clk_div : 63
starting USB...

No emmc will get discovered,
*This is the real issue I faced for failure of eMMC not getting detected.*

> > +     /* Core clock phase 2:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> > +     /* TX clock phase 0:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> > +     /* RX clock phase 0:180 */
> > +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>
> These are ok, but it's exactly the same as before with a different style.
>
> > +
> > +#ifdef CONFIG_MESON_GX
> > +     /* clk always on */
> > +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +#endif
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > +     /* clk always on */
> > +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +#endif
>
> Why not, not sure about the effect.

Ok, I will changes these to  FIELD_PREP for consultancy.

>
> >
> >       /* clock settings */
> >       meson_mmc_clk |= clk_src;
> >
>
> Neil

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
  2020-02-09 13:01     ` Neil Armstrong
@ 2020-02-09 17:23       ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:23 UTC (permalink / raw)
  To: u-boot

Hi Neil

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:31, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Use proper compatible string as per the dts so that mmc driver
> > could be tuned properly. SoC family S905, S905X have common clk
> > tuning parameters setting, while AGX and G12 have common clk tuning
> > parameters setting for mmc driver.
> >
> > Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > No changes.
> > ---
> >  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
> >  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
> >  2 files changed, 41 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index f4299485dc..83142d5d3f 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -13,6 +13,12 @@
> >  #define SDIO_PORT_B                  1
> >  #define SDIO_PORT_C                  2
> >
> > +enum mmc_compatible {
> > +        MMC_COMPATIBLE_GXBB,
> > +        MMC_COMPATIBLE_GX,
> > +        MMC_COMPATIBLE_AXG,
> > +};
> > +
> >  #define SD_EMMC_CLKSRC_24M           24000000        /* 24 MHz */
> >  #define SD_EMMC_CLKSRC_DIV2          1000000000      /* 1 GHz */
> >
> > @@ -87,6 +93,7 @@
> >  struct meson_mmc_platdata {
> >       struct mmc_config cfg;
> >       struct mmc mmc;
> > +     int compat;
> >       void *regbase;
> >       void *w_buf;
> >  };
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index b013c7c5fb..1aefe360c4 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
> >       writel(val, get_regbase(mmc) + offset);
> >  }
> >
> > -static void meson_mmc_config_clock(struct mmc *mmc)
> > +static void meson_mmc_config_clock(struct mmc *mmc,
> > +                                struct meson_mmc_platdata *pdata)
> >  {
> >       uint32_t meson_mmc_clk = 0;
> >       unsigned int clk, clk_src, clk_div;
> > @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >       /* RX clock phase 0:180 */
> >       meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >
> > -#ifdef CONFIG_MESON_GX
> > -     /* clk always on */
> > -     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > -#endif
> > -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > -     /* clk always on */
> > -     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > -#endif
> > +     switch (pdata->compat) {
> > +     case MMC_COMPATIBLE_GXBB:
> > +     case MMC_COMPATIBLE_GX:
> > +             /* clk always on */
> > +             meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +             break;
> > +     case MMC_COMPATIBLE_AXG:
> > +             /* clk always on */
> > +             meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +             break;
> > +     default:
> > +             debug("no compatible supported");
> > +             break;
> > +     }
> >
> >       /* clock settings */
> >       meson_mmc_clk |= clk_src;
> > @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >  static int meson_dm_mmc_set_ios(struct udevice *dev)
> >  {
> >       struct mmc *mmc = mmc_get_mmc_dev(dev);
> > +     struct meson_mmc_platdata *pdata =
> > +             (struct meson_mmc_platdata *)dev_get_driver_data(dev);
> >       uint32_t meson_mmc_cfg;
> >
> > -     meson_mmc_config_clock(mmc);
> > +     meson_mmc_config_clock(mmc, pdata);
> >
> >       meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
> >
> > @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
> >       return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
> >  }
> >
> > +static const struct meson_mmc_platdata gxbb_data = {
> > +        .compat = MMC_COMPATIBLE_GXBB,
> > +};
> > +
> > +static const struct meson_mmc_platdata gx_data = {
> > +        .compat = MMC_COMPATIBLE_GX,
> > +};
> > +
> > +static const struct meson_mmc_platdata axg_data = {
> > +        .compat = MMC_COMPATIBLE_AXG,
> > +};
> > +
> >  static const struct udevice_id meson_mmc_match[] = {
> > -     { .compatible = "amlogic,meson-gx-mmc" },
> > -     { .compatible = "amlogic,meson-axg-mmc" },
> > +     { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
> > +     { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
> > +     { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
> >       { /* sentinel */ }
> >  };
> >
> >
>
>
> It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.
>

Only GXBB and GLX have  CLK_ALWAYS_ON(24) bit set
and AXG and G12X  have CLK_ALWAYS_ON(28) bit set
for clk enable rest of the configuration is all most common for all the SoC.
let keep this simple as of now.


> If you move it before, then:
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Neil

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
@ 2020-02-09 17:23       ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:23 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Neil

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:31, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Use proper compatible string as per the dts so that mmc driver
> > could be tuned properly. SoC family S905, S905X have common clk
> > tuning parameters setting, while AGX and G12 have common clk tuning
> > parameters setting for mmc driver.
> >
> > Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > No changes.
> > ---
> >  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
> >  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
> >  2 files changed, 41 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index f4299485dc..83142d5d3f 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -13,6 +13,12 @@
> >  #define SDIO_PORT_B                  1
> >  #define SDIO_PORT_C                  2
> >
> > +enum mmc_compatible {
> > +        MMC_COMPATIBLE_GXBB,
> > +        MMC_COMPATIBLE_GX,
> > +        MMC_COMPATIBLE_AXG,
> > +};
> > +
> >  #define SD_EMMC_CLKSRC_24M           24000000        /* 24 MHz */
> >  #define SD_EMMC_CLKSRC_DIV2          1000000000      /* 1 GHz */
> >
> > @@ -87,6 +93,7 @@
> >  struct meson_mmc_platdata {
> >       struct mmc_config cfg;
> >       struct mmc mmc;
> > +     int compat;
> >       void *regbase;
> >       void *w_buf;
> >  };
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index b013c7c5fb..1aefe360c4 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
> >       writel(val, get_regbase(mmc) + offset);
> >  }
> >
> > -static void meson_mmc_config_clock(struct mmc *mmc)
> > +static void meson_mmc_config_clock(struct mmc *mmc,
> > +                                struct meson_mmc_platdata *pdata)
> >  {
> >       uint32_t meson_mmc_clk = 0;
> >       unsigned int clk, clk_src, clk_div;
> > @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >       /* RX clock phase 0:180 */
> >       meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >
> > -#ifdef CONFIG_MESON_GX
> > -     /* clk always on */
> > -     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > -#endif
> > -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > -     /* clk always on */
> > -     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > -#endif
> > +     switch (pdata->compat) {
> > +     case MMC_COMPATIBLE_GXBB:
> > +     case MMC_COMPATIBLE_GX:
> > +             /* clk always on */
> > +             meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +             break;
> > +     case MMC_COMPATIBLE_AXG:
> > +             /* clk always on */
> > +             meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +             break;
> > +     default:
> > +             debug("no compatible supported");
> > +             break;
> > +     }
> >
> >       /* clock settings */
> >       meson_mmc_clk |= clk_src;
> > @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >  static int meson_dm_mmc_set_ios(struct udevice *dev)
> >  {
> >       struct mmc *mmc = mmc_get_mmc_dev(dev);
> > +     struct meson_mmc_platdata *pdata =
> > +             (struct meson_mmc_platdata *)dev_get_driver_data(dev);
> >       uint32_t meson_mmc_cfg;
> >
> > -     meson_mmc_config_clock(mmc);
> > +     meson_mmc_config_clock(mmc, pdata);
> >
> >       meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
> >
> > @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
> >       return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
> >  }
> >
> > +static const struct meson_mmc_platdata gxbb_data = {
> > +        .compat = MMC_COMPATIBLE_GXBB,
> > +};
> > +
> > +static const struct meson_mmc_platdata gx_data = {
> > +        .compat = MMC_COMPATIBLE_GX,
> > +};
> > +
> > +static const struct meson_mmc_platdata axg_data = {
> > +        .compat = MMC_COMPATIBLE_AXG,
> > +};
> > +
> >  static const struct udevice_id meson_mmc_match[] = {
> > -     { .compatible = "amlogic,meson-gx-mmc" },
> > -     { .compatible = "amlogic,meson-axg-mmc" },
> > +     { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
> > +     { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
> > +     { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
> >       { /* sentinel */ }
> >  };
> >
> >
>
>
> It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.
>

Only GXBB and GLX have  CLK_ALWAYS_ON(24) bit set
and AXG and G12X  have CLK_ALWAYS_ON(28) bit set
for clk enable rest of the configuration is all most common for all the SoC.
let keep this simple as of now.


> If you move it before, then:
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Neil

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
  2020-02-09 12:58     ` Neil Armstrong
@ 2020-02-09 17:24       ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:24 UTC (permalink / raw)
  To: u-boot

hi Neil,

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:29, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
>
> Same as patch 4.
>
> Neil
>

$ git grep meson-axg-s400-u-boot.dtsi
it not show any thing, looks like it's not getting included.
so  I will update this in next version.

-Anand
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > no changes from previous changes
> > ---
> >  arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
> >  arch/arm/dts/meson-axg-s400.dts         |  9 ---------
> >  2 files changed, 16 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > index c46eb3f38d..74241e9fcd 100644
> > --- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > @@ -2,6 +2,22 @@
> >  /*
> >   * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
> >   */
> > +/ {
> > +     soc {
> > +             u-boot,dm-pre-reloc;
> > +     };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             serial1 = &uart_A;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +};
> >
> >  /* wifi module */
> >  &sd_emmc_b {
> > diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
> > index 18778ada7b..feb84255ad 100644
> > --- a/arch/arm/dts/meson-axg-s400.dts
> > +++ b/arch/arm/dts/meson-axg-s400.dts
> > @@ -55,11 +55,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -     };
> > -
> >       linein: audio-codec at 0 {
> >               #sound-dai-cells = <0>;
> >               compatible = "everest,es7241";
> > @@ -100,10 +95,6 @@
> >               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> >       };
> >
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 17:24       ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:24 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

hi Neil,

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:29, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
>
> Same as patch 4.
>
> Neil
>

$ git grep meson-axg-s400-u-boot.dtsi
it not show any thing, looks like it's not getting included.
so  I will update this in next version.

-Anand
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > no changes from previous changes
> > ---
> >  arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
> >  arch/arm/dts/meson-axg-s400.dts         |  9 ---------
> >  2 files changed, 16 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > index c46eb3f38d..74241e9fcd 100644
> > --- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> > @@ -2,6 +2,22 @@
> >  /*
> >   * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
> >   */
> > +/ {
> > +     soc {
> > +             u-boot,dm-pre-reloc;
> > +     };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             serial1 = &uart_A;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +};
> >
> >  /* wifi module */
> >  &sd_emmc_b {
> > diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
> > index 18778ada7b..feb84255ad 100644
> > --- a/arch/arm/dts/meson-axg-s400.dts
> > +++ b/arch/arm/dts/meson-axg-s400.dts
> > @@ -55,11 +55,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -     };
> > -
> >       linein: audio-codec@0 {
> >               #sound-dai-cells = <0>;
> >               compatible = "everest,es7241";
> > @@ -100,10 +95,6 @@
> >               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> >       };
> >
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
  2020-02-09 12:58     ` Neil Armstrong
@ 2020-02-09 17:25       ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:25 UTC (permalink / raw)
  To: u-boot

Hi Neil,

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-g12-common-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
> Same as patch 4.
>
> Neil
>

$ git grep meson-g12-common-u-boot.dtsi
arch/arm/dts/meson-g12a-sei510-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-g12a-u200-u-boot.dtsi:#include "meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-g12b-odroid-n2-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-sm1-sei610-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"

So all the common nodes is included in *meson-g12-common-u-boot.dtsi*
for G12 dts.

-Anand

> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > No changes from previous patch
> > ---
> >  arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
> >  arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
> >  arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
> >  arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
> >  arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
> >  arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
> >  6 files changed, 12 insertions(+), 45 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > index 38fd3d3feb..347b8ded22 100644
> > --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > @@ -8,6 +8,18 @@
> >       soc {
> >               u-boot,dm-pre-reloc;
> >       };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             ethernet0 = &ethmac;
> > +             mmc0 = &sd_emmc_a;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> >  };
> >
> >  &canvas {
> > diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
> > index c7a8736885..c6a48ebbe5 100644
> > --- a/arch/arm/dts/meson-g12a-sei510.dts
> > +++ b/arch/arm/dts/meson-g12a-sei510.dts
> > @@ -28,11 +28,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> >       mono_dac: audio-codec-0 {
> >               compatible = "maxim,max98357a";
> >               #sound-dai-cells = <0>;
> > @@ -49,10 +44,6 @@
> >               sound-name-prefix = "MIC";
> >       };
> >
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
> > index 8551fbd4a4..8be7b6985b 100644
> > --- a/arch/arm/dts/meson-g12a-u200.dts
> > +++ b/arch/arm/dts/meson-g12a-u200.dts
> > @@ -13,15 +13,6 @@
> >       compatible = "amlogic,u200", "amlogic,g12a";
> >       model = "Amlogic Meson G12A U200 Development Board";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
> > index 42f1540575..a37f66a5e0 100644
> > --- a/arch/arm/dts/meson-g12b-odroid-n2.dts
> > +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
> > @@ -15,15 +15,6 @@
> >       compatible = "hardkernel,odroid-n2", "amlogic,g12b";
> >       model = "Hardkernel ODROID-N2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> > diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
> > index 8647da7d66..c6b0ce9a88 100644
> > --- a/arch/arm/dts/meson-khadas-vim3.dtsi
> > +++ b/arch/arm/dts/meson-khadas-vim3.dtsi
> > @@ -11,15 +11,6 @@
> >  / {
> >       model = "Khadas VIM3";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
> > index 3435aaa4e8..4372708811 100644
> > --- a/arch/arm/dts/meson-sm1-sei610.dts
> > +++ b/arch/arm/dts/meson-sm1-sei610.dts
> > @@ -14,15 +14,6 @@
> >       compatible = "seirobotics,sei610", "amlogic,sm1";
> >       model = "SEI Robotics SEI610";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       emmc_pwrseq: emmc-pwrseq {
> >               compatible = "mmc-pwrseq-emmc";
> >               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 17:25       ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:25 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Neil,

Thanks for your review comments.

On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-g12-common-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
> Same as patch 4.
>
> Neil
>

$ git grep meson-g12-common-u-boot.dtsi
arch/arm/dts/meson-g12a-sei510-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-g12a-u200-u-boot.dtsi:#include "meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-g12b-odroid-n2-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"
arch/arm/dts/meson-sm1-sei610-u-boot.dtsi:#include
"meson-g12-common-u-boot.dtsi"

So all the common nodes is included in *meson-g12-common-u-boot.dtsi*
for G12 dts.

-Anand

> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > No changes from previous patch
> > ---
> >  arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
> >  arch/arm/dts/meson-g12a-sei510.dts        |  9 ---------
> >  arch/arm/dts/meson-g12a-u200.dts          |  9 ---------
> >  arch/arm/dts/meson-g12b-odroid-n2.dts     |  9 ---------
> >  arch/arm/dts/meson-khadas-vim3.dtsi       |  9 ---------
> >  arch/arm/dts/meson-sm1-sei610.dts         |  9 ---------
> >  6 files changed, 12 insertions(+), 45 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > index 38fd3d3feb..347b8ded22 100644
> > --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
> > @@ -8,6 +8,18 @@
> >       soc {
> >               u-boot,dm-pre-reloc;
> >       };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             ethernet0 = &ethmac;
> > +             mmc0 = &sd_emmc_a;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> >  };
> >
> >  &canvas {
> > diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
> > index c7a8736885..c6a48ebbe5 100644
> > --- a/arch/arm/dts/meson-g12a-sei510.dts
> > +++ b/arch/arm/dts/meson-g12a-sei510.dts
> > @@ -28,11 +28,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> >       mono_dac: audio-codec-0 {
> >               compatible = "maxim,max98357a";
> >               #sound-dai-cells = <0>;
> > @@ -49,10 +44,6 @@
> >               sound-name-prefix = "MIC";
> >       };
> >
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
> > index 8551fbd4a4..8be7b6985b 100644
> > --- a/arch/arm/dts/meson-g12a-u200.dts
> > +++ b/arch/arm/dts/meson-g12a-u200.dts
> > @@ -13,15 +13,6 @@
> >       compatible = "amlogic,u200", "amlogic,g12a";
> >       model = "Amlogic Meson G12A U200 Development Board";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
> > index 42f1540575..a37f66a5e0 100644
> > --- a/arch/arm/dts/meson-g12b-odroid-n2.dts
> > +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
> > @@ -15,15 +15,6 @@
> >       compatible = "hardkernel,odroid-n2", "amlogic,g12b";
> >       model = "Hardkernel ODROID-N2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> > diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
> > index 8647da7d66..c6b0ce9a88 100644
> > --- a/arch/arm/dts/meson-khadas-vim3.dtsi
> > +++ b/arch/arm/dts/meson-khadas-vim3.dtsi
> > @@ -11,15 +11,6 @@
> >  / {
> >       model = "Khadas VIM3";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
> > index 3435aaa4e8..4372708811 100644
> > --- a/arch/arm/dts/meson-sm1-sei610.dts
> > +++ b/arch/arm/dts/meson-sm1-sei610.dts
> > @@ -14,15 +14,6 @@
> >       compatible = "seirobotics,sei610", "amlogic,sm1";
> >       model = "SEI Robotics SEI610";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       emmc_pwrseq: emmc-pwrseq {
> >               compatible = "mmc-pwrseq-emmc";
> >               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
  2020-02-09 12:58     ` Neil Armstrong
@ 2020-02-09 17:25       ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:25 UTC (permalink / raw)
  To: u-boot

Hi Neil,

Thanks for your review.

On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-gx-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
> The mmc aliases are u-boot specific, so only those should be
> moved into the meson-gx-u-boot.dtsi.
>
> Please keep the other aliases in the their linux sync'ed files.
>
> Neil
>

meson-gx-u-boot.dtsi is included in following dts file so
their is no another common -u-boot.dtsi for all the SBC dts.

$ git grep meson-gx-u-boot.dtsi
arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-p200-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-p201-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi:#include
"meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi:#include
"meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"

So all the common nodes is included in *meson-gx-u-boot.dtsi* for GXBB
and GXL dts.



-Anand

> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > no changes from previous
> > ---
> >  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
> >  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
> >  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
> >  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
> >  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
> >  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
> >  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
> >  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
> >  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
> >  9 files changed, 15 insertions(+), 71 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
> > index b84e5edba4..13be3a7b8f 100644
> > --- a/arch/arm/dts/meson-gx-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
> > @@ -8,6 +8,21 @@
> >       soc {
> >               u-boot,dm-pre-reloc;
> >       };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             serial1 = &uart_A;
> > +             serial2 = &uart_AO_B;
> > +             ethernet0 = &ethmac;
> > +             spi0 = &spifc;
> > +             mmc0 = &sd_emmc_a;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> >  };
> >
> >  &vpu {
> > diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > index cbe99bd4e0..11690d6c46 100644
> > --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > @@ -11,15 +11,6 @@
> >  / {
> >       compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
> > index 54954b314a..f8cd76a2ef 100644
> > --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> > +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> > @@ -14,15 +14,6 @@
> >       compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
> >       model = "Hardkernel ODROID-C2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
> > index 0be0f2a5d2..c9822e50f9 100644
> > --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
> > +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
> > @@ -8,15 +8,6 @@
> >  #include "meson-gxbb.dtsi"
> >
> >  / {
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> > diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > index 82b1c48511..4f9072a83e 100644
> > --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > @@ -16,16 +16,6 @@
> >                    "amlogic,meson-gxl";
> >       model = "Libre Computer Board AML-S805X-AC";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -             spi0 = &spifc;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               /*
> >                * The pads are present but no connector is soldered on
> > diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > index ceb34afe42..072e4575d2 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > @@ -26,11 +26,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial2 = &uart_AO_B;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> >       gpio-keys-polled {
> >               compatible = "gpio-keys-polled";
> >               #address-cells = <1>;
> > diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > index a23252efc6..8d3965ab42 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > @@ -15,15 +15,6 @@
> >       compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
> >       model = "Libre Computer Board AML-S905X-CC";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > index a1b31013ab..70f437fc3a 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > @@ -13,16 +13,6 @@
> >  #include "meson-gxl-s905x.dtsi"
> >
> >  / {
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > index 782e9edac8..4e68e289d3 100644
> > --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > @@ -16,16 +16,6 @@
> >       compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
> >       model = "Khadas VIM2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -             serial2 = &uart_AO_B;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory at 0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
@ 2020-02-09 17:25       ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-09 17:25 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Neil,

Thanks for your review.

On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> > Move u-boot specific common nodes in the dts files to
> > meson-gx-u-boot.dtsi. This allows us to keep the basic
> > dts[i] files up-to-date with the ones in kernel,
> > but at the same time allowing the u-boot to add its own
> > properties to the existing nodes.
> > Also add missing mmc alias to dts nodes to avoid
> > below debug warning.
> >
> > mmc_bind: alias ret=-2, devnum=-1
> > mmc_bind: alias ret=-2, devnum=-1
>
> The mmc aliases are u-boot specific, so only those should be
> moved into the meson-gx-u-boot.dtsi.
>
> Please keep the other aliases in the their linux sync'ed files.
>
> Neil
>

meson-gx-u-boot.dtsi is included in following dts file so
their is no another common -u-boot.dtsi for all the SBC dts.

$ git grep meson-gx-u-boot.dtsi
arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-p200-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxbb-p201-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi:#include
"meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi:#include
"meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"

So all the common nodes is included in *meson-gx-u-boot.dtsi* for GXBB
and GXL dts.



-Anand

> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > no changes from previous
> > ---
> >  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
> >  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
> >  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
> >  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
> >  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
> >  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
> >  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
> >  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
> >  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
> >  9 files changed, 15 insertions(+), 71 deletions(-)
> >
> > diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
> > index b84e5edba4..13be3a7b8f 100644
> > --- a/arch/arm/dts/meson-gx-u-boot.dtsi
> > +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
> > @@ -8,6 +8,21 @@
> >       soc {
> >               u-boot,dm-pre-reloc;
> >       };
> > +
> > +     aliases {
> > +             serial0 = &uart_AO;
> > +             serial1 = &uart_A;
> > +             serial2 = &uart_AO_B;
> > +             ethernet0 = &ethmac;
> > +             spi0 = &spifc;
> > +             mmc0 = &sd_emmc_a;
> > +             mmc1 = &sd_emmc_b;
> > +             mmc2 = &sd_emmc_c;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> >  };
> >
> >  &vpu {
> > diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > index cbe99bd4e0..11690d6c46 100644
> > --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> > @@ -11,15 +11,6 @@
> >  / {
> >       compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
> > index 54954b314a..f8cd76a2ef 100644
> > --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> > +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> > @@ -14,15 +14,6 @@
> >       compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
> >       model = "Hardkernel ODROID-C2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
> > index 0be0f2a5d2..c9822e50f9 100644
> > --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
> > +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
> > @@ -8,15 +8,6 @@
> >  #include "meson-gxbb.dtsi"
> >
> >  / {
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x40000000>;
> > diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > index 82b1c48511..4f9072a83e 100644
> > --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
> > @@ -16,16 +16,6 @@
> >                    "amlogic,meson-gxl";
> >       model = "Libre Computer Board AML-S805X-AC";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -             spi0 = &spifc;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               /*
> >                * The pads are present but no connector is soldered on
> > diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > index ceb34afe42..072e4575d2 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
> > @@ -26,11 +26,6 @@
> >               };
> >       };
> >
> > -     aliases {
> > -             serial2 = &uart_AO_B;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> >       gpio-keys-polled {
> >               compatible = "gpio-keys-polled";
> >               #address-cells = <1>;
> > diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > index a23252efc6..8d3965ab42 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
> > @@ -15,15 +15,6 @@
> >       compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
> >       model = "Libre Computer Board AML-S905X-CC";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       cvbs-connector {
> >               compatible = "composite-video-connector";
> >
> > diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > index a1b31013ab..70f437fc3a 100644
> > --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
> > @@ -13,16 +13,6 @@
> >  #include "meson-gxl-s905x.dtsi"
> >
> >  / {
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -             ethernet0 = &ethmac;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> > diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > index 782e9edac8..4e68e289d3 100644
> > --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> > @@ -16,16 +16,6 @@
> >       compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
> >       model = "Khadas VIM2";
> >
> > -     aliases {
> > -             serial0 = &uart_AO;
> > -             serial1 = &uart_A;
> > -             serial2 = &uart_AO_B;
> > -     };
> > -
> > -     chosen {
> > -             stdout-path = "serial0:115200n8";
> > -     };
> > -
> >       memory@0 {
> >               device_type = "memory";
> >               reg = <0x0 0x0 0x0 0x80000000>;
> >

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
  2020-02-09 17:25       ` Anand Moon
@ 2020-02-10  8:24         ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  8:24 UTC (permalink / raw)
  To: u-boot

On 09/02/2020 18:25, Anand Moon wrote:
> Hi Neil,
> 
> Thanks for your review.
> 
> On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> Move u-boot specific common nodes in the dts files to
>>> meson-gx-u-boot.dtsi. This allows us to keep the basic
>>> dts[i] files up-to-date with the ones in kernel,
>>> but at the same time allowing the u-boot to add its own
>>> properties to the existing nodes.
>>> Also add missing mmc alias to dts nodes to avoid
>>> below debug warning.
>>>
>>> mmc_bind: alias ret=-2, devnum=-1
>>> mmc_bind: alias ret=-2, devnum=-1
>>
>> The mmc aliases are u-boot specific, so only those should be
>> moved into the meson-gx-u-boot.dtsi.
>>
>> Please keep the other aliases in the their linux sync'ed files.
>>
>> Neil
>>
> 
> meson-gx-u-boot.dtsi is included in following dts file so
> their is no another common -u-boot.dtsi for all the SBC dts.
> 
> $ git grep meson-gx-u-boot.dtsi
> arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-p200-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-p201-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi:#include
> "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi:#include
> "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> 
> So all the common nodes is included in *meson-gx-u-boot.dtsi* for GXBB
> and GXL dts.

It's not the point.

The goal is to keep the dts and dtsi files untouched to be able to sync them
from linux easily.

So :
- all general changes/fixes must go through linux, and temporary in the -u-boot.dtsi
- all u-boot specific in the -u-boot.dtsi

If you have an issue with the aliases, please discuss it on the linux-amlogic ML, but
the linux policy is to only declare the needed aliases in the boards dts and avoid having
a bunch of aliases in the dtsi files.

Neil

> 
> 
> 
> -Anand
> 
>>>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> no changes from previous
>>> ---
>>>  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
>>>  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
>>>  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
>>>  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
>>>  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
>>>  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
>>>  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
>>>  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
>>>  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
>>>  9 files changed, 15 insertions(+), 71 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
>>> index b84e5edba4..13be3a7b8f 100644
>>> --- a/arch/arm/dts/meson-gx-u-boot.dtsi
>>> +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
>>> @@ -8,6 +8,21 @@
>>>       soc {
>>>               u-boot,dm-pre-reloc;
>>>       };
>>> +
>>> +     aliases {
>>> +             serial0 = &uart_AO;
>>> +             serial1 = &uart_A;
>>> +             serial2 = &uart_AO_B;
>>> +             ethernet0 = &ethmac;
>>> +             spi0 = &spifc;
>>> +             mmc0 = &sd_emmc_a;
>>> +             mmc1 = &sd_emmc_b;
>>> +             mmc2 = &sd_emmc_c;
>>> +     };
>>> +
>>> +     chosen {
>>> +             stdout-path = "serial0:115200n8";
>>> +     };
>>>  };
>>>
>>>  &vpu {
>>> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> index cbe99bd4e0..11690d6c46 100644
>>> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> @@ -11,15 +11,6 @@
>>>  / {
>>>       compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory at 0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> index 54954b314a..f8cd76a2ef 100644
>>> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> @@ -14,15 +14,6 @@
>>>       compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
>>>       model = "Hardkernel ODROID-C2";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory at 0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> index 0be0f2a5d2..c9822e50f9 100644
>>> --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> @@ -8,15 +8,6 @@
>>>  #include "meson-gxbb.dtsi"
>>>
>>>  / {
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory at 0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x40000000>;
>>> diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> index 82b1c48511..4f9072a83e 100644
>>> --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> @@ -16,16 +16,6 @@
>>>                    "amlogic,meson-gxl";
>>>       model = "Libre Computer Board AML-S805X-AC";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -             spi0 = &spifc;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       cvbs-connector {
>>>               /*
>>>                * The pads are present but no connector is soldered on
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> index ceb34afe42..072e4575d2 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> @@ -26,11 +26,6 @@
>>>               };
>>>       };
>>>
>>> -     aliases {
>>> -             serial2 = &uart_AO_B;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>>       gpio-keys-polled {
>>>               compatible = "gpio-keys-polled";
>>>               #address-cells = <1>;
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> index a23252efc6..8d3965ab42 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> @@ -15,15 +15,6 @@
>>>       compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
>>>       model = "Libre Computer Board AML-S905X-CC";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       cvbs-connector {
>>>               compatible = "composite-video-connector";
>>>
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> index a1b31013ab..70f437fc3a 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> @@ -13,16 +13,6 @@
>>>  #include "meson-gxl-s905x.dtsi"
>>>
>>>  / {
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             serial1 = &uart_A;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory at 0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> index 782e9edac8..4e68e289d3 100644
>>> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> @@ -16,16 +16,6 @@
>>>       compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
>>>       model = "Khadas VIM2";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             serial1 = &uart_A;
>>> -             serial2 = &uart_AO_B;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory at 0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>>

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
@ 2020-02-10  8:24         ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  8:24 UTC (permalink / raw)
  To: Anand Moon
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

On 09/02/2020 18:25, Anand Moon wrote:
> Hi Neil,
> 
> Thanks for your review.
> 
> On Sun, 9 Feb 2020 at 18:28, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> Move u-boot specific common nodes in the dts files to
>>> meson-gx-u-boot.dtsi. This allows us to keep the basic
>>> dts[i] files up-to-date with the ones in kernel,
>>> but at the same time allowing the u-boot to add its own
>>> properties to the existing nodes.
>>> Also add missing mmc alias to dts nodes to avoid
>>> below debug warning.
>>>
>>> mmc_bind: alias ret=-2, devnum=-1
>>> mmc_bind: alias ret=-2, devnum=-1
>>
>> The mmc aliases are u-boot specific, so only those should be
>> moved into the meson-gx-u-boot.dtsi.
>>
>> Please keep the other aliases in the their linux sync'ed files.
>>
>> Neil
>>
> 
> meson-gx-u-boot.dtsi is included in following dts file so
> their is no another common -u-boot.dtsi for all the SBC dts.
> 
> $ git grep meson-gx-u-boot.dtsi
> arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-p200-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxbb-p201-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi:#include
> "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi:#include
> "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi:#include "meson-gx-u-boot.dtsi"
> 
> So all the common nodes is included in *meson-gx-u-boot.dtsi* for GXBB
> and GXL dts.

It's not the point.

The goal is to keep the dts and dtsi files untouched to be able to sync them
from linux easily.

So :
- all general changes/fixes must go through linux, and temporary in the -u-boot.dtsi
- all u-boot specific in the -u-boot.dtsi

If you have an issue with the aliases, please discuss it on the linux-amlogic ML, but
the linux policy is to only declare the needed aliases in the boards dts and avoid having
a bunch of aliases in the dtsi files.

Neil

> 
> 
> 
> -Anand
> 
>>>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> no changes from previous
>>> ---
>>>  arch/arm/dts/meson-gx-u-boot.dtsi             | 15 +++++++++++++++
>>>  arch/arm/dts/meson-gxbb-nanopi-k2.dts         |  9 ---------
>>>  arch/arm/dts/meson-gxbb-odroidc2.dts          |  9 ---------
>>>  arch/arm/dts/meson-gxbb-p20x.dtsi             |  9 ---------
>>>  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
>>>  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  5 -----
>>>  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  9 ---------
>>>  arch/arm/dts/meson-gxl-s905x-p212.dtsi        | 10 ----------
>>>  arch/arm/dts/meson-gxm-khadas-vim2.dts        | 10 ----------
>>>  9 files changed, 15 insertions(+), 71 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
>>> index b84e5edba4..13be3a7b8f 100644
>>> --- a/arch/arm/dts/meson-gx-u-boot.dtsi
>>> +++ b/arch/arm/dts/meson-gx-u-boot.dtsi
>>> @@ -8,6 +8,21 @@
>>>       soc {
>>>               u-boot,dm-pre-reloc;
>>>       };
>>> +
>>> +     aliases {
>>> +             serial0 = &uart_AO;
>>> +             serial1 = &uart_A;
>>> +             serial2 = &uart_AO_B;
>>> +             ethernet0 = &ethmac;
>>> +             spi0 = &spifc;
>>> +             mmc0 = &sd_emmc_a;
>>> +             mmc1 = &sd_emmc_b;
>>> +             mmc2 = &sd_emmc_c;
>>> +     };
>>> +
>>> +     chosen {
>>> +             stdout-path = "serial0:115200n8";
>>> +     };
>>>  };
>>>
>>>  &vpu {
>>> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> index cbe99bd4e0..11690d6c46 100644
>>> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> @@ -11,15 +11,6 @@
>>>  / {
>>>       compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory@0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> index 54954b314a..f8cd76a2ef 100644
>>> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> @@ -14,15 +14,6 @@
>>>       compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
>>>       model = "Hardkernel ODROID-C2";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory@0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> index 0be0f2a5d2..c9822e50f9 100644
>>> --- a/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
>>> @@ -8,15 +8,6 @@
>>>  #include "meson-gxbb.dtsi"
>>>
>>>  / {
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory@0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x40000000>;
>>> diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> index 82b1c48511..4f9072a83e 100644
>>> --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
>>> @@ -16,16 +16,6 @@
>>>                    "amlogic,meson-gxl";
>>>       model = "Libre Computer Board AML-S805X-AC";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -             spi0 = &spifc;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       cvbs-connector {
>>>               /*
>>>                * The pads are present but no connector is soldered on
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> index ceb34afe42..072e4575d2 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
>>> @@ -26,11 +26,6 @@
>>>               };
>>>       };
>>>
>>> -     aliases {
>>> -             serial2 = &uart_AO_B;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>>       gpio-keys-polled {
>>>               compatible = "gpio-keys-polled";
>>>               #address-cells = <1>;
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> index a23252efc6..8d3965ab42 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
>>> @@ -15,15 +15,6 @@
>>>       compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
>>>       model = "Libre Computer Board AML-S905X-CC";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       cvbs-connector {
>>>               compatible = "composite-video-connector";
>>>
>>> diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> index a1b31013ab..70f437fc3a 100644
>>> --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
>>> @@ -13,16 +13,6 @@
>>>  #include "meson-gxl-s905x.dtsi"
>>>
>>>  / {
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             serial1 = &uart_A;
>>> -             ethernet0 = &ethmac;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory@0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> index 782e9edac8..4e68e289d3 100644
>>> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> @@ -16,16 +16,6 @@
>>>       compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
>>>       model = "Khadas VIM2";
>>>
>>> -     aliases {
>>> -             serial0 = &uart_AO;
>>> -             serial1 = &uart_A;
>>> -             serial2 = &uart_AO_B;
>>> -     };
>>> -
>>> -     chosen {
>>> -             stdout-path = "serial0:115200n8";
>>> -     };
>>> -
>>>       memory@0 {
>>>               device_type = "memory";
>>>               reg = <0x0 0x0 0x0 0x80000000>;
>>>


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
  2020-02-09 17:23       ` Anand Moon
@ 2020-02-10  8:26         ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  8:26 UTC (permalink / raw)
  To: u-boot

On 09/02/2020 18:23, Anand Moon wrote:
> Hi Neil
> 
> Thanks for your review comments.
> 
> On Sun, 9 Feb 2020 at 18:31, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> Use proper compatible string as per the dts so that mmc driver
>>> could be tuned properly. SoC family S905, S905X have common clk
>>> tuning parameters setting, while AGX and G12 have common clk tuning
>>> parameters setting for mmc driver.
>>>
>>> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> No changes.
>>> ---
>>>  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
>>>  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
>>>  2 files changed, 41 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> index f4299485dc..83142d5d3f 100644
>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> @@ -13,6 +13,12 @@
>>>  #define SDIO_PORT_B                  1
>>>  #define SDIO_PORT_C                  2
>>>
>>> +enum mmc_compatible {
>>> +        MMC_COMPATIBLE_GXBB,
>>> +        MMC_COMPATIBLE_GX,
>>> +        MMC_COMPATIBLE_AXG,
>>> +};
>>> +
>>>  #define SD_EMMC_CLKSRC_24M           24000000        /* 24 MHz */
>>>  #define SD_EMMC_CLKSRC_DIV2          1000000000      /* 1 GHz */
>>>
>>> @@ -87,6 +93,7 @@
>>>  struct meson_mmc_platdata {
>>>       struct mmc_config cfg;
>>>       struct mmc mmc;
>>> +     int compat;
>>>       void *regbase;
>>>       void *w_buf;
>>>  };
>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>> index b013c7c5fb..1aefe360c4 100644
>>> --- a/drivers/mmc/meson_gx_mmc.c
>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>> @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
>>>       writel(val, get_regbase(mmc) + offset);
>>>  }
>>>
>>> -static void meson_mmc_config_clock(struct mmc *mmc)
>>> +static void meson_mmc_config_clock(struct mmc *mmc,
>>> +                                struct meson_mmc_platdata *pdata)
>>>  {
>>>       uint32_t meson_mmc_clk = 0;
>>>       unsigned int clk, clk_src, clk_div;
>>> @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>       /* RX clock phase 0:180 */
>>>       meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>>
>>> -#ifdef CONFIG_MESON_GX
>>> -     /* clk always on */
>>> -     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> -#endif
>>> -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>>> -     /* clk always on */
>>> -     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> -#endif
>>> +     switch (pdata->compat) {
>>> +     case MMC_COMPATIBLE_GXBB:
>>> +     case MMC_COMPATIBLE_GX:
>>> +             /* clk always on */
>>> +             meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> +             break;
>>> +     case MMC_COMPATIBLE_AXG:
>>> +             /* clk always on */
>>> +             meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> +             break;
>>> +     default:
>>> +             debug("no compatible supported");
>>> +             break;
>>> +     }
>>>
>>>       /* clock settings */
>>>       meson_mmc_clk |= clk_src;
>>> @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>  static int meson_dm_mmc_set_ios(struct udevice *dev)
>>>  {
>>>       struct mmc *mmc = mmc_get_mmc_dev(dev);
>>> +     struct meson_mmc_platdata *pdata =
>>> +             (struct meson_mmc_platdata *)dev_get_driver_data(dev);
>>>       uint32_t meson_mmc_cfg;
>>>
>>> -     meson_mmc_config_clock(mmc);
>>> +     meson_mmc_config_clock(mmc, pdata);
>>>
>>>       meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
>>>
>>> @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
>>>       return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
>>>  }
>>>
>>> +static const struct meson_mmc_platdata gxbb_data = {
>>> +        .compat = MMC_COMPATIBLE_GXBB,
>>> +};
>>> +
>>> +static const struct meson_mmc_platdata gx_data = {
>>> +        .compat = MMC_COMPATIBLE_GX,
>>> +};
>>> +
>>> +static const struct meson_mmc_platdata axg_data = {
>>> +        .compat = MMC_COMPATIBLE_AXG,
>>> +};
>>> +a in 
>>>  static const struct udevice_id meson_mmc_match[] = {
>>> -     { .compatible = "amlogic,meson-gx-mmc" },
>>> -     { .compatible = "amlogic,meson-axg-mmc" },
>>> +     { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
>>> +     { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
>>> +     { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
>>>       { /* sentinel */ }
>>>  };
>>>
>>>
>>
>>
>> It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.
>>
> 
> Only GXBB and GLX have  CLK_ALWAYS_ON(24) bit set
> and AXG and G12X  have CLK_ALWAYS_ON(28) bit set
> for clk enable rest of the configuration is all most common for all the SoC.
> let keep this simple as of now.

It's not the point, just add the "struct meson_mmc_platdata" and .data in meson_mmc_match
_before_ patch 1, to avoid adding hideous #ifdef/#elif/#endif in the meantime.

Neil


> 
> 
>> If you move it before, then:
>>
>> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> Neil
> 
> -Anand
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts
@ 2020-02-10  8:26         ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  8:26 UTC (permalink / raw)
  To: Anand Moon
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

On 09/02/2020 18:23, Anand Moon wrote:
> Hi Neil
> 
> Thanks for your review comments.
> 
> On Sun, 9 Feb 2020 at 18:31, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> Use proper compatible string as per the dts so that mmc driver
>>> could be tuned properly. SoC family S905, S905X have common clk
>>> tuning parameters setting, while AGX and G12 have common clk tuning
>>> parameters setting for mmc driver.
>>>
>>> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> No changes.
>>> ---
>>>  arch/arm/include/asm/arch-meson/sd_emmc.h |  7 ++++
>>>  drivers/mmc/meson_gx_mmc.c                | 46 +++++++++++++++++------
>>>  2 files changed, 41 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> index f4299485dc..83142d5d3f 100644
>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> @@ -13,6 +13,12 @@
>>>  #define SDIO_PORT_B                  1
>>>  #define SDIO_PORT_C                  2
>>>
>>> +enum mmc_compatible {
>>> +        MMC_COMPATIBLE_GXBB,
>>> +        MMC_COMPATIBLE_GX,
>>> +        MMC_COMPATIBLE_AXG,
>>> +};
>>> +
>>>  #define SD_EMMC_CLKSRC_24M           24000000        /* 24 MHz */
>>>  #define SD_EMMC_CLKSRC_DIV2          1000000000      /* 1 GHz */
>>>
>>> @@ -87,6 +93,7 @@
>>>  struct meson_mmc_platdata {
>>>       struct mmc_config cfg;
>>>       struct mmc mmc;
>>> +     int compat;
>>>       void *regbase;
>>>       void *w_buf;
>>>  };
>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>> index b013c7c5fb..1aefe360c4 100644
>>> --- a/drivers/mmc/meson_gx_mmc.c
>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>> @@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
>>>       writel(val, get_regbase(mmc) + offset);
>>>  }
>>>
>>> -static void meson_mmc_config_clock(struct mmc *mmc)
>>> +static void meson_mmc_config_clock(struct mmc *mmc,
>>> +                                struct meson_mmc_platdata *pdata)
>>>  {
>>>       uint32_t meson_mmc_clk = 0;
>>>       unsigned int clk, clk_src, clk_div;
>>> @@ -66,14 +67,20 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>       /* RX clock phase 0:180 */
>>>       meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>>
>>> -#ifdef CONFIG_MESON_GX
>>> -     /* clk always on */
>>> -     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> -#endif
>>> -#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>>> -     /* clk always on */
>>> -     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> -#endif
>>> +     switch (pdata->compat) {
>>> +     case MMC_COMPATIBLE_GXBB:
>>> +     case MMC_COMPATIBLE_GX:
>>> +             /* clk always on */
>>> +             meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> +             break;
>>> +     case MMC_COMPATIBLE_AXG:
>>> +             /* clk always on */
>>> +             meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> +             break;
>>> +     default:
>>> +             debug("no compatible supported");
>>> +             break;
>>> +     }
>>>
>>>       /* clock settings */
>>>       meson_mmc_clk |= clk_src;
>>> @@ -85,9 +92,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>  static int meson_dm_mmc_set_ios(struct udevice *dev)
>>>  {
>>>       struct mmc *mmc = mmc_get_mmc_dev(dev);
>>> +     struct meson_mmc_platdata *pdata =
>>> +             (struct meson_mmc_platdata *)dev_get_driver_data(dev);
>>>       uint32_t meson_mmc_cfg;
>>>
>>> -     meson_mmc_config_clock(mmc);
>>> +     meson_mmc_config_clock(mmc, pdata);
>>>
>>>       meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
>>>
>>> @@ -324,9 +333,22 @@ int meson_mmc_bind(struct udevice *dev)
>>>       return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
>>>  }
>>>
>>> +static const struct meson_mmc_platdata gxbb_data = {
>>> +        .compat = MMC_COMPATIBLE_GXBB,
>>> +};
>>> +
>>> +static const struct meson_mmc_platdata gx_data = {
>>> +        .compat = MMC_COMPATIBLE_GX,
>>> +};
>>> +
>>> +static const struct meson_mmc_platdata axg_data = {
>>> +        .compat = MMC_COMPATIBLE_AXG,
>>> +};
>>> +a in 
>>>  static const struct udevice_id meson_mmc_match[] = {
>>> -     { .compatible = "amlogic,meson-gx-mmc" },
>>> -     { .compatible = "amlogic,meson-axg-mmc" },
>>> +     { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
>>> +     { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
>>> +     { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
>>>       { /* sentinel */ }
>>>  };
>>>
>>>
>>
>>
>> It's fine but you should do that before patch 1, and introduce the clk setup directly with the MMC_COMPATIBLE_*.
>>
> 
> Only GXBB and GLX have  CLK_ALWAYS_ON(24) bit set
> and AXG and G12X  have CLK_ALWAYS_ON(28) bit set
> for clk enable rest of the configuration is all most common for all the SoC.
> let keep this simple as of now.

It's not the point, just add the "struct meson_mmc_platdata" and .data in meson_mmc_match
_before_ patch 1, to avoid adding hideous #ifdef/#elif/#endif in the meantime.

Neil


> 
> 
>> If you move it before, then:
>>
>> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> Neil
> 
> -Anand
> 


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-09 17:22       ` Anand Moon
@ 2020-02-10  9:03         ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  9:03 UTC (permalink / raw)
  To: u-boot

On 09/02/2020 18:22, Anand Moon wrote:
> Hi Neil,
> 
> Thanks for you review comments.
> 
> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> As per mainline line kernel fix the clk tuning phase for mmc,
>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>>> As per S905, S905X, AGX and S922X datasheet set the default
>>> values for clk tuning.
>>>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> Changes from previous
>>> v5  Fix the commit message, configure as per mainline kernel.
>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>>>
>>> v4  Fix the update mask value using FIELD_PREP macro.
>>>
>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
>>>     Fix the commit message.
>>>
>>> v2: Fix the clk phase macro to support PHASE_180
>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
>>>
>>> v1: use the mainline kernel tuning for clk tuning.
>>>
>>> Fixed the commmit messages.
>>> Patch v1:
>>> https://patchwork.ozlabs.org/patch/1201208/
>>>
>>> Before these changes.
>>>     clock is enabled (380953Hz)
>>>     clock is enabled (25000000Hz)
>>> After these changes
>>>     clock is enabled (380953Hz)
>>>     clock is enabled (25000000Hz)
>>>     clock is enabled (52000000Hz)
>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>>> ---
>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>>>  2 files changed, 38 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> index e3a72c8b66..f4299485dc 100644
>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> @@ -7,6 +7,7 @@
>>>  #define __SD_EMMC_H__
>>>
>>>  #include <mmc.h>
>>> +#include <linux/bitops.h>
>>>
>>>  #define SDIO_PORT_A                  0
>>>  #define SDIO_PORT_B                  1
>>> @@ -19,15 +20,20 @@
>>>  #define   CLK_MAX_DIV                        63
>>>  #define   CLK_SRC_24M                        (0 << 6)
>>>  #define   CLK_SRC_DIV2                       (1 << 6)
>>> -#define   CLK_CO_PHASE_000           (0 << 8)
>>> -#define   CLK_CO_PHASE_090           (1 << 8)
>>> -#define   CLK_CO_PHASE_180           (2 << 8)
>>> -#define   CLK_CO_PHASE_270           (3 << 8)
>>> -#define   CLK_TX_PHASE_000           (0 << 10)
>>> -#define   CLK_TX_PHASE_090           (1 << 10)
>>> -#define   CLK_TX_PHASE_180           (2 << 10)
>>> -#define   CLK_TX_PHASE_270           (3 << 10)
>>> -#define   CLK_ALWAYS_ON                      BIT(24)
>>> +
>>> +#define   CRYSTAL_24MHZ                      0
>>> +#define   CLK_PHASE_0                        0
>>> +#define   CLK_PHASE_180                      2
>>> +
>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>>> +
>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
>>> +
>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
>>>
>>>  #define MESON_SD_EMMC_CFG            0x44
>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>> index 86c1a7164a..b013c7c5fb 100644
>>> --- a/drivers/mmc/meson_gx_mmc.c
>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>> @@ -16,6 +16,10 @@
>>>  #include <asm/arch/sd_emmc.h>
>>>  #include <linux/log2.h>
>>>
>>> +#include <linux/bitops.h>
>>> +#include <linux/compat.h>
>>> +#include <linux/bitfield.h>
>>> +
>>>  static inline void *get_regbase(const struct mmc *mmc)
>>>  {
>>>       struct meson_mmc_platdata *pdata = mmc->priv;
>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>       }
>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>>>
>>> -     /* 180 phase core clock */
>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
>>> -
>>> -     /* 180 phase tx clock */
>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
>>> +     /* Clock divider */
>>> +     meson_mmc_clk |= CLK_DIV_MASK;
>>
>> This will set the max divider, whatever the value of clk_div, so the following statement:
>> meson_mmc_clk |= clk_div;
>> will have no effect.
> 
> As per the datasheet S905 and S922X max divider is 63.
> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>                                         Frequency = clock source/cfg_div
>                                         Clock off: cfg_div==0, the
> clock is disabled
>                                         Divider bypass: cfg_div==1,
> clock source is used as core clock without divider
>                                         Maximum divider 63
> 
> So here is the log of clk_div and clk_freq at my end.
> 
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> clock is enabled (25000000Hz)
> ......clk_div : 40
> ......clk_div : 40
> clock is enabled (52000000Hz)
> ......clk_div : 20
> switch to partitions #0, OK
> mmc2(part 0) is current device
> Scanning mmc 2:1...
> Found U-Boot script /boot/boot.scr


OK, seems you didn't see the issue.

With the original code, let's say mmc->clock = 25000000

clk = SD_EMMC_CLKSRC_DIV2
clk_src = CLK_SRC_DIV2
clk_div = 40

meson_mmc_clk |= CLK_CO_PHASE_180;
meson_mmc_clk |= CLK_TX_PHASE_000;
meson_mmc_clk |= CLK_SRC_DIV2;
meson_mmc_clk |= 40;

=> meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
=> meson_mmc_clk = 0x268

With your code :
meson_mmc_clk |= CLK_DIV_MASK;
meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
meson_mmc_clk |= CLK_SRC_DIV2;
meson_mmc_clk |= 40;

=> meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40

-------------------/\---this---------makes-------this-----useless------------------/\

=> 0x27f

It sets the clock to 15873015Hz instead of the 25000000Hz requested.

so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.

> 
>>
>>
>>> +     /* Clock source : Crystal 24MHz */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>
>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>> meson_mmc_clk |= clk_src;
>>
>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>> freq asked by the mmc core !
>>
> As per the datasheet S905 and S922X
> Cfg_src:             Clock source
>                           0: Crystal 24MHz or other frequencies
> selected by clock reset test control register.
>                           1: Fix PLL, 1000MHz
>                           Recommended value: 1
> 
> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> some how break the clk_freq tuning setting in my testing,
> see the logs below.
> 
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> starting USB...
> 
> No emmc will get discovered,
> *This is the real issue I faced for failure of eMMC not getting detected.*

This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.

This issue is somewhere else, but I don't know where because the Linux driver behaves
correctly with the same setup.

My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.

Could you post instead :
- your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
- this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
- redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi

If you have a issue, please chat with me on #linux-amlogic on freenode.

Thanks,
Neil

> 
>>> +     /* Core clock phase 2:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>>> +     /* TX clock phase 0:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>>> +     /* RX clock phase 0:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>
>> These are ok, but it's exactly the same as before with a different style.
>>
>>> +
>>> +#ifdef CONFIG_MESON_GX
>>> +     /* clk always on */
>>> +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> +#endif
>>> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>>> +     /* clk always on */
>>> +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> +#endif
>>
>> Why not, not sure about the effect.
> 
> Ok, I will changes these to  FIELD_PREP for consultancy.

Really not sure about the effect of these, please drop these until we find out
if we really need these.

> 
>>
>>>
>>>       /* clock settings */
>>>       meson_mmc_clk |= clk_src;
>>>
>>
>> Neil
> 
> -Anand
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-10  9:03         ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-10  9:03 UTC (permalink / raw)
  To: Anand Moon
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

On 09/02/2020 18:22, Anand Moon wrote:
> Hi Neil,
> 
> Thanks for you review comments.
> 
> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>> As per mainline line kernel fix the clk tuning phase for mmc,
>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>>> As per S905, S905X, AGX and S922X datasheet set the default
>>> values for clk tuning.
>>>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>> ---
>>> Changes from previous
>>> v5  Fix the commit message, configure as per mainline kernel.
>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>>>
>>> v4  Fix the update mask value using FIELD_PREP macro.
>>>
>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
>>>     Fix the commit message.
>>>
>>> v2: Fix the clk phase macro to support PHASE_180
>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
>>>
>>> v1: use the mainline kernel tuning for clk tuning.
>>>
>>> Fixed the commmit messages.
>>> Patch v1:
>>> https://patchwork.ozlabs.org/patch/1201208/
>>>
>>> Before these changes.
>>>     clock is enabled (380953Hz)
>>>     clock is enabled (25000000Hz)
>>> After these changes
>>>     clock is enabled (380953Hz)
>>>     clock is enabled (25000000Hz)
>>>     clock is enabled (52000000Hz)
>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>>> ---
>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>>>  2 files changed, 38 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> index e3a72c8b66..f4299485dc 100644
>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>> @@ -7,6 +7,7 @@
>>>  #define __SD_EMMC_H__
>>>
>>>  #include <mmc.h>
>>> +#include <linux/bitops.h>
>>>
>>>  #define SDIO_PORT_A                  0
>>>  #define SDIO_PORT_B                  1
>>> @@ -19,15 +20,20 @@
>>>  #define   CLK_MAX_DIV                        63
>>>  #define   CLK_SRC_24M                        (0 << 6)
>>>  #define   CLK_SRC_DIV2                       (1 << 6)
>>> -#define   CLK_CO_PHASE_000           (0 << 8)
>>> -#define   CLK_CO_PHASE_090           (1 << 8)
>>> -#define   CLK_CO_PHASE_180           (2 << 8)
>>> -#define   CLK_CO_PHASE_270           (3 << 8)
>>> -#define   CLK_TX_PHASE_000           (0 << 10)
>>> -#define   CLK_TX_PHASE_090           (1 << 10)
>>> -#define   CLK_TX_PHASE_180           (2 << 10)
>>> -#define   CLK_TX_PHASE_270           (3 << 10)
>>> -#define   CLK_ALWAYS_ON                      BIT(24)
>>> +
>>> +#define   CRYSTAL_24MHZ                      0
>>> +#define   CLK_PHASE_0                        0
>>> +#define   CLK_PHASE_180                      2
>>> +
>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>>> +
>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
>>> +
>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
>>>
>>>  #define MESON_SD_EMMC_CFG            0x44
>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>> index 86c1a7164a..b013c7c5fb 100644
>>> --- a/drivers/mmc/meson_gx_mmc.c
>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>> @@ -16,6 +16,10 @@
>>>  #include <asm/arch/sd_emmc.h>
>>>  #include <linux/log2.h>
>>>
>>> +#include <linux/bitops.h>
>>> +#include <linux/compat.h>
>>> +#include <linux/bitfield.h>
>>> +
>>>  static inline void *get_regbase(const struct mmc *mmc)
>>>  {
>>>       struct meson_mmc_platdata *pdata = mmc->priv;
>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>       }
>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>>>
>>> -     /* 180 phase core clock */
>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
>>> -
>>> -     /* 180 phase tx clock */
>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
>>> +     /* Clock divider */
>>> +     meson_mmc_clk |= CLK_DIV_MASK;
>>
>> This will set the max divider, whatever the value of clk_div, so the following statement:
>> meson_mmc_clk |= clk_div;
>> will have no effect.
> 
> As per the datasheet S905 and S922X max divider is 63.
> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>                                         Frequency = clock source/cfg_div
>                                         Clock off: cfg_div==0, the
> clock is disabled
>                                         Divider bypass: cfg_div==1,
> clock source is used as core clock without divider
>                                         Maximum divider 63
> 
> So here is the log of clk_div and clk_freq at my end.
> 
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> clock is enabled (25000000Hz)
> ......clk_div : 40
> ......clk_div : 40
> clock is enabled (52000000Hz)
> ......clk_div : 20
> switch to partitions #0, OK
> mmc2(part 0) is current device
> Scanning mmc 2:1...
> Found U-Boot script /boot/boot.scr


OK, seems you didn't see the issue.

With the original code, let's say mmc->clock = 25000000

clk = SD_EMMC_CLKSRC_DIV2
clk_src = CLK_SRC_DIV2
clk_div = 40

meson_mmc_clk |= CLK_CO_PHASE_180;
meson_mmc_clk |= CLK_TX_PHASE_000;
meson_mmc_clk |= CLK_SRC_DIV2;
meson_mmc_clk |= 40;

=> meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
=> meson_mmc_clk = 0x268

With your code :
meson_mmc_clk |= CLK_DIV_MASK;
meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
meson_mmc_clk |= CLK_SRC_DIV2;
meson_mmc_clk |= 40;

=> meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40

-------------------/\---this---------makes-------this-----useless------------------/\

=> 0x27f

It sets the clock to 15873015Hz instead of the 25000000Hz requested.

so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.

> 
>>
>>
>>> +     /* Clock source : Crystal 24MHz */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>
>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>> meson_mmc_clk |= clk_src;
>>
>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>> freq asked by the mmc core !
>>
> As per the datasheet S905 and S922X
> Cfg_src:             Clock source
>                           0: Crystal 24MHz or other frequencies
> selected by clock reset test control register.
>                           1: Fix PLL, 1000MHz
>                           Recommended value: 1
> 
> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> some how break the clk_freq tuning setting in my testing,
> see the logs below.
> 
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> starting USB...
> 
> No emmc will get discovered,
> *This is the real issue I faced for failure of eMMC not getting detected.*

This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.

This issue is somewhere else, but I don't know where because the Linux driver behaves
correctly with the same setup.

My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.

Could you post instead :
- your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
- this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
- redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi

If you have a issue, please chat with me on #linux-amlogic on freenode.

Thanks,
Neil

> 
>>> +     /* Core clock phase 2:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>>> +     /* TX clock phase 0:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>>> +     /* RX clock phase 0:180 */
>>> +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>
>> These are ok, but it's exactly the same as before with a different style.
>>
>>> +
>>> +#ifdef CONFIG_MESON_GX
>>> +     /* clk always on */
>>> +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>>> +#endif
>>> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>>> +     /* clk always on */
>>> +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>>> +#endif
>>
>> Why not, not sure about the effect.
> 
> Ok, I will changes these to  FIELD_PREP for consultancy.

Really not sure about the effect of these, please drop these until we find out
if we really need these.

> 
>>
>>>
>>>       /* clock settings */
>>>       meson_mmc_clk |= clk_src;
>>>
>>
>> Neil
> 
> -Anand
> 


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-09 17:22       ` Anand Moon
@ 2020-02-10  9:35         ` Jerome Brunet
  -1 siblings, 0 replies; 48+ messages in thread
From: Jerome Brunet @ 2020-02-10  9:35 UTC (permalink / raw)
  To: u-boot


On Sun 09 Feb 2020 at 18:22, Anand Moon <linux.amoon@gmail.com> wrote:

> Hi Neil,
>
> Thanks for you review comments.
>
> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> > ---
>> > Changes from previous
>> > v5  Fix the commit message, configure as per mainline kernel.
>> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>> >
>> > v4  Fix the update mask value using FIELD_PREP macro.
>> >
>> > v3  Fix the initialization of core clk tunning phase as per datasheet.
>> >     Fix the commit message.
>> >
>> > v2: Fix the clk phase macro to support PHASE_180
>> >     drop the wrong CLK_CORE_PHASE_MASK macro.
>> >
>> > v1: use the mainline kernel tuning for clk tuning.
>> >
>> > Fixed the commmit messages.
>> > Patch v1:
>> > https://patchwork.ozlabs.org/patch/1201208/
>> >
>> > Before these changes.
>> >     clock is enabled (380953Hz)
>> >     clock is enabled (25000000Hz)
>> > After these changes
>> >     clock is enabled (380953Hz)
>> >     clock is enabled (25000000Hz)
>> >     clock is enabled (52000000Hz)
>> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>> > ---
>> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>> >  2 files changed, 38 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..f4299485dc 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> >  #define __SD_EMMC_H__
>> >
>> >  #include <mmc.h>
>> > +#include <linux/bitops.h>
>> >
>> >  #define SDIO_PORT_A                  0
>> >  #define SDIO_PORT_B                  1
>> > @@ -19,15 +20,20 @@
>> >  #define   CLK_MAX_DIV                        63
>> >  #define   CLK_SRC_24M                        (0 << 6)
>> >  #define   CLK_SRC_DIV2                       (1 << 6)
>> > -#define   CLK_CO_PHASE_000           (0 << 8)
>> > -#define   CLK_CO_PHASE_090           (1 << 8)
>> > -#define   CLK_CO_PHASE_180           (2 << 8)
>> > -#define   CLK_CO_PHASE_270           (3 << 8)
>> > -#define   CLK_TX_PHASE_000           (0 << 10)
>> > -#define   CLK_TX_PHASE_090           (1 << 10)
>> > -#define   CLK_TX_PHASE_180           (2 << 10)
>> > -#define   CLK_TX_PHASE_270           (3 << 10)
>> > -#define   CLK_ALWAYS_ON                      BIT(24)
>> > +
>> > +#define   CRYSTAL_24MHZ                      0
>> > +#define   CLK_PHASE_0                        0
>> > +#define   CLK_PHASE_180                      2
>> > +
>> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>> > +
>> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
>> > +
>> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
>> >
>> >  #define MESON_SD_EMMC_CFG            0x44
>> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..b013c7c5fb 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> >  #include <asm/arch/sd_emmc.h>
>> >  #include <linux/log2.h>
>> >
>> > +#include <linux/bitops.h>
>> > +#include <linux/compat.h>
>> > +#include <linux/bitfield.h>
>> > +
>> >  static inline void *get_regbase(const struct mmc *mmc)
>> >  {
>> >       struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> >       }
>> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > -     /* 180 phase core clock */
>> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > -     /* 180 phase tx clock */
>> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
>> > +     /* Clock divider */
>> > +     meson_mmc_clk |= CLK_DIV_MASK;
>>
>> This will set the max divider, whatever the value of clk_div, so the following statement:
>> meson_mmc_clk |= clk_div;
>> will have no effect.
>
> As per the datasheet S905 and S922X max divider is 63.
> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>                                         Frequency = clock source/cfg_div
>                                         Clock off: cfg_div==0, the
> clock is disabled
>                                         Divider bypass: cfg_div==1,
> clock source is used as core clock without divider
>                                         Maximum divider 63
>
> So here is the log of clk_div and clk_freq at my end.
>
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> clock is enabled (25000000Hz)
> ......clk_div : 40
> ......clk_div : 40
> clock is enabled (52000000Hz)
> ......clk_div : 20
> switch to partitions #0, OK
> mmc2(part 0) is current device
> Scanning mmc 2:1...
> Found U-Boot script /boot/boot.scr
>
>>
>>
>> > +     /* Clock source : Crystal 24MHz */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>
>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>> meson_mmc_clk |= clk_src;
>>
>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>> freq asked by the mmc core !
>>
> As per the datasheet S905 and S922X
> Cfg_src:             Clock source
>                           0: Crystal 24MHz or other frequencies
> selected by clock reset test control register.
>                           1: Fix PLL, 1000MHz
>                           Recommended value: 1
>
> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> some how break the clk_freq tuning setting in my testing,
> see the logs below.
>
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> starting USB...
>
> No emmc will get discovered,
> *This is the real issue I faced for failure of eMMC not getting
> detected.*

I don't think the reality of the issue reported has been questioned.
What is being questioned is the proposed solution.

The patch you sent forces clock input 0 with the maximum divider
possible. This is an important comment for which an explanation is
missing AFAICT.

1) The doc is not clear but input 0 is not always the oscillator. It is
the MMC composite clock which can set to several different sources,
especially when the ROM code boots from another device, such as SPI
This is the topic of 2 patches I sent recently (not yet merged)

2) Let's assume that input 0 is indeed 24M, your patches forces this
with a 63 divider => 380kHz. With a clock that low, the phase does not
matter much anymore

IOW, you are the only one to report this issue on one specific case, the
cause of the issue is not really identified and the work around would:
* Add statements without effect in the code
* Considerably slow down eMMC and SDCard on all amlogic platforms.
* Provide no explanation about how it actually solves something

This is problematic ...

>
>> > +     /* Core clock phase 2:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> > +     /* TX clock phase 0:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>> > +     /* RX clock phase 0:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>
>> These are ok, but it's exactly the same as before with a different style.
>>
>> > +
>> > +#ifdef CONFIG_MESON_GX
>> > +     /* clk always on */
>> > +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>> > +#endif
>> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>> > +     /* clk always on */
>> > +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>> > +#endif
>>
>> Why not, not sure about the effect.
>
> Ok, I will changes these to  FIELD_PREP for consultancy.
>
>>
>> >
>> >       /* clock settings */
>> >       meson_mmc_clk |= clk_src;
>> >
>>
>> Neil
>
> -Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-10  9:35         ` Jerome Brunet
  0 siblings, 0 replies; 48+ messages in thread
From: Jerome Brunet @ 2020-02-10  9:35 UTC (permalink / raw)
  To: Anand Moon, Neil Armstrong
  Cc: Peng Fan, Jaehoon Chung, u-boot-amlogic, U-Boot Mailing List


On Sun 09 Feb 2020 at 18:22, Anand Moon <linux.amoon@gmail.com> wrote:

> Hi Neil,
>
> Thanks for you review comments.
>
> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> > ---
>> > Changes from previous
>> > v5  Fix the commit message, configure as per mainline kernel.
>> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>> >
>> > v4  Fix the update mask value using FIELD_PREP macro.
>> >
>> > v3  Fix the initialization of core clk tunning phase as per datasheet.
>> >     Fix the commit message.
>> >
>> > v2: Fix the clk phase macro to support PHASE_180
>> >     drop the wrong CLK_CORE_PHASE_MASK macro.
>> >
>> > v1: use the mainline kernel tuning for clk tuning.
>> >
>> > Fixed the commmit messages.
>> > Patch v1:
>> > https://patchwork.ozlabs.org/patch/1201208/
>> >
>> > Before these changes.
>> >     clock is enabled (380953Hz)
>> >     clock is enabled (25000000Hz)
>> > After these changes
>> >     clock is enabled (380953Hz)
>> >     clock is enabled (25000000Hz)
>> >     clock is enabled (52000000Hz)
>> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>> > ---
>> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>> >  2 files changed, 38 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..f4299485dc 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> >  #define __SD_EMMC_H__
>> >
>> >  #include <mmc.h>
>> > +#include <linux/bitops.h>
>> >
>> >  #define SDIO_PORT_A                  0
>> >  #define SDIO_PORT_B                  1
>> > @@ -19,15 +20,20 @@
>> >  #define   CLK_MAX_DIV                        63
>> >  #define   CLK_SRC_24M                        (0 << 6)
>> >  #define   CLK_SRC_DIV2                       (1 << 6)
>> > -#define   CLK_CO_PHASE_000           (0 << 8)
>> > -#define   CLK_CO_PHASE_090           (1 << 8)
>> > -#define   CLK_CO_PHASE_180           (2 << 8)
>> > -#define   CLK_CO_PHASE_270           (3 << 8)
>> > -#define   CLK_TX_PHASE_000           (0 << 10)
>> > -#define   CLK_TX_PHASE_090           (1 << 10)
>> > -#define   CLK_TX_PHASE_180           (2 << 10)
>> > -#define   CLK_TX_PHASE_270           (3 << 10)
>> > -#define   CLK_ALWAYS_ON                      BIT(24)
>> > +
>> > +#define   CRYSTAL_24MHZ                      0
>> > +#define   CLK_PHASE_0                        0
>> > +#define   CLK_PHASE_180                      2
>> > +
>> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>> > +
>> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
>> > +
>> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
>> >
>> >  #define MESON_SD_EMMC_CFG            0x44
>> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..b013c7c5fb 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> >  #include <asm/arch/sd_emmc.h>
>> >  #include <linux/log2.h>
>> >
>> > +#include <linux/bitops.h>
>> > +#include <linux/compat.h>
>> > +#include <linux/bitfield.h>
>> > +
>> >  static inline void *get_regbase(const struct mmc *mmc)
>> >  {
>> >       struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> >       }
>> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > -     /* 180 phase core clock */
>> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > -     /* 180 phase tx clock */
>> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
>> > +     /* Clock divider */
>> > +     meson_mmc_clk |= CLK_DIV_MASK;
>>
>> This will set the max divider, whatever the value of clk_div, so the following statement:
>> meson_mmc_clk |= clk_div;
>> will have no effect.
>
> As per the datasheet S905 and S922X max divider is 63.
> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>                                         Frequency = clock source/cfg_div
>                                         Clock off: cfg_div==0, the
> clock is disabled
>                                         Divider bypass: cfg_div==1,
> clock source is used as core clock without divider
>                                         Maximum divider 63
>
> So here is the log of clk_div and clk_freq at my end.
>
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> clock is enabled (25000000Hz)
> ......clk_div : 40
> ......clk_div : 40
> clock is enabled (52000000Hz)
> ......clk_div : 20
> switch to partitions #0, OK
> mmc2(part 0) is current device
> Scanning mmc 2:1...
> Found U-Boot script /boot/boot.scr
>
>>
>>
>> > +     /* Clock source : Crystal 24MHz */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>
>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>> meson_mmc_clk |= clk_src;
>>
>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>> freq asked by the mmc core !
>>
> As per the datasheet S905 and S922X
> Cfg_src:             Clock source
>                           0: Crystal 24MHz or other frequencies
> selected by clock reset test control register.
>                           1: Fix PLL, 1000MHz
>                           Recommended value: 1
>
> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> some how break the clk_freq tuning setting in my testing,
> see the logs below.
>
> MMC Device 0 not found
> no mmc device at slot 0
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> Card did not respond to voltage select!
> clock is disabled (0Hz)
> clock is enabled (380953Hz)
> ......clk_div : 63
> starting USB...
>
> No emmc will get discovered,
> *This is the real issue I faced for failure of eMMC not getting
> detected.*

I don't think the reality of the issue reported has been questioned.
What is being questioned is the proposed solution.

The patch you sent forces clock input 0 with the maximum divider
possible. This is an important comment for which an explanation is
missing AFAICT.

1) The doc is not clear but input 0 is not always the oscillator. It is
the MMC composite clock which can set to several different sources,
especially when the ROM code boots from another device, such as SPI
This is the topic of 2 patches I sent recently (not yet merged)

2) Let's assume that input 0 is indeed 24M, your patches forces this
with a 63 divider => 380kHz. With a clock that low, the phase does not
matter much anymore

IOW, you are the only one to report this issue on one specific case, the
cause of the issue is not really identified and the work around would:
* Add statements without effect in the code
* Considerably slow down eMMC and SDCard on all amlogic platforms.
* Provide no explanation about how it actually solves something

This is problematic ...

>
>> > +     /* Core clock phase 2:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> > +     /* TX clock phase 0:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>> > +     /* RX clock phase 0:180 */
>> > +     meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>>
>> These are ok, but it's exactly the same as before with a different style.
>>
>> > +
>> > +#ifdef CONFIG_MESON_GX
>> > +     /* clk always on */
>> > +     meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>> > +#endif
>> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>> > +     /* clk always on */
>> > +     meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>> > +#endif
>>
>> Why not, not sure about the effect.
>
> Ok, I will changes these to  FIELD_PREP for consultancy.
>
>>
>> >
>> >       /* clock settings */
>> >       meson_mmc_clk |= clk_src;
>> >
>>
>> Neil
>
> -Anand


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-10  9:03         ` Neil Armstrong
@ 2020-02-13 11:58           ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 11:58 UTC (permalink / raw)
  To: u-boot

hi Niel / Jerome,

Thanks for your review comments and debug output
Sorry for late reply.

On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 09/02/2020 18:22, Anand Moon wrote:
> > Hi Neil,
> >
> > Thanks for you review comments.
> >
> > On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> Hi,
> >>
> >> Le 09/02/2020 ? 12:05, Anand Moon a ?crit :
> >>> As per mainline line kernel fix the clk tuning phase for mmc,
> >>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >>> As per S905, S905X, AGX and S922X datasheet set the default
> >>> values for clk tuning.
> >>>
> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>> ---
> >>> Changes from previous
> >>> v5  Fix the commit message, configure as per mainline kernel.
> >>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >>>
> >>> v4  Fix the update mask value using FIELD_PREP macro.
> >>>
> >>> v3  Fix the initialization of core clk tunning phase as per datasheet.
> >>>     Fix the commit message.
> >>>
> >>> v2: Fix the clk phase macro to support PHASE_180
> >>>     drop the wrong CLK_CORE_PHASE_MASK macro.
> >>>
> >>> v1: use the mainline kernel tuning for clk tuning.
> >>>
> >>> Fixed the commmit messages.
> >>> Patch v1:
> >>> https://patchwork.ozlabs.org/patch/1201208/
> >>>
> >>> Before these changes.
> >>>     clock is enabled (380953Hz)
> >>>     clock is enabled (25000000Hz)
> >>> After these changes
> >>>     clock is enabled (380953Hz)
> >>>     clock is enabled (25000000Hz)
> >>>     clock is enabled (52000000Hz)
> >>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >>> ---
> >>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >>>  2 files changed, 38 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> index e3a72c8b66..f4299485dc 100644
> >>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> @@ -7,6 +7,7 @@
> >>>  #define __SD_EMMC_H__
> >>>
> >>>  #include <mmc.h>
> >>> +#include <linux/bitops.h>
> >>>
> >>>  #define SDIO_PORT_A                  0
> >>>  #define SDIO_PORT_B                  1
> >>> @@ -19,15 +20,20 @@
> >>>  #define   CLK_MAX_DIV                        63
> >>>  #define   CLK_SRC_24M                        (0 << 6)
> >>>  #define   CLK_SRC_DIV2                       (1 << 6)
> >>> -#define   CLK_CO_PHASE_000           (0 << 8)
> >>> -#define   CLK_CO_PHASE_090           (1 << 8)
> >>> -#define   CLK_CO_PHASE_180           (2 << 8)
> >>> -#define   CLK_CO_PHASE_270           (3 << 8)
> >>> -#define   CLK_TX_PHASE_000           (0 << 10)
> >>> -#define   CLK_TX_PHASE_090           (1 << 10)
> >>> -#define   CLK_TX_PHASE_180           (2 << 10)
> >>> -#define   CLK_TX_PHASE_270           (3 << 10)
> >>> -#define   CLK_ALWAYS_ON                      BIT(24)
> >>> +
> >>> +#define   CRYSTAL_24MHZ                      0
> >>> +#define   CLK_PHASE_0                        0
> >>> +#define   CLK_PHASE_180                      2
> >>> +
> >>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >>> +
> >>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >>> +
> >>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >>>
> >>>  #define MESON_SD_EMMC_CFG            0x44
> >>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >>> index 86c1a7164a..b013c7c5fb 100644
> >>> --- a/drivers/mmc/meson_gx_mmc.c
> >>> +++ b/drivers/mmc/meson_gx_mmc.c
> >>> @@ -16,6 +16,10 @@
> >>>  #include <asm/arch/sd_emmc.h>
> >>>  #include <linux/log2.h>
> >>>
> >>> +#include <linux/bitops.h>
> >>> +#include <linux/compat.h>
> >>> +#include <linux/bitfield.h>
> >>> +
> >>>  static inline void *get_regbase(const struct mmc *mmc)
> >>>  {
> >>>       struct meson_mmc_platdata *pdata = mmc->priv;
> >>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >>>       }
> >>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >>>
> >>> -     /* 180 phase core clock */
> >>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >>> -
> >>> -     /* 180 phase tx clock */
> >>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >>> +     /* Clock divider */
> >>> +     meson_mmc_clk |= CLK_DIV_MASK;
> >>
> >> This will set the max divider, whatever the value of clk_div, so the following statement:
> >> meson_mmc_clk |= clk_div;
> >> will have no effect.
> >
> > As per the datasheet S905 and S922X max divider is 63.
> > CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >                                         Frequency = clock source/cfg_div
> >                                         Clock off: cfg_div==0, the
> > clock is disabled
> >                                         Divider bypass: cfg_div==1,
> > clock source is used as core clock without divider
> >                                         Maximum divider 63
> >
> > So here is the log of clk_div and clk_freq at my end.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > clock is enabled (25000000Hz)
> > ......clk_div : 40
> > ......clk_div : 40
> > clock is enabled (52000000Hz)
> > ......clk_div : 20
> > switch to partitions #0, OK
> > mmc2(part 0) is current device
> > Scanning mmc 2:1...
> > Found U-Boot script /boot/boot.scr
>
>
> OK, seems you didn't see the issue.
>
> With the original code, let's say mmc->clock = 25000000
>
> clk = SD_EMMC_CLKSRC_DIV2
> clk_src = CLK_SRC_DIV2
> clk_div = 40
>
> meson_mmc_clk |= CLK_CO_PHASE_180;
> meson_mmc_clk |= CLK_TX_PHASE_000;
> meson_mmc_clk |= CLK_SRC_DIV2;
> meson_mmc_clk |= 40;
>
> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
> => meson_mmc_clk = 0x268
>
> With your code :
> meson_mmc_clk |= CLK_DIV_MASK;
> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> meson_mmc_clk |= CLK_SRC_DIV2;
> meson_mmc_clk |= 40;
>
> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
>
> -------------------/\---this---------makes-------this-----useless------------------/\
>
> => 0x27f
>
> It sets the clock to 15873015Hz instead of the 25000000Hz requested.

I did not observer this at my end, but any way thanks for the input.

>
> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
>
> >
> >>
> >>
> >>> +     /* Clock source : Crystal 24MHz */
> >>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>
> >> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >> meson_mmc_clk |= clk_src;
> >>
> >> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >> freq asked by the mmc core !
> >>
> > As per the datasheet S905 and S922X
> > Cfg_src:             Clock source
> >                           0: Crystal 24MHz or other frequencies
> > selected by clock reset test control register.
> >                           1: Fix PLL, 1000MHz
> >                           Recommended value: 1
> >
> > Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> > some how break the clk_freq tuning setting in my testing,
> > see the logs below.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > starting USB...
> >
> > No emmc will get discovered,
> > *This is the real issue I faced for failure of eMMC not getting detected.*
>
> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
>
> This issue is somewhere else, but I don't know where because the Linux driver behaves
> correctly with the same setup.
>
> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.

I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
       if (mmc->clock > 400000) {
               /* Clock source : Fix PLL, 1000MHz */
               meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
       } else {
               /* Clock source : Crystal 24MHz */
               meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
       }
>
> Could you post instead :
> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1

Ok I will change the order.

> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2

I propose the dynamically select 24MHz and Fix PLL, as above code.

> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
>

Ok I will make these changes

> If you have a issue, please chat with me on #linux-amlogic on freenode.

I could not connect to freenode or register my self to this chat
group. sorry about that.

>
> Thanks,
> Neil
>

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-13 11:58           ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 11:58 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

hi Niel / Jerome,

Thanks for your review comments and debug output
Sorry for late reply.

On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 09/02/2020 18:22, Anand Moon wrote:
> > Hi Neil,
> >
> > Thanks for you review comments.
> >
> > On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> Hi,
> >>
> >> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> >>> As per mainline line kernel fix the clk tuning phase for mmc,
> >>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >>> As per S905, S905X, AGX and S922X datasheet set the default
> >>> values for clk tuning.
> >>>
> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>> ---
> >>> Changes from previous
> >>> v5  Fix the commit message, configure as per mainline kernel.
> >>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >>>
> >>> v4  Fix the update mask value using FIELD_PREP macro.
> >>>
> >>> v3  Fix the initialization of core clk tunning phase as per datasheet.
> >>>     Fix the commit message.
> >>>
> >>> v2: Fix the clk phase macro to support PHASE_180
> >>>     drop the wrong CLK_CORE_PHASE_MASK macro.
> >>>
> >>> v1: use the mainline kernel tuning for clk tuning.
> >>>
> >>> Fixed the commmit messages.
> >>> Patch v1:
> >>> https://patchwork.ozlabs.org/patch/1201208/
> >>>
> >>> Before these changes.
> >>>     clock is enabled (380953Hz)
> >>>     clock is enabled (25000000Hz)
> >>> After these changes
> >>>     clock is enabled (380953Hz)
> >>>     clock is enabled (25000000Hz)
> >>>     clock is enabled (52000000Hz)
> >>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >>> ---
> >>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >>>  2 files changed, 38 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> index e3a72c8b66..f4299485dc 100644
> >>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>> @@ -7,6 +7,7 @@
> >>>  #define __SD_EMMC_H__
> >>>
> >>>  #include <mmc.h>
> >>> +#include <linux/bitops.h>
> >>>
> >>>  #define SDIO_PORT_A                  0
> >>>  #define SDIO_PORT_B                  1
> >>> @@ -19,15 +20,20 @@
> >>>  #define   CLK_MAX_DIV                        63
> >>>  #define   CLK_SRC_24M                        (0 << 6)
> >>>  #define   CLK_SRC_DIV2                       (1 << 6)
> >>> -#define   CLK_CO_PHASE_000           (0 << 8)
> >>> -#define   CLK_CO_PHASE_090           (1 << 8)
> >>> -#define   CLK_CO_PHASE_180           (2 << 8)
> >>> -#define   CLK_CO_PHASE_270           (3 << 8)
> >>> -#define   CLK_TX_PHASE_000           (0 << 10)
> >>> -#define   CLK_TX_PHASE_090           (1 << 10)
> >>> -#define   CLK_TX_PHASE_180           (2 << 10)
> >>> -#define   CLK_TX_PHASE_270           (3 << 10)
> >>> -#define   CLK_ALWAYS_ON                      BIT(24)
> >>> +
> >>> +#define   CRYSTAL_24MHZ                      0
> >>> +#define   CLK_PHASE_0                        0
> >>> +#define   CLK_PHASE_180                      2
> >>> +
> >>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >>> +
> >>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >>> +
> >>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >>>
> >>>  #define MESON_SD_EMMC_CFG            0x44
> >>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >>> index 86c1a7164a..b013c7c5fb 100644
> >>> --- a/drivers/mmc/meson_gx_mmc.c
> >>> +++ b/drivers/mmc/meson_gx_mmc.c
> >>> @@ -16,6 +16,10 @@
> >>>  #include <asm/arch/sd_emmc.h>
> >>>  #include <linux/log2.h>
> >>>
> >>> +#include <linux/bitops.h>
> >>> +#include <linux/compat.h>
> >>> +#include <linux/bitfield.h>
> >>> +
> >>>  static inline void *get_regbase(const struct mmc *mmc)
> >>>  {
> >>>       struct meson_mmc_platdata *pdata = mmc->priv;
> >>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >>>       }
> >>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >>>
> >>> -     /* 180 phase core clock */
> >>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >>> -
> >>> -     /* 180 phase tx clock */
> >>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >>> +     /* Clock divider */
> >>> +     meson_mmc_clk |= CLK_DIV_MASK;
> >>
> >> This will set the max divider, whatever the value of clk_div, so the following statement:
> >> meson_mmc_clk |= clk_div;
> >> will have no effect.
> >
> > As per the datasheet S905 and S922X max divider is 63.
> > CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >                                         Frequency = clock source/cfg_div
> >                                         Clock off: cfg_div==0, the
> > clock is disabled
> >                                         Divider bypass: cfg_div==1,
> > clock source is used as core clock without divider
> >                                         Maximum divider 63
> >
> > So here is the log of clk_div and clk_freq at my end.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > clock is enabled (25000000Hz)
> > ......clk_div : 40
> > ......clk_div : 40
> > clock is enabled (52000000Hz)
> > ......clk_div : 20
> > switch to partitions #0, OK
> > mmc2(part 0) is current device
> > Scanning mmc 2:1...
> > Found U-Boot script /boot/boot.scr
>
>
> OK, seems you didn't see the issue.
>
> With the original code, let's say mmc->clock = 25000000
>
> clk = SD_EMMC_CLKSRC_DIV2
> clk_src = CLK_SRC_DIV2
> clk_div = 40
>
> meson_mmc_clk |= CLK_CO_PHASE_180;
> meson_mmc_clk |= CLK_TX_PHASE_000;
> meson_mmc_clk |= CLK_SRC_DIV2;
> meson_mmc_clk |= 40;
>
> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
> => meson_mmc_clk = 0x268
>
> With your code :
> meson_mmc_clk |= CLK_DIV_MASK;
> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> meson_mmc_clk |= CLK_SRC_DIV2;
> meson_mmc_clk |= 40;
>
> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
>
> -------------------/\---this---------makes-------this-----useless------------------/\
>
> => 0x27f
>
> It sets the clock to 15873015Hz instead of the 25000000Hz requested.

I did not observer this at my end, but any way thanks for the input.

>
> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
>
> >
> >>
> >>
> >>> +     /* Clock source : Crystal 24MHz */
> >>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>
> >> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >> meson_mmc_clk |= clk_src;
> >>
> >> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >> freq asked by the mmc core !
> >>
> > As per the datasheet S905 and S922X
> > Cfg_src:             Clock source
> >                           0: Crystal 24MHz or other frequencies
> > selected by clock reset test control register.
> >                           1: Fix PLL, 1000MHz
> >                           Recommended value: 1
> >
> > Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> > some how break the clk_freq tuning setting in my testing,
> > see the logs below.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > starting USB...
> >
> > No emmc will get discovered,
> > *This is the real issue I faced for failure of eMMC not getting detected.*
>
> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
>
> This issue is somewhere else, but I don't know where because the Linux driver behaves
> correctly with the same setup.
>
> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.

I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
       if (mmc->clock > 400000) {
               /* Clock source : Fix PLL, 1000MHz */
               meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
       } else {
               /* Clock source : Crystal 24MHz */
               meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
       }
>
> Could you post instead :
> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1

Ok I will change the order.

> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2

I propose the dynamically select 24MHz and Fix PLL, as above code.

> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
>

Ok I will make these changes

> If you have a issue, please chat with me on #linux-amlogic on freenode.

I could not connect to freenode or register my self to this chat
group. sorry about that.

>
> Thanks,
> Neil
>

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-10  9:35         ` Jerome Brunet
@ 2020-02-13 12:04           ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 12:04 UTC (permalink / raw)
  To: u-boot

Hi Jerome / Neil,

On Mon, 10 Feb 2020 at 15:05, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Sun 09 Feb 2020 at 18:22, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > Hi Neil,
> >
> > Thanks for you review comments.
> >
> > On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> Hi,
> >>
> >> Le 09/02/2020 ? 12:05, Anand Moon a ?crit :
> >> > As per mainline line kernel fix the clk tuning phase for mmc,
> >> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >> > As per S905, S905X, AGX and S922X datasheet set the default
> >> > values for clk tuning.
> >> >
> >> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >> > ---
> >> > Changes from previous
> >> > v5  Fix the commit message, configure as per mainline kernel.
> >> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >> >
> >> > v4  Fix the update mask value using FIELD_PREP macro.
> >> >
> >> > v3  Fix the initialization of core clk tunning phase as per datasheet.
> >> >     Fix the commit message.
> >> >
> >> > v2: Fix the clk phase macro to support PHASE_180
> >> >     drop the wrong CLK_CORE_PHASE_MASK macro.
> >> >
> >> > v1: use the mainline kernel tuning for clk tuning.
> >> >
> >> > Fixed the commmit messages.
> >> > Patch v1:
> >> > https://patchwork.ozlabs.org/patch/1201208/
> >> >
> >> > Before these changes.
> >> >     clock is enabled (380953Hz)
> >> >     clock is enabled (25000000Hz)
> >> > After these changes
> >> >     clock is enabled (380953Hz)
> >> >     clock is enabled (25000000Hz)
> >> >     clock is enabled (52000000Hz)
> >> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >> > ---
> >> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >> >  2 files changed, 38 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > index e3a72c8b66..f4299485dc 100644
> >> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > @@ -7,6 +7,7 @@
> >> >  #define __SD_EMMC_H__
> >> >
> >> >  #include <mmc.h>
> >> > +#include <linux/bitops.h>
> >> >
> >> >  #define SDIO_PORT_A                  0
> >> >  #define SDIO_PORT_B                  1
> >> > @@ -19,15 +20,20 @@
> >> >  #define   CLK_MAX_DIV                        63
> >> >  #define   CLK_SRC_24M                        (0 << 6)
> >> >  #define   CLK_SRC_DIV2                       (1 << 6)
> >> > -#define   CLK_CO_PHASE_000           (0 << 8)
> >> > -#define   CLK_CO_PHASE_090           (1 << 8)
> >> > -#define   CLK_CO_PHASE_180           (2 << 8)
> >> > -#define   CLK_CO_PHASE_270           (3 << 8)
> >> > -#define   CLK_TX_PHASE_000           (0 << 10)
> >> > -#define   CLK_TX_PHASE_090           (1 << 10)
> >> > -#define   CLK_TX_PHASE_180           (2 << 10)
> >> > -#define   CLK_TX_PHASE_270           (3 << 10)
> >> > -#define   CLK_ALWAYS_ON                      BIT(24)
> >> > +
> >> > +#define   CRYSTAL_24MHZ                      0
> >> > +#define   CLK_PHASE_0                        0
> >> > +#define   CLK_PHASE_180                      2
> >> > +
> >> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >> > +
> >> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >> > +
> >> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >> >
> >> >  #define MESON_SD_EMMC_CFG            0x44
> >> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >> > index 86c1a7164a..b013c7c5fb 100644
> >> > --- a/drivers/mmc/meson_gx_mmc.c
> >> > +++ b/drivers/mmc/meson_gx_mmc.c
> >> > @@ -16,6 +16,10 @@
> >> >  #include <asm/arch/sd_emmc.h>
> >> >  #include <linux/log2.h>
> >> >
> >> > +#include <linux/bitops.h>
> >> > +#include <linux/compat.h>
> >> > +#include <linux/bitfield.h>
> >> > +
> >> >  static inline void *get_regbase(const struct mmc *mmc)
> >> >  {
> >> >       struct meson_mmc_platdata *pdata = mmc->priv;
> >> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >> >       }
> >> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >> >
> >> > -     /* 180 phase core clock */
> >> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >> > -
> >> > -     /* 180 phase tx clock */
> >> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >> > +     /* Clock divider */
> >> > +     meson_mmc_clk |= CLK_DIV_MASK;
> >>
> >> This will set the max divider, whatever the value of clk_div, so the following statement:
> >> meson_mmc_clk |= clk_div;
> >> will have no effect.
> >
> > As per the datasheet S905 and S922X max divider is 63.
> > CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >                                         Frequency = clock source/cfg_div
> >                                         Clock off: cfg_div==0, the
> > clock is disabled
> >                                         Divider bypass: cfg_div==1,
> > clock source is used as core clock without divider
> >                                         Maximum divider 63
> >
> > So here is the log of clk_div and clk_freq at my end.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > clock is enabled (25000000Hz)
> > ......clk_div : 40
> > ......clk_div : 40
> > clock is enabled (52000000Hz)
> > ......clk_div : 20
> > switch to partitions #0, OK
> > mmc2(part 0) is current device
> > Scanning mmc 2:1...
> > Found U-Boot script /boot/boot.scr
> >
> >>
> >>
> >> > +     /* Clock source : Crystal 24MHz */
> >> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>
> >> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >> meson_mmc_clk |= clk_src;
> >>
> >> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >> freq asked by the mmc core !
> >>
> > As per the datasheet S905 and S922X
> > Cfg_src:             Clock source
> >                           0: Crystal 24MHz or other frequencies
> > selected by clock reset test control register.
> >                           1: Fix PLL, 1000MHz
> >                           Recommended value: 1
> >
> > Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> > some how break the clk_freq tuning setting in my testing,
> > see the logs below.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > starting USB...
> >
> > No emmc will get discovered,
> > *This is the real issue I faced for failure of eMMC not getting
> > detected.*
>
> I don't think the reality of the issue reported has been questioned.
> What is being questioned is the proposed solution.
>
> The patch you sent forces clock input 0 with the maximum divider
> possible. This is an important comment for which an explanation is
> missing AFAICT.
>
> 1) The doc is not clear but input 0 is not always the oscillator. It is
> the MMC composite clock which can set to several different sources,
> especially when the ROM code boots from another device, such as SPI
> This is the topic of 2 patches I sent recently (not yet merged)
>
> 2) Let's assume that input 0 is indeed 24M, your patches forces this
> with a 63 divider => 380kHz. With a clock that low, the phase does not
> matter much anymore
>
> IOW, you are the only one to report this issue on one specific case, the
> cause of the issue is not really identified and the work around would:
> * Add statements without effect in the code
> * Considerably slow down eMMC and SDCard on all amlogic platforms.
> * Provide no explanation about how it actually solves something
>
> This is problematic ...
>

Ok Thanks for your review comments.
I have tried to test these on all the device that I have with all the
emmc sdcards.
I have almost used the mainline code to resolve this issue.
but my approach to address this was not up to date.

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-13 12:04           ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 12:04 UTC (permalink / raw)
  To: Jerome Brunet
  Cc: Neil Armstrong, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Jerome / Neil,

On Mon, 10 Feb 2020 at 15:05, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Sun 09 Feb 2020 at 18:22, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > Hi Neil,
> >
> > Thanks for you review comments.
> >
> > On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> Hi,
> >>
> >> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> >> > As per mainline line kernel fix the clk tuning phase for mmc,
> >> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >> > As per S905, S905X, AGX and S922X datasheet set the default
> >> > values for clk tuning.
> >> >
> >> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >> > ---
> >> > Changes from previous
> >> > v5  Fix the commit message, configure as per mainline kernel.
> >> >     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >> >
> >> > v4  Fix the update mask value using FIELD_PREP macro.
> >> >
> >> > v3  Fix the initialization of core clk tunning phase as per datasheet.
> >> >     Fix the commit message.
> >> >
> >> > v2: Fix the clk phase macro to support PHASE_180
> >> >     drop the wrong CLK_CORE_PHASE_MASK macro.
> >> >
> >> > v1: use the mainline kernel tuning for clk tuning.
> >> >
> >> > Fixed the commmit messages.
> >> > Patch v1:
> >> > https://patchwork.ozlabs.org/patch/1201208/
> >> >
> >> > Before these changes.
> >> >     clock is enabled (380953Hz)
> >> >     clock is enabled (25000000Hz)
> >> > After these changes
> >> >     clock is enabled (380953Hz)
> >> >     clock is enabled (25000000Hz)
> >> >     clock is enabled (52000000Hz)
> >> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >> > ---
> >> >  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >> >  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >> >  2 files changed, 38 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > index e3a72c8b66..f4299485dc 100644
> >> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > @@ -7,6 +7,7 @@
> >> >  #define __SD_EMMC_H__
> >> >
> >> >  #include <mmc.h>
> >> > +#include <linux/bitops.h>
> >> >
> >> >  #define SDIO_PORT_A                  0
> >> >  #define SDIO_PORT_B                  1
> >> > @@ -19,15 +20,20 @@
> >> >  #define   CLK_MAX_DIV                        63
> >> >  #define   CLK_SRC_24M                        (0 << 6)
> >> >  #define   CLK_SRC_DIV2                       (1 << 6)
> >> > -#define   CLK_CO_PHASE_000           (0 << 8)
> >> > -#define   CLK_CO_PHASE_090           (1 << 8)
> >> > -#define   CLK_CO_PHASE_180           (2 << 8)
> >> > -#define   CLK_CO_PHASE_270           (3 << 8)
> >> > -#define   CLK_TX_PHASE_000           (0 << 10)
> >> > -#define   CLK_TX_PHASE_090           (1 << 10)
> >> > -#define   CLK_TX_PHASE_180           (2 << 10)
> >> > -#define   CLK_TX_PHASE_270           (3 << 10)
> >> > -#define   CLK_ALWAYS_ON                      BIT(24)
> >> > +
> >> > +#define   CRYSTAL_24MHZ                      0
> >> > +#define   CLK_PHASE_0                        0
> >> > +#define   CLK_PHASE_180                      2
> >> > +
> >> > +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >> > +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >> > +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >> > +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >> > +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >> > +
> >> > +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >> > +
> >> > +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >> >
> >> >  #define MESON_SD_EMMC_CFG            0x44
> >> >  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >> > index 86c1a7164a..b013c7c5fb 100644
> >> > --- a/drivers/mmc/meson_gx_mmc.c
> >> > +++ b/drivers/mmc/meson_gx_mmc.c
> >> > @@ -16,6 +16,10 @@
> >> >  #include <asm/arch/sd_emmc.h>
> >> >  #include <linux/log2.h>
> >> >
> >> > +#include <linux/bitops.h>
> >> > +#include <linux/compat.h>
> >> > +#include <linux/bitfield.h>
> >> > +
> >> >  static inline void *get_regbase(const struct mmc *mmc)
> >> >  {
> >> >       struct meson_mmc_platdata *pdata = mmc->priv;
> >> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >> >       }
> >> >       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >> >
> >> > -     /* 180 phase core clock */
> >> > -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >> > -
> >> > -     /* 180 phase tx clock */
> >> > -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >> > +     /* Clock divider */
> >> > +     meson_mmc_clk |= CLK_DIV_MASK;
> >>
> >> This will set the max divider, whatever the value of clk_div, so the following statement:
> >> meson_mmc_clk |= clk_div;
> >> will have no effect.
> >
> > As per the datasheet S905 and S922X max divider is 63.
> > CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >                                         Frequency = clock source/cfg_div
> >                                         Clock off: cfg_div==0, the
> > clock is disabled
> >                                         Divider bypass: cfg_div==1,
> > clock source is used as core clock without divider
> >                                         Maximum divider 63
> >
> > So here is the log of clk_div and clk_freq at my end.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > clock is enabled (25000000Hz)
> > ......clk_div : 40
> > ......clk_div : 40
> > clock is enabled (52000000Hz)
> > ......clk_div : 20
> > switch to partitions #0, OK
> > mmc2(part 0) is current device
> > Scanning mmc 2:1...
> > Found U-Boot script /boot/boot.scr
> >
> >>
> >>
> >> > +     /* Clock source : Crystal 24MHz */
> >> > +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>
> >> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >> meson_mmc_clk |= clk_src;
> >>
> >> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >> freq asked by the mmc core !
> >>
> > As per the datasheet S905 and S922X
> > Cfg_src:             Clock source
> >                           0: Crystal 24MHz or other frequencies
> > selected by clock reset test control register.
> >                           1: Fix PLL, 1000MHz
> >                           Recommended value: 1
> >
> > Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> > some how break the clk_freq tuning setting in my testing,
> > see the logs below.
> >
> > MMC Device 0 not found
> > no mmc device at slot 0
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > Card did not respond to voltage select!
> > clock is disabled (0Hz)
> > clock is enabled (380953Hz)
> > ......clk_div : 63
> > starting USB...
> >
> > No emmc will get discovered,
> > *This is the real issue I faced for failure of eMMC not getting
> > detected.*
>
> I don't think the reality of the issue reported has been questioned.
> What is being questioned is the proposed solution.
>
> The patch you sent forces clock input 0 with the maximum divider
> possible. This is an important comment for which an explanation is
> missing AFAICT.
>
> 1) The doc is not clear but input 0 is not always the oscillator. It is
> the MMC composite clock which can set to several different sources,
> especially when the ROM code boots from another device, such as SPI
> This is the topic of 2 patches I sent recently (not yet merged)
>
> 2) Let's assume that input 0 is indeed 24M, your patches forces this
> with a 63 divider => 380kHz. With a clock that low, the phase does not
> matter much anymore
>
> IOW, you are the only one to report this issue on one specific case, the
> cause of the issue is not really identified and the work around would:
> * Add statements without effect in the code
> * Considerably slow down eMMC and SDCard on all amlogic platforms.
> * Provide no explanation about how it actually solves something
>
> This is problematic ...
>

Ok Thanks for your review comments.
I have tried to test these on all the device that I have with all the
emmc sdcards.
I have almost used the mainline code to resolve this issue.
but my approach to address this was not up to date.

-Anand

^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-13 11:58           ` Anand Moon
@ 2020-02-13 15:39             ` Neil Armstrong
  -1 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-13 15:39 UTC (permalink / raw)
  To: u-boot

On 13/02/2020 12:58, Anand Moon wrote:
> hi Niel / Jerome,
> 
> Thanks for your review comments and debug output
> Sorry for late reply.
> 
> On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> On 09/02/2020 18:22, Anand Moon wrote:
>>> Hi Neil,
>>>
>>> Thanks for you review comments.
>>>
>>> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>>>
>>>> Hi,
>>>>
>>>> Le 09/02/2020 ? 12:05, Anand Moon a ?crit :
>>>>> As per mainline line kernel fix the clk tuning phase for mmc,
>>>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>>>>> As per S905, S905X, AGX and S922X datasheet set the default
>>>>> values for clk tuning.
>>>>>
>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>>>> ---
>>>>> Changes from previous
>>>>> v5  Fix the commit message, configure as per mainline kernel.
>>>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>>>>>
>>>>> v4  Fix the update mask value using FIELD_PREP macro.
>>>>>
>>>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
>>>>>     Fix the commit message.
>>>>>
>>>>> v2: Fix the clk phase macro to support PHASE_180
>>>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
>>>>>
>>>>> v1: use the mainline kernel tuning for clk tuning.
>>>>>
>>>>> Fixed the commmit messages.
>>>>> Patch v1:
>>>>> https://patchwork.ozlabs.org/patch/1201208/
>>>>>
>>>>> Before these changes.
>>>>>     clock is enabled (380953Hz)
>>>>>     clock is enabled (25000000Hz)
>>>>> After these changes
>>>>>     clock is enabled (380953Hz)
>>>>>     clock is enabled (25000000Hz)
>>>>>     clock is enabled (52000000Hz)
>>>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>>>>> ---
>>>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>>>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>>>>>  2 files changed, 38 insertions(+), 14 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> index e3a72c8b66..f4299485dc 100644
>>>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> @@ -7,6 +7,7 @@
>>>>>  #define __SD_EMMC_H__
>>>>>
>>>>>  #include <mmc.h>
>>>>> +#include <linux/bitops.h>
>>>>>
>>>>>  #define SDIO_PORT_A                  0
>>>>>  #define SDIO_PORT_B                  1
>>>>> @@ -19,15 +20,20 @@
>>>>>  #define   CLK_MAX_DIV                        63
>>>>>  #define   CLK_SRC_24M                        (0 << 6)
>>>>>  #define   CLK_SRC_DIV2                       (1 << 6)
>>>>> -#define   CLK_CO_PHASE_000           (0 << 8)
>>>>> -#define   CLK_CO_PHASE_090           (1 << 8)
>>>>> -#define   CLK_CO_PHASE_180           (2 << 8)
>>>>> -#define   CLK_CO_PHASE_270           (3 << 8)
>>>>> -#define   CLK_TX_PHASE_000           (0 << 10)
>>>>> -#define   CLK_TX_PHASE_090           (1 << 10)
>>>>> -#define   CLK_TX_PHASE_180           (2 << 10)
>>>>> -#define   CLK_TX_PHASE_270           (3 << 10)
>>>>> -#define   CLK_ALWAYS_ON                      BIT(24)
>>>>> +
>>>>> +#define   CRYSTAL_24MHZ                      0
>>>>> +#define   CLK_PHASE_0                        0
>>>>> +#define   CLK_PHASE_180                      2
>>>>> +
>>>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>>>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>>>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>>>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>>>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>>>>> +
>>>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
>>>>> +
>>>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
>>>>>
>>>>>  #define MESON_SD_EMMC_CFG            0x44
>>>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>>>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>>>> index 86c1a7164a..b013c7c5fb 100644
>>>>> --- a/drivers/mmc/meson_gx_mmc.c
>>>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>>>> @@ -16,6 +16,10 @@
>>>>>  #include <asm/arch/sd_emmc.h>
>>>>>  #include <linux/log2.h>
>>>>>
>>>>> +#include <linux/bitops.h>
>>>>> +#include <linux/compat.h>
>>>>> +#include <linux/bitfield.h>
>>>>> +
>>>>>  static inline void *get_regbase(const struct mmc *mmc)
>>>>>  {
>>>>>       struct meson_mmc_platdata *pdata = mmc->priv;
>>>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>>>       }
>>>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>>>>>
>>>>> -     /* 180 phase core clock */
>>>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
>>>>> -
>>>>> -     /* 180 phase tx clock */
>>>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
>>>>> +     /* Clock divider */
>>>>> +     meson_mmc_clk |= CLK_DIV_MASK;
>>>>
>>>> This will set the max divider, whatever the value of clk_div, so the following statement:
>>>> meson_mmc_clk |= clk_div;
>>>> will have no effect.
>>>
>>> As per the datasheet S905 and S922X max divider is 63.
>>> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>>>                                         Frequency = clock source/cfg_div
>>>                                         Clock off: cfg_div==0, the
>>> clock is disabled
>>>                                         Divider bypass: cfg_div==1,
>>> clock source is used as core clock without divider
>>>                                         Maximum divider 63
>>>
>>> So here is the log of clk_div and clk_freq at my end.
>>>
>>> MMC Device 0 not found
>>> no mmc device at slot 0
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> Card did not respond to voltage select!
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> clock is enabled (25000000Hz)
>>> ......clk_div : 40
>>> ......clk_div : 40
>>> clock is enabled (52000000Hz)
>>> ......clk_div : 20
>>> switch to partitions #0, OK
>>> mmc2(part 0) is current device
>>> Scanning mmc 2:1...
>>> Found U-Boot script /boot/boot.scr
>>
>>
>> OK, seems you didn't see the issue.
>>
>> With the original code, let's say mmc->clock = 25000000
>>
>> clk = SD_EMMC_CLKSRC_DIV2
>> clk_src = CLK_SRC_DIV2
>> clk_div = 40
>>
>> meson_mmc_clk |= CLK_CO_PHASE_180;
>> meson_mmc_clk |= CLK_TX_PHASE_000;
>> meson_mmc_clk |= CLK_SRC_DIV2;
>> meson_mmc_clk |= 40;
>>
>> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
>> => meson_mmc_clk = 0x268
>>
>> With your code :
>> meson_mmc_clk |= CLK_DIV_MASK;
>> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>> meson_mmc_clk |= CLK_SRC_DIV2;
>> meson_mmc_clk |= 40;
>>
>> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
>>
>> -------------------/\---this---------makes-------this-----useless------------------/\
>>
>> => 0x27f
>>
>> It sets the clock to 15873015Hz instead of the 25000000Hz requested.
> 
> I did not observer this at my end, but any way thanks for the input.
> 
>>
>> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
>>
>>>
>>>>
>>>>
>>>>> +     /* Clock source : Crystal 24MHz */
>>>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>>>
>>>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>>>> meson_mmc_clk |= clk_src;
>>>>
>>>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>>>> freq asked by the mmc core !
>>>>
>>> As per the datasheet S905 and S922X
>>> Cfg_src:             Clock source
>>>                           0: Crystal 24MHz or other frequencies
>>> selected by clock reset test control register.
>>>                           1: Fix PLL, 1000MHz
>>>                           Recommended value: 1
>>>
>>> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
>>> some how break the clk_freq tuning setting in my testing,
>>> see the logs below.
>>>
>>> MMC Device 0 not found
>>> no mmc device at slot 0
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> Card did not respond to voltage select!
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> starting USB...
>>>
>>> No emmc will get discovered,
>>> *This is the real issue I faced for failure of eMMC not getting detected.*
>>
>> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
>>
>> This issue is somewhere else, but I don't know where because the Linux driver behaves
>> correctly with the same setup.
>>
>> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.
> 
> I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
> I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
>        if (mmc->clock > 400000) {
>                /* Clock source : Fix PLL, 1000MHz */
>                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
>        } else {
>                /* Clock source : Crystal 24MHz */
>                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>        }

This is still wrong and broken. The original code is correct and works fine.

As Jerome said, the underlying issue must be understood, why when using the FIXPLL clock source, it fails ?

The clock setup function is correct, don't try to fix it.

The weirdness is why does it works under linux ? maybe the fixpll clock setup is different ?

Could you dump the emmc and clock registers from linux to see the difference ?

Neil

>>
>> Could you post instead :
>> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
> 
> Ok I will change the order.
> 
>> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
> 
> I propose the dynamically select 24MHz and Fix PLL, as above code.
> 
>> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
>>
> 
> Ok I will make these changes
> 
>> If you have a issue, please chat with me on #linux-amlogic on freenode.
> 
> I could not connect to freenode or register my self to this chat
> group. sorry about that.
> 
>>
>> Thanks,
>> Neil
>>
> 
> -Anand
> 

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-13 15:39             ` Neil Armstrong
  0 siblings, 0 replies; 48+ messages in thread
From: Neil Armstrong @ 2020-02-13 15:39 UTC (permalink / raw)
  To: Anand Moon
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

On 13/02/2020 12:58, Anand Moon wrote:
> hi Niel / Jerome,
> 
> Thanks for your review comments and debug output
> Sorry for late reply.
> 
> On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> On 09/02/2020 18:22, Anand Moon wrote:
>>> Hi Neil,
>>>
>>> Thanks for you review comments.
>>>
>>> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>>>
>>>> Hi,
>>>>
>>>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>>>>> As per mainline line kernel fix the clk tuning phase for mmc,
>>>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>>>>> As per S905, S905X, AGX and S922X datasheet set the default
>>>>> values for clk tuning.
>>>>>
>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>>>> ---
>>>>> Changes from previous
>>>>> v5  Fix the commit message, configure as per mainline kernel.
>>>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>>>>>
>>>>> v4  Fix the update mask value using FIELD_PREP macro.
>>>>>
>>>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
>>>>>     Fix the commit message.
>>>>>
>>>>> v2: Fix the clk phase macro to support PHASE_180
>>>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
>>>>>
>>>>> v1: use the mainline kernel tuning for clk tuning.
>>>>>
>>>>> Fixed the commmit messages.
>>>>> Patch v1:
>>>>> https://patchwork.ozlabs.org/patch/1201208/
>>>>>
>>>>> Before these changes.
>>>>>     clock is enabled (380953Hz)
>>>>>     clock is enabled (25000000Hz)
>>>>> After these changes
>>>>>     clock is enabled (380953Hz)
>>>>>     clock is enabled (25000000Hz)
>>>>>     clock is enabled (52000000Hz)
>>>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>>>>> ---
>>>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
>>>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
>>>>>  2 files changed, 38 insertions(+), 14 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> index e3a72c8b66..f4299485dc 100644
>>>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>>>>> @@ -7,6 +7,7 @@
>>>>>  #define __SD_EMMC_H__
>>>>>
>>>>>  #include <mmc.h>
>>>>> +#include <linux/bitops.h>
>>>>>
>>>>>  #define SDIO_PORT_A                  0
>>>>>  #define SDIO_PORT_B                  1
>>>>> @@ -19,15 +20,20 @@
>>>>>  #define   CLK_MAX_DIV                        63
>>>>>  #define   CLK_SRC_24M                        (0 << 6)
>>>>>  #define   CLK_SRC_DIV2                       (1 << 6)
>>>>> -#define   CLK_CO_PHASE_000           (0 << 8)
>>>>> -#define   CLK_CO_PHASE_090           (1 << 8)
>>>>> -#define   CLK_CO_PHASE_180           (2 << 8)
>>>>> -#define   CLK_CO_PHASE_270           (3 << 8)
>>>>> -#define   CLK_TX_PHASE_000           (0 << 10)
>>>>> -#define   CLK_TX_PHASE_090           (1 << 10)
>>>>> -#define   CLK_TX_PHASE_180           (2 << 10)
>>>>> -#define   CLK_TX_PHASE_270           (3 << 10)
>>>>> -#define   CLK_ALWAYS_ON                      BIT(24)
>>>>> +
>>>>> +#define   CRYSTAL_24MHZ                      0
>>>>> +#define   CLK_PHASE_0                        0
>>>>> +#define   CLK_PHASE_180                      2
>>>>> +
>>>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
>>>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
>>>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
>>>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
>>>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
>>>>> +
>>>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
>>>>> +
>>>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
>>>>>
>>>>>  #define MESON_SD_EMMC_CFG            0x44
>>>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
>>>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>>>>> index 86c1a7164a..b013c7c5fb 100644
>>>>> --- a/drivers/mmc/meson_gx_mmc.c
>>>>> +++ b/drivers/mmc/meson_gx_mmc.c
>>>>> @@ -16,6 +16,10 @@
>>>>>  #include <asm/arch/sd_emmc.h>
>>>>>  #include <linux/log2.h>
>>>>>
>>>>> +#include <linux/bitops.h>
>>>>> +#include <linux/compat.h>
>>>>> +#include <linux/bitfield.h>
>>>>> +
>>>>>  static inline void *get_regbase(const struct mmc *mmc)
>>>>>  {
>>>>>       struct meson_mmc_platdata *pdata = mmc->priv;
>>>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>>>>       }
>>>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
>>>>>
>>>>> -     /* 180 phase core clock */
>>>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
>>>>> -
>>>>> -     /* 180 phase tx clock */
>>>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
>>>>> +     /* Clock divider */
>>>>> +     meson_mmc_clk |= CLK_DIV_MASK;
>>>>
>>>> This will set the max divider, whatever the value of clk_div, so the following statement:
>>>> meson_mmc_clk |= clk_div;
>>>> will have no effect.
>>>
>>> As per the datasheet S905 and S922X max divider is 63.
>>> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
>>>                                         Frequency = clock source/cfg_div
>>>                                         Clock off: cfg_div==0, the
>>> clock is disabled
>>>                                         Divider bypass: cfg_div==1,
>>> clock source is used as core clock without divider
>>>                                         Maximum divider 63
>>>
>>> So here is the log of clk_div and clk_freq at my end.
>>>
>>> MMC Device 0 not found
>>> no mmc device at slot 0
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> Card did not respond to voltage select!
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> clock is enabled (25000000Hz)
>>> ......clk_div : 40
>>> ......clk_div : 40
>>> clock is enabled (52000000Hz)
>>> ......clk_div : 20
>>> switch to partitions #0, OK
>>> mmc2(part 0) is current device
>>> Scanning mmc 2:1...
>>> Found U-Boot script /boot/boot.scr
>>
>>
>> OK, seems you didn't see the issue.
>>
>> With the original code, let's say mmc->clock = 25000000
>>
>> clk = SD_EMMC_CLKSRC_DIV2
>> clk_src = CLK_SRC_DIV2
>> clk_div = 40
>>
>> meson_mmc_clk |= CLK_CO_PHASE_180;
>> meson_mmc_clk |= CLK_TX_PHASE_000;
>> meson_mmc_clk |= CLK_SRC_DIV2;
>> meson_mmc_clk |= 40;
>>
>> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
>> => meson_mmc_clk = 0x268
>>
>> With your code :
>> meson_mmc_clk |= CLK_DIV_MASK;
>> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
>> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>> meson_mmc_clk |= CLK_SRC_DIV2;
>> meson_mmc_clk |= 40;
>>
>> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
>>
>> -------------------/\---this---------makes-------this-----useless------------------/\
>>
>> => 0x27f
>>
>> It sets the clock to 15873015Hz instead of the 25000000Hz requested.
> 
> I did not observer this at my end, but any way thanks for the input.
> 
>>
>> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
>>
>>>
>>>>
>>>>
>>>>> +     /* Clock source : Crystal 24MHz */
>>>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>>>>
>>>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
>>>> meson_mmc_clk |= clk_src;
>>>>
>>>> In conclusion your change forces the 24MHz crystal and max divider whatever the
>>>> freq asked by the mmc core !
>>>>
>>> As per the datasheet S905 and S922X
>>> Cfg_src:             Clock source
>>>                           0: Crystal 24MHz or other frequencies
>>> selected by clock reset test control register.
>>>                           1: Fix PLL, 1000MHz
>>>                           Recommended value: 1
>>>
>>> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
>>> some how break the clk_freq tuning setting in my testing,
>>> see the logs below.
>>>
>>> MMC Device 0 not found
>>> no mmc device at slot 0
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> Card did not respond to voltage select!
>>> clock is disabled (0Hz)
>>> clock is enabled (380953Hz)
>>> ......clk_div : 63
>>> starting USB...
>>>
>>> No emmc will get discovered,
>>> *This is the real issue I faced for failure of eMMC not getting detected.*
>>
>> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
>>
>> This issue is somewhere else, but I don't know where because the Linux driver behaves
>> correctly with the same setup.
>>
>> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.
> 
> I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
> I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
>        if (mmc->clock > 400000) {
>                /* Clock source : Fix PLL, 1000MHz */
>                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
>        } else {
>                /* Clock source : Crystal 24MHz */
>                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>        }

This is still wrong and broken. The original code is correct and works fine.

As Jerome said, the underlying issue must be understood, why when using the FIXPLL clock source, it fails ?

The clock setup function is correct, don't try to fix it.

The weirdness is why does it works under linux ? maybe the fixpll clock setup is different ?

Could you dump the emmc and clock registers from linux to see the difference ?

Neil

>>
>> Could you post instead :
>> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
> 
> Ok I will change the order.
> 
>> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
> 
> I propose the dynamically select 24MHz and Fix PLL, as above code.
> 
>> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
>>
> 
> Ok I will make these changes
> 
>> If you have a issue, please chat with me on #linux-amlogic on freenode.
> 
> I could not connect to freenode or register my self to this chat
> group. sorry about that.
> 
>>
>> Thanks,
>> Neil
>>
> 
> -Anand
> 


^ permalink raw reply	[flat|nested] 48+ messages in thread

* [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
  2020-02-13 15:39             ` Neil Armstrong
@ 2020-02-13 16:41               ` Anand Moon
  -1 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 16:41 UTC (permalink / raw)
  To: u-boot

Hi Neil,

On Thu, 13 Feb 2020 at 21:09, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 13/02/2020 12:58, Anand Moon wrote:
> > hi Niel / Jerome,
> >
> > Thanks for your review comments and debug output
> > Sorry for late reply.
> >
> > On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> On 09/02/2020 18:22, Anand Moon wrote:
> >>> Hi Neil,
> >>>
> >>> Thanks for you review comments.
> >>>
> >>> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>>>
> >>>> Hi,
> >>>>
> >>>> Le 09/02/2020 ? 12:05, Anand Moon a ?crit :
> >>>>> As per mainline line kernel fix the clk tuning phase for mmc,
> >>>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >>>>> As per S905, S905X, AGX and S922X datasheet set the default
> >>>>> values for clk tuning.
> >>>>>
> >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>>>> ---
> >>>>> Changes from previous
> >>>>> v5  Fix the commit message, configure as per mainline kernel.
> >>>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >>>>>
> >>>>> v4  Fix the update mask value using FIELD_PREP macro.
> >>>>>
> >>>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
> >>>>>     Fix the commit message.
> >>>>>
> >>>>> v2: Fix the clk phase macro to support PHASE_180
> >>>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
> >>>>>
> >>>>> v1: use the mainline kernel tuning for clk tuning.
> >>>>>
> >>>>> Fixed the commmit messages.
> >>>>> Patch v1:
> >>>>> https://patchwork.ozlabs.org/patch/1201208/
> >>>>>
> >>>>> Before these changes.
> >>>>>     clock is enabled (380953Hz)
> >>>>>     clock is enabled (25000000Hz)
> >>>>> After these changes
> >>>>>     clock is enabled (380953Hz)
> >>>>>     clock is enabled (25000000Hz)
> >>>>>     clock is enabled (52000000Hz)
> >>>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >>>>> ---
> >>>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >>>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >>>>>  2 files changed, 38 insertions(+), 14 deletions(-)
> >>>>>
> >>>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> index e3a72c8b66..f4299485dc 100644
> >>>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> @@ -7,6 +7,7 @@
> >>>>>  #define __SD_EMMC_H__
> >>>>>
> >>>>>  #include <mmc.h>
> >>>>> +#include <linux/bitops.h>
> >>>>>
> >>>>>  #define SDIO_PORT_A                  0
> >>>>>  #define SDIO_PORT_B                  1
> >>>>> @@ -19,15 +20,20 @@
> >>>>>  #define   CLK_MAX_DIV                        63
> >>>>>  #define   CLK_SRC_24M                        (0 << 6)
> >>>>>  #define   CLK_SRC_DIV2                       (1 << 6)
> >>>>> -#define   CLK_CO_PHASE_000           (0 << 8)
> >>>>> -#define   CLK_CO_PHASE_090           (1 << 8)
> >>>>> -#define   CLK_CO_PHASE_180           (2 << 8)
> >>>>> -#define   CLK_CO_PHASE_270           (3 << 8)
> >>>>> -#define   CLK_TX_PHASE_000           (0 << 10)
> >>>>> -#define   CLK_TX_PHASE_090           (1 << 10)
> >>>>> -#define   CLK_TX_PHASE_180           (2 << 10)
> >>>>> -#define   CLK_TX_PHASE_270           (3 << 10)
> >>>>> -#define   CLK_ALWAYS_ON                      BIT(24)
> >>>>> +
> >>>>> +#define   CRYSTAL_24MHZ                      0
> >>>>> +#define   CLK_PHASE_0                        0
> >>>>> +#define   CLK_PHASE_180                      2
> >>>>> +
> >>>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >>>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >>>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >>>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >>>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >>>>> +
> >>>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >>>>> +
> >>>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >>>>>
> >>>>>  #define MESON_SD_EMMC_CFG            0x44
> >>>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >>>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >>>>> index 86c1a7164a..b013c7c5fb 100644
> >>>>> --- a/drivers/mmc/meson_gx_mmc.c
> >>>>> +++ b/drivers/mmc/meson_gx_mmc.c
> >>>>> @@ -16,6 +16,10 @@
> >>>>>  #include <asm/arch/sd_emmc.h>
> >>>>>  #include <linux/log2.h>
> >>>>>
> >>>>> +#include <linux/bitops.h>
> >>>>> +#include <linux/compat.h>
> >>>>> +#include <linux/bitfield.h>
> >>>>> +
> >>>>>  static inline void *get_regbase(const struct mmc *mmc)
> >>>>>  {
> >>>>>       struct meson_mmc_platdata *pdata = mmc->priv;
> >>>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >>>>>       }
> >>>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >>>>>
> >>>>> -     /* 180 phase core clock */
> >>>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >>>>> -
> >>>>> -     /* 180 phase tx clock */
> >>>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >>>>> +     /* Clock divider */
> >>>>> +     meson_mmc_clk |= CLK_DIV_MASK;
> >>>>
> >>>> This will set the max divider, whatever the value of clk_div, so the following statement:
> >>>> meson_mmc_clk |= clk_div;
> >>>> will have no effect.
> >>>
> >>> As per the datasheet S905 and S922X max divider is 63.
> >>> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >>>                                         Frequency = clock source/cfg_div
> >>>                                         Clock off: cfg_div==0, the
> >>> clock is disabled
> >>>                                         Divider bypass: cfg_div==1,
> >>> clock source is used as core clock without divider
> >>>                                         Maximum divider 63
> >>>
> >>> So here is the log of clk_div and clk_freq at my end.
> >>>
> >>> MMC Device 0 not found
> >>> no mmc device at slot 0
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> Card did not respond to voltage select!
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> clock is enabled (25000000Hz)
> >>> ......clk_div : 40
> >>> ......clk_div : 40
> >>> clock is enabled (52000000Hz)
> >>> ......clk_div : 20
> >>> switch to partitions #0, OK
> >>> mmc2(part 0) is current device
> >>> Scanning mmc 2:1...
> >>> Found U-Boot script /boot/boot.scr
> >>
> >>
> >> OK, seems you didn't see the issue.
> >>
> >> With the original code, let's say mmc->clock = 25000000
> >>
> >> clk = SD_EMMC_CLKSRC_DIV2
> >> clk_src = CLK_SRC_DIV2
> >> clk_div = 40
> >>
> >> meson_mmc_clk |= CLK_CO_PHASE_180;
> >> meson_mmc_clk |= CLK_TX_PHASE_000;
> >> meson_mmc_clk |= CLK_SRC_DIV2;
> >> meson_mmc_clk |= 40;
> >>
> >> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
> >> => meson_mmc_clk = 0x268
> >>
> >> With your code :
> >> meson_mmc_clk |= CLK_DIV_MASK;
> >> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> >> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> >> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >> meson_mmc_clk |= CLK_SRC_DIV2;
> >> meson_mmc_clk |= 40;
> >>
> >> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
> >>
> >> -------------------/\---this---------makes-------this-----useless------------------/\
> >>
> >> => 0x27f
> >>
> >> It sets the clock to 15873015Hz instead of the 25000000Hz requested.
> >
> > I did not observer this at my end, but any way thanks for the input.
> >
> >>
> >> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
> >>
> >>>
> >>>>
> >>>>
> >>>>> +     /* Clock source : Crystal 24MHz */
> >>>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>>>
> >>>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >>>> meson_mmc_clk |= clk_src;
> >>>>
> >>>> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >>>> freq asked by the mmc core !
> >>>>
> >>> As per the datasheet S905 and S922X
> >>> Cfg_src:             Clock source
> >>>                           0: Crystal 24MHz or other frequencies
> >>> selected by clock reset test control register.
> >>>                           1: Fix PLL, 1000MHz
> >>>                           Recommended value: 1
> >>>
> >>> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> >>> some how break the clk_freq tuning setting in my testing,
> >>> see the logs below.
> >>>
> >>> MMC Device 0 not found
> >>> no mmc device at slot 0
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> Card did not respond to voltage select!
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> starting USB...
> >>>
> >>> No emmc will get discovered,
> >>> *This is the real issue I faced for failure of eMMC not getting detected.*
> >>
> >> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
> >>
> >> This issue is somewhere else, but I don't know where because the Linux driver behaves
> >> correctly with the same setup.
> >>
> >> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.
> >
> > I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
> > I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
> >        if (mmc->clock > 400000) {
> >                /* Clock source : Fix PLL, 1000MHz */
> >                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
> >        } else {
> >                /* Clock source : Crystal 24MHz */
> >                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >        }
>
> This is still wrong and broken. The original code is correct and works fine.
>
> As Jerome said, the underlying issue must be understood, why when using the FIXPLL clock source, it fails ?
>
> The clock setup function is correct, don't try to fix it.
>
> The weirdness is why does it works under linux ? maybe the fixpll clock setup is different ?
>
> Could you dump the emmc and clock registers from linux to see the difference ?
>
> Neil
>

Ok thanks for this Input. I will try to figure our how it's working in
linux kernel first.

-Anand

> >>
> >> Could you post instead :
> >> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
> >
> > Ok I will change the order.
> >
> >> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
> >
> > I propose the dynamically select 24MHz and Fix PLL, as above code.
> >
> >> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
> >>
> >
> > Ok I will make these changes
> >
> >> If you have a issue, please chat with me on #linux-amlogic on freenode.
> >
> > I could not connect to freenode or register my self to this chat
> > group. sorry about that.
> >
> >>
> >> Thanks,
> >> Neil
> >>
> >
> > -Anand
> >
>

^ permalink raw reply	[flat|nested] 48+ messages in thread

* Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-13 16:41               ` Anand Moon
  0 siblings, 0 replies; 48+ messages in thread
From: Anand Moon @ 2020-02-13 16:41 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Peng Fan, Jaehoon Chung, u-boot-amlogic,
	U-Boot Mailing List

Hi Neil,

On Thu, 13 Feb 2020 at 21:09, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 13/02/2020 12:58, Anand Moon wrote:
> > hi Niel / Jerome,
> >
> > Thanks for your review comments and debug output
> > Sorry for late reply.
> >
> > On Mon, 10 Feb 2020 at 14:33, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> On 09/02/2020 18:22, Anand Moon wrote:
> >>> Hi Neil,
> >>>
> >>> Thanks for you review comments.
> >>>
> >>> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>>>
> >>>> Hi,
> >>>>
> >>>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
> >>>>> As per mainline line kernel fix the clk tuning phase for mmc,
> >>>>> set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >>>>> As per S905, S905X, AGX and S922X datasheet set the default
> >>>>> values for clk tuning.
> >>>>>
> >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>>>> ---
> >>>>> Changes from previous
> >>>>> v5  Fix the commit message, configure as per mainline kernel.
> >>>>>     drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
> >>>>>
> >>>>> v4  Fix the update mask value using FIELD_PREP macro.
> >>>>>
> >>>>> v3  Fix the initialization of core clk tunning phase as per datasheet.
> >>>>>     Fix the commit message.
> >>>>>
> >>>>> v2: Fix the clk phase macro to support PHASE_180
> >>>>>     drop the wrong CLK_CORE_PHASE_MASK macro.
> >>>>>
> >>>>> v1: use the mainline kernel tuning for clk tuning.
> >>>>>
> >>>>> Fixed the commmit messages.
> >>>>> Patch v1:
> >>>>> https://patchwork.ozlabs.org/patch/1201208/
> >>>>>
> >>>>> Before these changes.
> >>>>>     clock is enabled (380953Hz)
> >>>>>     clock is enabled (25000000Hz)
> >>>>> After these changes
> >>>>>     clock is enabled (380953Hz)
> >>>>>     clock is enabled (25000000Hz)
> >>>>>     clock is enabled (52000000Hz)
> >>>>> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> >>>>> ---
> >>>>>  arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++++++++++--------
> >>>>>  drivers/mmc/meson_gx_mmc.c                | 28 +++++++++++++++++++----
> >>>>>  2 files changed, 38 insertions(+), 14 deletions(-)
> >>>>>
> >>>>> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> index e3a72c8b66..f4299485dc 100644
> >>>>> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >>>>> @@ -7,6 +7,7 @@
> >>>>>  #define __SD_EMMC_H__
> >>>>>
> >>>>>  #include <mmc.h>
> >>>>> +#include <linux/bitops.h>
> >>>>>
> >>>>>  #define SDIO_PORT_A                  0
> >>>>>  #define SDIO_PORT_B                  1
> >>>>> @@ -19,15 +20,20 @@
> >>>>>  #define   CLK_MAX_DIV                        63
> >>>>>  #define   CLK_SRC_24M                        (0 << 6)
> >>>>>  #define   CLK_SRC_DIV2                       (1 << 6)
> >>>>> -#define   CLK_CO_PHASE_000           (0 << 8)
> >>>>> -#define   CLK_CO_PHASE_090           (1 << 8)
> >>>>> -#define   CLK_CO_PHASE_180           (2 << 8)
> >>>>> -#define   CLK_CO_PHASE_270           (3 << 8)
> >>>>> -#define   CLK_TX_PHASE_000           (0 << 10)
> >>>>> -#define   CLK_TX_PHASE_090           (1 << 10)
> >>>>> -#define   CLK_TX_PHASE_180           (2 << 10)
> >>>>> -#define   CLK_TX_PHASE_270           (3 << 10)
> >>>>> -#define   CLK_ALWAYS_ON                      BIT(24)
> >>>>> +
> >>>>> +#define   CRYSTAL_24MHZ                      0
> >>>>> +#define   CLK_PHASE_0                        0
> >>>>> +#define   CLK_PHASE_180                      2
> >>>>> +
> >>>>> +#define   CLK_DIV_MASK                       GENMASK(5, 0)
> >>>>> +#define   CLK_SRC_MASK                       GENMASK(7, 6)
> >>>>> +#define   CLK_CORE_PHASE_MASK                GENMASK(9, 8)
> >>>>> +#define   CLK_TX_PHASE_MASK          GENMASK(11, 10)
> >>>>> +#define   CLK_RX_PHASE_MASK          GENMASK(13, 12)
> >>>>> +
> >>>>> +#define   CLK_V2_ALWAYS_ON           BIT(24)
> >>>>> +
> >>>>> +#define   CLK_V3_ALWAYS_ON           BIT(28)
> >>>>>
> >>>>>  #define MESON_SD_EMMC_CFG            0x44
> >>>>>  #define   CFG_BUS_WIDTH_MASK         GENMASK(1, 0)
> >>>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >>>>> index 86c1a7164a..b013c7c5fb 100644
> >>>>> --- a/drivers/mmc/meson_gx_mmc.c
> >>>>> +++ b/drivers/mmc/meson_gx_mmc.c
> >>>>> @@ -16,6 +16,10 @@
> >>>>>  #include <asm/arch/sd_emmc.h>
> >>>>>  #include <linux/log2.h>
> >>>>>
> >>>>> +#include <linux/bitops.h>
> >>>>> +#include <linux/compat.h>
> >>>>> +#include <linux/bitfield.h>
> >>>>> +
> >>>>>  static inline void *get_regbase(const struct mmc *mmc)
> >>>>>  {
> >>>>>       struct meson_mmc_platdata *pdata = mmc->priv;
> >>>>> @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >>>>>       }
> >>>>>       clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >>>>>
> >>>>> -     /* 180 phase core clock */
> >>>>> -     meson_mmc_clk |= CLK_CO_PHASE_180;
> >>>>> -
> >>>>> -     /* 180 phase tx clock */
> >>>>> -     meson_mmc_clk |= CLK_TX_PHASE_000;
> >>>>> +     /* Clock divider */
> >>>>> +     meson_mmc_clk |= CLK_DIV_MASK;
> >>>>
> >>>> This will set the max divider, whatever the value of clk_div, so the following statement:
> >>>> meson_mmc_clk |= clk_div;
> >>>> will have no effect.
> >>>
> >>> As per the datasheet S905 and S922X max divider is 63.
> >>> CLK_DIV_MASK[0-5]      Cfg_div: Clock divider
> >>>                                         Frequency = clock source/cfg_div
> >>>                                         Clock off: cfg_div==0, the
> >>> clock is disabled
> >>>                                         Divider bypass: cfg_div==1,
> >>> clock source is used as core clock without divider
> >>>                                         Maximum divider 63
> >>>
> >>> So here is the log of clk_div and clk_freq at my end.
> >>>
> >>> MMC Device 0 not found
> >>> no mmc device at slot 0
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> Card did not respond to voltage select!
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> clock is enabled (25000000Hz)
> >>> ......clk_div : 40
> >>> ......clk_div : 40
> >>> clock is enabled (52000000Hz)
> >>> ......clk_div : 20
> >>> switch to partitions #0, OK
> >>> mmc2(part 0) is current device
> >>> Scanning mmc 2:1...
> >>> Found U-Boot script /boot/boot.scr
> >>
> >>
> >> OK, seems you didn't see the issue.
> >>
> >> With the original code, let's say mmc->clock = 25000000
> >>
> >> clk = SD_EMMC_CLKSRC_DIV2
> >> clk_src = CLK_SRC_DIV2
> >> clk_div = 40
> >>
> >> meson_mmc_clk |= CLK_CO_PHASE_180;
> >> meson_mmc_clk |= CLK_TX_PHASE_000;
> >> meson_mmc_clk |= CLK_SRC_DIV2;
> >> meson_mmc_clk |= 40;
> >>
> >> => meson_mmc_clk = (2 << 8) | (0 << 10) | (1 << 6) | 40
> >> => meson_mmc_clk = 0x268
> >>
> >> With your code :
> >> meson_mmc_clk |= CLK_DIV_MASK;
> >> meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >> meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> >> meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
> >> meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >> meson_mmc_clk |= CLK_SRC_DIV2;
> >> meson_mmc_clk |= 40;
> >>
> >> => meson_mmc_clk = 0x3f | (0 << 6) | (2 << 8) | (0 << 11) | (0 << 13) | (1 << 6) | 40
> >>
> >> -------------------/\---this---------makes-------this-----useless------------------/\
> >>
> >> => 0x27f
> >>
> >> It sets the clock to 15873015Hz instead of the 25000000Hz requested.
> >
> > I did not observer this at my end, but any way thanks for the input.
> >
> >>
> >> so this code sets max divider whatever mmc->clock value, but keeps the CRYSTAL_24MHZ/CLK_SRC_DIV2 selection.
> >>
> >>>
> >>>>
> >>>>
> >>>>> +     /* Clock source : Crystal 24MHz */
> >>>>> +     meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >>>>
> >>>> You set CRYSTAL_24MHZ here, but the src is selected in clk_src and set with:
> >>>> meson_mmc_clk |= clk_src;
> >>>>
> >>>> In conclusion your change forces the 24MHz crystal and max divider whatever the
> >>>> freq asked by the mmc core !
> >>>>
> >>> As per the datasheet S905 and S922X
> >>> Cfg_src:             Clock source
> >>>                           0: Crystal 24MHz or other frequencies
> >>> selected by clock reset test control register.
> >>>                           1: Fix PLL, 1000MHz
> >>>                           Recommended value: 1
> >>>
> >>> Note: *setting cfg_src value to I       i.e; Fix PLL 1000 Mhz *
> >>> some how break the clk_freq tuning setting in my testing,
> >>> see the logs below.
> >>>
> >>> MMC Device 0 not found
> >>> no mmc device at slot 0
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> Card did not respond to voltage select!
> >>> clock is disabled (0Hz)
> >>> clock is enabled (380953Hz)
> >>> ......clk_div : 63
> >>> starting USB...
> >>>
> >>> No emmc will get discovered,
> >>> *This is the real issue I faced for failure of eMMC not getting detected.*
> >>
> >> This is the issue I get on SM1, but when I cap the max freq to 24MHz, it disappears.
> >>
> >> This issue is somewhere else, but I don't know where because the Linux driver behaves
> >> correctly with the same setup.
> >>
> >> My fix was to always use the 24MHz crystal input on non-GX until we find out why, and it still acceptable.
> >
> > I have studied amlogic u-boot and it seen to use 24MHz crystal inputs.
> > I have following fix the issue with select  Fix PLL and CRYSTAL24MHz
> >        if (mmc->clock > 400000) {
> >                /* Clock source : Fix PLL, 1000MHz */
> >                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, FIXPLL_10000MHZ);
> >        } else {
> >                /* Clock source : Crystal 24MHz */
> >                meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >        }
>
> This is still wrong and broken. The original code is correct and works fine.
>
> As Jerome said, the underlying issue must be understood, why when using the FIXPLL clock source, it fails ?
>
> The clock setup function is correct, don't try to fix it.
>
> The weirdness is why does it works under linux ? maybe the fixpll clock setup is different ?
>
> Could you dump the emmc and clock registers from linux to see the difference ?
>
> Neil
>

Ok thanks for this Input. I will try to figure our how it's working in
linux kernel first.

-Anand

> >>
> >> Could you post instead :
> >> - your patch 2 introducing the MMC_COMPATIBLE_* as patch 1
> >
> > Ok I will change the order.
> >
> >> - this patch but only forcing 24MHz for MMC_COMPATIBLE_AXG as patch 2
> >
> > I propose the dynamically select 24MHz and Fix PLL, as above code.
> >
> >> - redude patches 3,4 & 5 to only add mmc* aliases into meson-gx-u-boot.dtsi/meson-g12-common-u-boot.dtsi
> >>
> >
> > Ok I will make these changes
> >
> >> If you have a issue, please chat with me on #linux-amlogic on freenode.
> >
> > I could not connect to freenode or register my self to this chat
> > group. sorry about that.
> >
> >>
> >> Thanks,
> >> Neil
> >>
> >
> > -Anand
> >
>

^ permalink raw reply	[flat|nested] 48+ messages in thread

end of thread, other threads:[~2020-02-13 16:41 UTC | newest]

Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-09 11:05 [PATCHv6 0/5] Odroid n2 using eMMC would fail to boot up Anand Moon
2020-02-09 11:05 ` Anand Moon
2020-02-09 11:05 ` [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC Anand Moon
2020-02-09 11:05   ` Anand Moon
2020-02-09 13:08   ` Neil Armstrong
2020-02-09 13:08     ` Neil Armstrong
2020-02-09 17:22     ` Anand Moon
2020-02-09 17:22       ` Anand Moon
2020-02-10  9:03       ` Neil Armstrong
2020-02-10  9:03         ` Neil Armstrong
2020-02-13 11:58         ` Anand Moon
2020-02-13 11:58           ` Anand Moon
2020-02-13 15:39           ` Neil Armstrong
2020-02-13 15:39             ` Neil Armstrong
2020-02-13 16:41             ` Anand Moon
2020-02-13 16:41               ` Anand Moon
2020-02-10  9:35       ` Jerome Brunet
2020-02-10  9:35         ` Jerome Brunet
2020-02-13 12:04         ` Anand Moon
2020-02-13 12:04           ` Anand Moon
2020-02-09 11:05 ` [PATCHv6 2/5] mmc: meson-gx: Use proper compatible string as per the dts Anand Moon
2020-02-09 11:05   ` Anand Moon
2020-02-09 13:01   ` Neil Armstrong
2020-02-09 13:01     ` Neil Armstrong
2020-02-09 17:23     ` Anand Moon
2020-02-09 17:23       ` Anand Moon
2020-02-10  8:26       ` Neil Armstrong
2020-02-10  8:26         ` Neil Armstrong
2020-02-09 11:05 ` [PATCHv6 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi Anand Moon
2020-02-09 11:05   ` Anand Moon
2020-02-09 12:58   ` Neil Armstrong
2020-02-09 12:58     ` Neil Armstrong
2020-02-09 17:25     ` Anand Moon
2020-02-09 17:25       ` Anand Moon
2020-02-10  8:24       ` Neil Armstrong
2020-02-10  8:24         ` Neil Armstrong
2020-02-09 11:05 ` [PATCHv6 4/5] arm: dts: g12: " Anand Moon
2020-02-09 11:05   ` Anand Moon
2020-02-09 12:58   ` Neil Armstrong
2020-02-09 12:58     ` Neil Armstrong
2020-02-09 17:25     ` Anand Moon
2020-02-09 17:25       ` Anand Moon
2020-02-09 11:05 ` [PATCHv6 5/5] arm: dts: s400: " Anand Moon
2020-02-09 11:05   ` Anand Moon
2020-02-09 12:58   ` Neil Armstrong
2020-02-09 12:58     ` Neil Armstrong
2020-02-09 17:24     ` Anand Moon
2020-02-09 17:24       ` Anand Moon

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