From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C4E2C3F68F for ; Thu, 13 Feb 2020 16:09:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED40724649 for ; Thu, 13 Feb 2020 16:09:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581610152; bh=+RxjQhRoBpM0ZRuPEJ4OTJMFlyjir8IlfSTJLp61wZ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=UmVjpnGoZdNm+Wp18TkSB1Q5i5ie9Ld5Y6dCTF/uUN1vHsgUfw1WycJWkl8oh3yMs bEtTQOWRTPjNeC89N3Du4I1IY8o+erQSrS3m64q/FzSrksk54uvkOUaE6QY6ICPy3P cdTrDtBrcsGan72o96hhmgS9ULch8bvLWoJ+tk1k= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728395AbgBMQJK (ORCPT ); Thu, 13 Feb 2020 11:09:10 -0500 Received: from mail.kernel.org ([198.145.29.99]:60968 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728148AbgBMPWu (ORCPT ); Thu, 13 Feb 2020 10:22:50 -0500 Received: from localhost (unknown [104.132.1.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1C46B2469C; Thu, 13 Feb 2020 15:22:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581607368; bh=+RxjQhRoBpM0ZRuPEJ4OTJMFlyjir8IlfSTJLp61wZ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vQwyshjzjK4/xrGHwhWtoa+Dakn15X228up/tTbW/8CWDvuNaDHBtyHDc0yEA781z Pr6rrVg7WTVRaig0j2+9wCpKKzPUdKJCYsOtoMt4hRYyMRfqhTJ9jlRnWchnraM2h8 zAjKUP1sKSrZ8ybVqC5P8c4CPtY1jbPiZr6VWjo4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Nick Finco , Marios Pomonis , Andrew Honig , Jim Mattson , Paolo Bonzini Subject: [PATCH 4.4 41/91] KVM: x86: Protect MSR-based index computations from Spectre-v1/L1TF attacks in x86.c Date: Thu, 13 Feb 2020 07:19:58 -0800 Message-Id: <20200213151837.499087300@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200213151821.384445454@linuxfoundation.org> References: <20200213151821.384445454@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marios Pomonis commit 6ec4c5eee1750d5d17951c4e1960d953376a0dda upstream. This fixes a Spectre-v1/L1TF vulnerability in set_msr_mce() and get_msr_mce(). Both functions contain index computations based on the (attacker-controlled) MSR number. Fixes: 890ca9aefa78 ("KVM: Add MCE support") Signed-off-by: Nick Finco Signed-off-by: Marios Pomonis Reviewed-by: Andrew Honig Cc: stable@vger.kernel.org Reviewed-by: Jim Mattson Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/x86.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1994,7 +1994,10 @@ static int set_msr_mce(struct kvm_vcpu * default: if (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(bank_num)) { - u32 offset = msr - MSR_IA32_MC0_CTL; + u32 offset = array_index_nospec( + msr - MSR_IA32_MC0_CTL, + MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); + /* only 0 or all 1s can be written to IA32_MCi_CTL * some Linux kernels though clear bit 10 in bank 4 to * workaround a BIOS/GART TBL issue on AMD K8s, ignore @@ -2355,7 +2358,10 @@ static int get_msr_mce(struct kvm_vcpu * default: if (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(bank_num)) { - u32 offset = msr - MSR_IA32_MC0_CTL; + u32 offset = array_index_nospec( + msr - MSR_IA32_MC0_CTL, + MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); + data = vcpu->arch.mce_banks[offset]; break; }