From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF7ECC7619B for ; Mon, 17 Feb 2020 06:43:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8A3F6206F4 for ; Mon, 17 Feb 2020 06:43:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="cJWsfnoi"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="LyQtsjJ6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727739AbgBQGnR (ORCPT ); Mon, 17 Feb 2020 01:43:17 -0500 Received: from new2-smtp.messagingengine.com ([66.111.4.224]:32939 "EHLO new2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727291AbgBQGnG (ORCPT ); Mon, 17 Feb 2020 01:43:06 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailnew.nyi.internal (Postfix) with ESMTP id 106B451E1; Mon, 17 Feb 2020 01:43:06 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 17 Feb 2020 01:43:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=kKzb1Qj4ZHVK4 pTJQ0r23qGMmMSqQTfk8t4pDT3gnm0=; b=cJWsfnoin1B+Wo5944BqdmNssv+vU DfB4yaL80OtxjshXQIj/pYnXlv4YhOFvmJQJX9qdTcUUZ2ci51bsKMGbo2e//seH C6YDFGG1Jw1KQZacmGyJaMP8ysrV6pa/ELT/KqTXE8v5dgQNv+RhM458T3lybPKT tplH+XNWjzJzVERzw4tvuv/q8TvHg1ogx4grGPIipXXRgBNw6IQ9uDJt7w6zUdmo V9n6Utcyw+doW9smfbk/O+pAF4LRqflAOkRem2biaJaRbPu2T6KR5BqlSoY67Srb T0z260YGHJhUFPWN0hl3Q8rVPJ+zrcm4UnGmlJYLbP0FuiUqFkimUytig== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=kKzb1Qj4ZHVK4pTJQ0r23qGMmMSqQTfk8t4pDT3gnm0=; b=LyQtsjJ6 GPG/D7mcDBh3Ys3IPzNYou16MFyR1pyBqSXcuPpEwXpDU6XyCgmZGJ5AtnSfFcOh ya94U0vDdc0+L+g3AFapP53yajvMoNK2R4LqiFliOPI5CnN60A3uYvKeKMpfKVXh SyZHItJ6LoUH93ajxgkCGleHC7SV49BH/mSZzpgHXy5JXBtvUFo6VS2AoEbL0FON Tmc6gtG8/6FMQEb6Lg7JIP2O3wCOOI8b5wrHopvwt5ykdWrawp6vVuXU0r78c5FK DHam2JAsuZrhpwvjAqC8Gbhif7SXNurvOa/xDuLxykzMz4E46OcI1GtkGGVNu9Ac wwaqOvkBskAj7A== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedugedrjeehgdelkecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhuvghl ucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecukfhppe ejtddrudefhedrudegkedrudehudenucevlhhushhtvghrufhiiigvpedujeenucfrrghr rghmpehmrghilhhfrhhomhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id 507D9328005A; Mon, 17 Feb 2020 01:43:05 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?UTF-8?q?Myl=C3=A8ne=20Josserand?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 24/34] ASoC: sun8i-codec: Prepare to support multiple AIFs Date: Mon, 17 Feb 2020 00:42:40 -0600 Message-Id: <20200217064250.15516-25-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clock control registers for AIF1 and AIF2 have an identical layout (other than the unused bit 0 for TDM mode). Rename the offsets/masks to signify that they are shared between AIFs, and get the register address from the AIF ID (this requires filling in the AIF ID). We also need to rename the DAI and DAI streams, so they are still unique once AIF2 is added. Finally, we convert the AIF driver struct to an array. Since this already breaks `git blame`, we clean it up a bit by moving it and the DAI ops up near the DAI driver implementation; this stops the ASoC DAPM component driver splitting the DAI driver in half. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 159 +++++++++++++++++----------------- 1 file changed, 80 insertions(+), 79 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 5dfaf656b5b1..aaea9aaa5632 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -38,16 +38,15 @@ #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 -#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 -#define SUN8I_SYS_SR_CTRL_AIF2_FS 8 -#define SUN8I_AIF1CLK_CTRL 0x040 -#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 -#define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 +#define SUN8I_SYS_SR_CTRL_AIF_FS(n) (16 - 4 * (n)) +#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (n)) +#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 +#define SUN8I_AIF_CLK_CTRL_CLK_INV 13 +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 +#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 +#define SUN8I_AIF_CLK_CTRL_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -80,13 +79,12 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) -#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) -#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_SYS_SR_CTRL_AIF_FS_MASK(n) (GENMASK(19, 16) >> (4 * (n))) +#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -189,6 +187,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value; /* clock masters */ @@ -202,9 +201,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), - value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -234,9 +233,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) * invert the value here. */ value ^= scodec->inverted_lrck; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, + value << SUN8I_AIF_CLK_CTRL_CLK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -255,9 +254,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT); return 0; } @@ -327,23 +326,24 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); int sample_rate, lrck_div; u8 bclk_div; u32 value; bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), channels, slot_width); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); switch (params_width(params)) { case 8: @@ -361,29 +361,60 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, + value << SUN8I_AIF_CLK_CTRL_WORD_SIZ); value = channels == 1; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), - value << SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM); sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate; regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); return 0; } +static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { + .hw_params = sun8i_codec_hw_params, + .set_fmt = sun8i_set_fmt, +}; + +static struct snd_soc_dai_driver sun8i_codec_dais[] = { + { + .name = "sun8i-codec-aif1", + .id = 1, + /* playback capabilities */ + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, +}; + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -424,10 +455,10 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "Capture", 1, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), @@ -438,10 +469,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { sun8i_aif1_ad0_mixer_controls), /* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "Playback", 1, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), @@ -565,37 +596,6 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return 0; } -static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { - .hw_params = sun8i_codec_hw_params, - .set_fmt = sun8i_set_fmt, -}; - -static struct snd_soc_dai_driver sun8i_codec_dai = { - .name = "sun8i", - /* playback capabilities */ - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - }, - /* capture capabilities */ - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - .sig_bits = 24, - }, - /* pcm operations */ - .ops = &sun8i_codec_dai_ops, - .symmetric_rates = 1, - .symmetric_channels = 1, - .symmetric_samplebits = 1, -}; - static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), @@ -664,7 +664,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) } ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, - &sun8i_codec_dai, 1); + sun8i_codec_dais, + ARRAY_SIZE(sun8i_codec_dais)); if (ret) { dev_err(&pdev->dev, "Failed to register codec\n"); goto err_suspend; -- 2.24.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ACBCC7619B for ; Mon, 17 Feb 2020 06:58:15 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD80D20679 for ; Mon, 17 Feb 2020 06:58:14 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 17 Feb 2020 01:43:05 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?UTF-8?q?Myl=C3=A8ne=20Josserand?= , Jaroslav Kysela , Takashi Iwai Date: Mon, 17 Feb 2020 00:42:40 -0600 Message-Id: <20200217064250.15516-25-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [alsa-devel] [RFC PATCH 24/34] ASoC: sun8i-codec: Prepare to support multiple AIFs X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The clock control registers for AIF1 and AIF2 have an identical layout (other than the unused bit 0 for TDM mode). Rename the offsets/masks to signify that they are shared between AIFs, and get the register address from the AIF ID (this requires filling in the AIF ID). We also need to rename the DAI and DAI streams, so they are still unique once AIF2 is added. Finally, we convert the AIF driver struct to an array. Since this already breaks `git blame`, we clean it up a bit by moving it and the DAI ops up near the DAI driver implementation; this stops the ASoC DAPM component driver splitting the DAI driver in half. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 159 +++++++++++++++++----------------- 1 file changed, 80 insertions(+), 79 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 5dfaf656b5b1..aaea9aaa5632 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -38,16 +38,15 @@ #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 -#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 -#define SUN8I_SYS_SR_CTRL_AIF2_FS 8 -#define SUN8I_AIF1CLK_CTRL 0x040 -#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 -#define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 +#define SUN8I_SYS_SR_CTRL_AIF_FS(n) (16 - 4 * (n)) +#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (n)) +#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 +#define SUN8I_AIF_CLK_CTRL_CLK_INV 13 +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 +#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 +#define SUN8I_AIF_CLK_CTRL_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -80,13 +79,12 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) -#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) -#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_SYS_SR_CTRL_AIF_FS_MASK(n) (GENMASK(19, 16) >> (4 * (n))) +#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -189,6 +187,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value; /* clock masters */ @@ -202,9 +201,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), - value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -234,9 +233,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) * invert the value here. */ value ^= scodec->inverted_lrck; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, + value << SUN8I_AIF_CLK_CTRL_CLK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -255,9 +254,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT); return 0; } @@ -327,23 +326,24 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); int sample_rate, lrck_div; u8 bclk_div; u32 value; bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), channels, slot_width); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); switch (params_width(params)) { case 8: @@ -361,29 +361,60 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, + value << SUN8I_AIF_CLK_CTRL_WORD_SIZ); value = channels == 1; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), - value << SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM); sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate; regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); return 0; } +static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { + .hw_params = sun8i_codec_hw_params, + .set_fmt = sun8i_set_fmt, +}; + +static struct snd_soc_dai_driver sun8i_codec_dais[] = { + { + .name = "sun8i-codec-aif1", + .id = 1, + /* playback capabilities */ + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, +}; + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -424,10 +455,10 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "Capture", 1, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), @@ -438,10 +469,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { sun8i_aif1_ad0_mixer_controls), /* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "Playback", 1, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), @@ -565,37 +596,6 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return 0; } -static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { - .hw_params = sun8i_codec_hw_params, - .set_fmt = sun8i_set_fmt, -}; - -static struct snd_soc_dai_driver sun8i_codec_dai = { - .name = "sun8i", - /* playback capabilities */ - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - }, - /* capture capabilities */ - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - .sig_bits = 24, - }, - /* pcm operations */ - .ops = &sun8i_codec_dai_ops, - .symmetric_rates = 1, - .symmetric_channels = 1, - .symmetric_samplebits = 1, -}; - static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), @@ -664,7 +664,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) } ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, - &sun8i_codec_dai, 1); + sun8i_codec_dais, + ARRAY_SIZE(sun8i_codec_dais)); if (ret) { dev_err(&pdev->dev, "Failed to register codec\n"); goto err_suspend; -- 2.24.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F08D4C7619D for ; Mon, 17 Feb 2020 06:51:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B20402070B for ; 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Mon, 17 Feb 2020 01:43:05 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?UTF-8?q?Myl=C3=A8ne=20Josserand?= , Jaroslav Kysela , Takashi Iwai Subject: [RFC PATCH 24/34] ASoC: sun8i-codec: Prepare to support multiple AIFs Date: Mon, 17 Feb 2020 00:42:40 -0600 Message-Id: <20200217064250.15516-25-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200216_224307_681795_1CBB1067 X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org The clock control registers for AIF1 and AIF2 have an identical layout (other than the unused bit 0 for TDM mode). Rename the offsets/masks to signify that they are shared between AIFs, and get the register address from the AIF ID (this requires filling in the AIF ID). We also need to rename the DAI and DAI streams, so they are still unique once AIF2 is added. Finally, we convert the AIF driver struct to an array. Since this already breaks `git blame`, we clean it up a bit by moving it and the DAI ops up near the DAI driver implementation; this stops the ASoC DAPM component driver splitting the DAI driver in half. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 159 +++++++++++++++++----------------- 1 file changed, 80 insertions(+), 79 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 5dfaf656b5b1..aaea9aaa5632 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -38,16 +38,15 @@ #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 -#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 -#define SUN8I_SYS_SR_CTRL_AIF2_FS 8 -#define SUN8I_AIF1CLK_CTRL 0x040 -#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 -#define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 +#define SUN8I_SYS_SR_CTRL_AIF_FS(n) (16 - 4 * (n)) +#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (n)) +#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 +#define SUN8I_AIF_CLK_CTRL_CLK_INV 13 +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 +#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 +#define SUN8I_AIF_CLK_CTRL_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -80,13 +79,12 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) -#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) -#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_SYS_SR_CTRL_AIF_FS_MASK(n) (GENMASK(19, 16) >> (4 * (n))) +#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -189,6 +187,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value; /* clock masters */ @@ -202,9 +201,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), - value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -234,9 +233,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) * invert the value here. */ value ^= scodec->inverted_lrck; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, + value << SUN8I_AIF_CLK_CTRL_CLK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -255,9 +254,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT); return 0; } @@ -327,23 +326,24 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); int sample_rate, lrck_div; u8 bclk_div; u32 value; bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), channels, slot_width); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); switch (params_width(params)) { case 8: @@ -361,29 +361,60 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, + value << SUN8I_AIF_CLK_CTRL_WORD_SIZ); value = channels == 1; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), - value << SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM); sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate; regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); return 0; } +static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { + .hw_params = sun8i_codec_hw_params, + .set_fmt = sun8i_set_fmt, +}; + +static struct snd_soc_dai_driver sun8i_codec_dais[] = { + { + .name = "sun8i-codec-aif1", + .id = 1, + /* playback capabilities */ + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, +}; + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -424,10 +455,10 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "Capture", 1, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), @@ -438,10 +469,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { sun8i_aif1_ad0_mixer_controls), /* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "Playback", 1, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), @@ -565,37 +596,6 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return 0; } -static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { - .hw_params = sun8i_codec_hw_params, - .set_fmt = sun8i_set_fmt, -}; - -static struct snd_soc_dai_driver sun8i_codec_dai = { - .name = "sun8i", - /* playback capabilities */ - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - }, - /* capture capabilities */ - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - .sig_bits = 24, - }, - /* pcm operations */ - .ops = &sun8i_codec_dai_ops, - .symmetric_rates = 1, - .symmetric_channels = 1, - .symmetric_samplebits = 1, -}; - static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), @@ -664,7 +664,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) } ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, - &sun8i_codec_dai, 1); + sun8i_codec_dais, + ARRAY_SIZE(sun8i_codec_dais)); if (ret) { dev_err(&pdev->dev, "Failed to register codec\n"); goto err_suspend; -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel