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From: David Miller <davem@davemloft.net>
To: alexandre.belloni@bootlin.com
Cc: nicolas.ferre@microchip.com, linux@armlinux.org.uk,
	antoine.tenart@bootlin.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net v2] net: macb: Properly handle phylink on at91rm9200
Date: Thu, 20 Feb 2020 15:00:51 -0800 (PST)	[thread overview]
Message-ID: <20200220.150051.2170993471455503146.davem@davemloft.net> (raw)
In-Reply-To: <20200219141551.5152-1-alexandre.belloni@bootlin.com>

From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Date: Wed, 19 Feb 2020 15:15:51 +0100

> at91ether_init was handling the phy mode and speed but since the switch to
> phylink, the NCFGR register got overwritten by macb_mac_config(). The issue
> is that the RM9200_RMII bit and the MACB_CLK_DIV32 field are cleared
> but never restored as they conflict with the PAE, GBE and PCSSEL bits.
> 
> Add new capability to differentiate between EMAC and the other versions of
> the IP and use it to set and avoid clearing the relevant bits.
> 
> Also, this fixes a NULL pointer dereference in macb_mac_link_up as the EMAC
> doesn't use any rings/bufffers/queues.
> 
> Fixes: 7897b071ac3b ("net: macb: convert to phylink")
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

Applied and queued up for -stable, thanks.

      parent reply	other threads:[~2020-02-20 23:00 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-19 14:15 [PATCH net v2] net: macb: Properly handle phylink on at91rm9200 Alexandre Belloni
2020-02-19 14:27 ` Alexandre Belloni
2020-02-20 23:00 ` David Miller [this message]

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