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From: Matthias Kaehlcke <mka@chromium.org>
To: Akash Asthana <akashast@codeaurora.org>
Cc: gregkh@linuxfoundation.org, agross@kernel.org,
	bjorn.andersson@linaro.org, wsa@the-dreams.de,
	broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
	linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, swboyd@chromium.org,
	mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
	linux-serial@vger.kernel.org, dianders@chromium.org
Subject: Re: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support
Date: Thu, 20 Feb 2020 16:24:00 -0800	[thread overview]
Message-ID: <20200221002400.GD24720@google.com> (raw)
In-Reply-To: <84a7d97a-4e10-5509-9c87-af8a545c7385@codeaurora.org>

Hi Akash,

On Wed, Feb 19, 2020 at 07:17:44PM +0530, Akash Asthana wrote:
> Hi Matthias,
> 
> On 2/19/2020 4:17 AM, Matthias Kaehlcke wrote:
> > On Mon, Feb 17, 2020 at 07:00:02PM +0530, Akash Asthana wrote:
> > > Get the interconnect paths for I2C based Serial Engine device
> > > and vote according to the bus speed of the driver.
> > > 
> > > Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> > > ---
> > >   drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
> > >   1 file changed, 80 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> > > index 17abf60c..5de10a1 100644
> > > --- a/drivers/i2c/busses/i2c-qcom-geni.c
> > > +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> > >
> > >   static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
> > >   {
> > >   	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
> > > @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
> > >   	gi2c->adap.dev.of_node = pdev->dev.of_node;
> > >   	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
> > > +	ret = geni_i2c_icc_get(&gi2c->se);
> > > +	if (ret)
> > > +		return ret;
> > > +	/* Set the bus quota to a reasonable value */
> > > +	gi2c->se.avg_bw_core = Bps_to_icc(1000);
> > > +	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
> > > +	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
> > > +	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
> > > +	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
> > > +	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
> > > +
> > > +	/* Vote for core clocks and CPU for register access */
> > > +	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
> > > +				gi2c->se.peak_bw_core);
> > > +	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
> > > +				gi2c->se.peak_bw_cpu);
> > error handling needed?
> 
> I will add error handling for GENI_TO_CORE path in all the drivers. Will it
> be okay if we don't handle errors for CPU_TO_GENI and GENI_TO_DDR path
> 
> as CPU and DDR will be running at much higher frequency?

It may still work, but you might never know that there was a problem. I
would be inclined to check the return value of all invocations of icc_set_bw()
- including runtime suspend/resume - and log a message if a problem is
detected. For runtime suspend/resume it would probably be wise to use
dev_err_ratelimited(), to avoid spamming the system log too much in case of
a persistent problem.

If others think that error checking all icc_set_bw() calls is overkill
please speak up :)

Thanks

Matthias

  reply	other threads:[~2020-02-21  0:24 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-17 13:29 [PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI Akash Asthana
2020-02-17 13:29 ` Akash Asthana
2020-02-17 13:30 ` [PATCH 1/6] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-02-17 13:30   ` Akash Asthana
2020-02-18  3:03   ` Bjorn Andersson
2020-02-19 13:25     ` Akash Asthana
2020-02-17 13:30 ` [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support Akash Asthana
2020-02-17 13:30   ` Akash Asthana
2020-02-17 16:00   ` Greg KH
2020-02-18  3:15   ` Bjorn Andersson
2020-02-18  3:15     ` Bjorn Andersson
2020-02-19 13:28     ` Akash Asthana
2020-02-18 22:34   ` Matthias Kaehlcke
2020-02-19 13:31     ` Akash Asthana
2020-02-17 13:30 ` [PATCH 3/6] i2c: i2c-qcom-geni: " Akash Asthana
2020-02-17 13:30   ` Akash Asthana
2020-02-18 22:47   ` Matthias Kaehlcke
2020-02-18 22:47     ` Matthias Kaehlcke
2020-02-19 13:47     ` Akash Asthana
2020-02-21  0:24       ` Matthias Kaehlcke [this message]
2020-02-17 13:30 ` [PATCH 4/6] spi: spi-geni-qcom: " Akash Asthana
2020-02-17 16:31   ` Mark Brown
2020-02-17 16:31     ` Mark Brown
2020-02-19 18:09   ` Matthias Kaehlcke
2020-02-21 18:55     ` Matthias Kaehlcke
2020-02-21 18:55       ` Matthias Kaehlcke
2020-02-17 13:30 ` [PATCH 5/6] spi: spi-qcom-qspi: " Akash Asthana
2020-02-17 16:35   ` Mark Brown
2020-02-17 13:30 ` [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
2020-02-18  3:18   ` Bjorn Andersson
2020-02-19 13:49     ` Akash Asthana
2020-02-27 12:11   ` Amit Kucheria
2020-02-27 12:11     ` Amit Kucheria
2020-02-27 17:03     ` Matthias Kaehlcke
2020-02-27 17:03       ` Matthias Kaehlcke
2020-03-09 17:59 ` [PATCH 0/6] Add interconnect support to UART, I2C, SPI " Matthias Kaehlcke
2020-03-09 17:59   ` Matthias Kaehlcke
2020-03-11 13:02   ` Akash Asthana
  -- strict thread matches above, loose matches on Subject: below --
2019-01-22  6:33 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
2019-01-22  6:33 ` [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Alok Chauhan
2019-01-22  9:07   ` Wolfram Sang
2019-01-22  9:13   ` Peter Rosin
2019-01-23  6:51     ` alokc
2019-01-24  1:19   ` Evan Green
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
2019-01-21 11:21 ` [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Alok Chauhan
2019-01-22  6:54   ` alokc

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