* [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM
@ 2020-02-21 6:35 Yubo Miao
2020-02-21 6:35 ` [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Yubo Miao
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Yubo Miao @ 2020-02-21 6:35 UTC (permalink / raw)
To: peter.maydell, shannon.zhaosl
Cc: imammedo, miaoyubo, qemu-devel, xiexiangyou, mst
From: miaoyubo <miaoyubo@huawei.com>
Currently pxb-pcie is not supported by arm, the reason for it is
pxb-pcie is not described in DSDT table and only one main host bridge
is described in acpi tables, which means it is not impossible to
present different io numas for different devices, especially
host-passthrough devices.
This series of patches make arm to support PXB-PCIE.
Users can configure pxb-pcie with certain numa, Example command
is:
-device pxb-pcie,id=pci.7,bus_nr=128,numa_node=0,bus=pcie.0,addr=0x9
Since the bus of pxb-pcie is root bus, devices could not be plugged
into pxb-pcie directly,pcie-root-port or pci-bridge should be defined
and plugged on pxb-pcie, then the device could be plugged onto the
pcie-root-port or pci-bridge.
With the patches,io numa could be presented to the guest by define a
pxb-pcie with the numa and plug the device on it.
miaoyubo (3):
acpi:Extract two APIs from acpi_dsdt_add_pci
acpi:pci-expender-bus: Add pxb support for arm
ACPI/unit-test: Add a new test for pxb-pcie for arm
hw/arm/virt-acpi-build.c | 240 ++++++++++++++++++++++++---------
hw/pci-host/gpex.c | 4 +
include/hw/arm/virt.h | 7 +
tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes
tests/qtest/bios-tables-test.c | 54 +++++++-
5 files changed, 238 insertions(+), 67 deletions(-)
create mode 100644 tests/data/acpi/virt/DSDT.pxb
--
2.19.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci
2020-02-21 6:35 [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
@ 2020-02-21 6:35 ` Yubo Miao
2020-02-21 6:35 ` [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Yubo Miao
2020-02-21 6:35 ` [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie " Yubo Miao
2 siblings, 0 replies; 9+ messages in thread
From: Yubo Miao @ 2020-02-21 6:35 UTC (permalink / raw)
To: peter.maydell, shannon.zhaosl
Cc: imammedo, miaoyubo, qemu-devel, xiexiangyou, mst
From: miaoyubo <miaoyubo@huawei.com>
Extract two APIs acpi_dsdt_add_pci_route_table and
acpi_dsdt_add_pci_osc form acpi_dsdt_add_pci. The first
API is used to specify the pci route table and the second
API is used to declare the operation system capabilities.
These two APIs would be used to specify the pxb-pcie in DSDT.
Signed-off-by: miaoyubo <miaoyubo@huawei.com>
---
hw/arm/virt-acpi-build.c | 135 ++++++++++++++++++++++-----------------
1 file changed, 75 insertions(+), 60 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index bd5f771e9b..0540234b8a 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -151,30 +151,12 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
-static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
- uint32_t irq, bool use_highmem, bool highmem_ecam)
+static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope,
+ int nr_pcie_buses,
+ uint32_t irq)
{
- int ecam_id = VIRT_ECAM_ID(highmem_ecam);
- Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
int i, bus_no;
- hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
- hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
- hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
- hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
- hwaddr base_ecam = memmap[ecam_id].base;
- hwaddr size_ecam = memmap[ecam_id].size;
- int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
-
- Aml *dev = aml_device("%s", "PCI0");
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
- aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
- aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
- aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
- aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
- aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
- aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
+ Aml *method, *crs;
/* Declare the PCI Routing Table. */
Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
@@ -190,7 +172,6 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
}
aml_append(dev, aml_name_decl("_PRT", rt_pkg));
- /* Create GSI link device */
for (i = 0; i < PCI_NUM_PINS; i++) {
uint32_t irqs = irq + i;
Aml *dev_gsi = aml_device("GSI%d", i);
@@ -210,42 +191,11 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
aml_append(dev_gsi, method);
aml_append(dev, dev_gsi);
}
+}
- method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(base_ecam)));
- aml_append(dev, method);
-
- method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
- Aml *rbuf = aml_resource_template();
- aml_append(rbuf,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
- nr_pcie_buses));
- aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
- base_mmio + size_mmio - 1, 0x0000, size_mmio));
- aml_append(rbuf,
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
- size_pio));
-
- if (use_highmem) {
- hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
- hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
-
- aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- base_mmio_high,
- base_mmio_high + size_mmio_high - 1, 0x0000,
- size_mmio_high));
- }
-
- aml_append(method, aml_name_decl("RBUF", rbuf));
- aml_append(method, aml_return(rbuf));
- aml_append(dev, method);
-
+static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
+{
+ Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
/* Declare an _OSC (OS Control Handoff) method */
aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
@@ -253,7 +203,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
aml_append(method,
aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
- /* PCI Firmware Specification 3.0
+ /*
+ * PCI Firmware Specification 3.0
* 4.5.1. _OSC Interface for PCI Host Bridge Devices
* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
* identified by the Universal Unique IDentifier (UUID)
@@ -298,7 +249,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
- /* PCI Firmware Specification 3.0
+ /*
+ * PCI Firmware Specification 3.0
* 4.6.1. _DSM for PCI Express Slot Information
* The UUID in _DSM in this context is
* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
@@ -316,6 +268,69 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
buf = aml_buffer(1, byte_list);
aml_append(method, aml_return(buf));
aml_append(dev, method);
+}
+
+static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
+ uint32_t irq, bool use_highmem, bool highmem_ecam)
+{
+ int ecam_id = VIRT_ECAM_ID(highmem_ecam);
+ Aml *method, *crs;
+ hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
+ hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
+ hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
+ hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
+ hwaddr base_ecam = memmap[ecam_id].base;
+ hwaddr size_ecam = memmap[ecam_id].size;
+ int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
+
+ Aml *dev = aml_device("%s", "PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
+ aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+ acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq);
+
+ method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(base_ecam)));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ Aml *rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
+ nr_pcie_buses));
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
+ base_mmio + size_mmio - 1, 0x0000, size_mmio));
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
+ size_pio));
+
+ if (use_highmem) {
+ hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
+ hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
+
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ base_mmio_high,
+ base_mmio_high + size_mmio_high - 1, 0x0000,
+ size_mmio_high));
+ }
+
+ aml_append(method, aml_name_decl("RBUF", rbuf));
+ aml_append(method, aml_return(rbuf));
+ aml_append(dev, method);
+
+ acpi_dsdt_add_pci_osc(dev, scope);
Aml *dev_rp0 = aml_device("%s", "RP0");
aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
--
2.19.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
2020-02-21 6:35 [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
2020-02-21 6:35 ` [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Yubo Miao
@ 2020-02-21 6:35 ` Yubo Miao
2020-02-21 11:17 ` Michael S. Tsirkin
2020-02-21 6:35 ` [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie " Yubo Miao
2 siblings, 1 reply; 9+ messages in thread
From: Yubo Miao @ 2020-02-21 6:35 UTC (permalink / raw)
To: peter.maydell, shannon.zhaosl
Cc: imammedo, miaoyubo, qemu-devel, xiexiangyou, mst
From: miaoyubo <miaoyubo@huawei.com>
Currently virt machine is not supported by pxb-pcie,
and only one main host bridge described in ACPI tables.
In this patch,PXB-PCIE is supproted by arm and certain
resource is allocated for each pxb-pcie in acpi table.
The resource for the main host bridge is also reallocated.
Signed-off-by: miaoyubo <miaoyubo@huawei.com>
---
hw/arm/virt-acpi-build.c | 125 +++++++++++++++++++++++++++++++++++----
hw/pci-host/gpex.c | 4 ++
include/hw/arm/virt.h | 7 +++
3 files changed, 125 insertions(+), 11 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 0540234b8a..2c1e0d2aaa 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -49,6 +49,8 @@
#include "kvm_arm.h"
#include "migration/vmstate.h"
+#include "hw/arm/virt.h"
+#include "hw/pci/pci_bus.h"
#define ARM_SPI_BASE 32
static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
@@ -271,19 +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
}
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
- uint32_t irq, bool use_highmem, bool highmem_ecam)
+ uint32_t irq, bool use_highmem, bool highmem_ecam,
+ VirtMachineState *vms)
{
int ecam_id = VIRT_ECAM_ID(highmem_ecam);
- Aml *method, *crs;
+ Aml *method, *dev, *crs;
+ int count = 0;
hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
hwaddr base_ecam = memmap[ecam_id].base;
hwaddr size_ecam = memmap[ecam_id].size;
+ /*
+ * 0x600000 would be enough for pxb device
+ * if it is too small, there is no enough space
+ * for a pcie device plugged in a pcie-root port
+ */
+ hwaddr size_addr = 0x600000;
+ hwaddr size_io = 0x4000;
int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
+ int root_bus_limit = 0xFF;
+ PCIBus *bus = NULL;
+ bus = VIRT_MACHINE(vms)->bus;
+
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ uint8_t bus_num = pci_bus_num(bus);
+ uint8_t numa_node = pci_bus_numa_node(bus);
+
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ if (bus_num < root_bus_limit) {
+ root_bus_limit = bus_num - 1;
+ }
+ count++;
+ dev = aml_device("PC%.02X", bus_num);
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
+ aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
+ if (numa_node != NUMA_NODE_UNASSIGNED) {
+ method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(numa_node)));
+ aml_append(dev, method);
+ }
+
+ acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq);
+
+ method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(base_ecam)));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ Aml *rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, 0x0000,
+ bus_num, bus_num + 1, 0x0000,
+ 2));
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE, 0x0000,
+ base_mmio + size_mmio -
+ size_addr * count,
+ base_mmio + size_mmio - 1 -
+ size_addr * (count - 1),
+ 0x0000, size_addr));
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
+ 0x0000, size_pio - size_io * count,
+ size_pio - 1 - size_io * (count - 1),
+ base_pio, size_io));
+
+ if (use_highmem) {
+ hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
+ hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
+
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE, 0x0000,
+ base_mmio_high + size_mmio_high -
+ size_addr * count,
+ base_mmio_high + size_mmio_high -
+ 1 - size_addr * (count - 1),
+ 0x0000, size_addr));
+ }
+
+ aml_append(method, aml_name_decl("RBUF", rbuf));
+ aml_append(method, aml_return(rbuf));
+ aml_append(dev, method);
+
+ acpi_dsdt_add_pci_osc(dev, scope);
+
+ Aml *dev_rp0 = aml_device("%s", "RP0");
+ aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, dev_rp0);
+
+ aml_append(scope, dev);
+
+ }
+ }
- Aml *dev = aml_device("%s", "PCI0");
+ dev = aml_device("%s", "PCI0");
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
@@ -303,16 +403,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
Aml *rbuf = aml_resource_template();
aml_append(rbuf,
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
- nr_pcie_buses));
+ 0x0000, 0x0000, root_bus_limit, 0x0000,
+ root_bus_limit + 1));
aml_append(rbuf,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
- base_mmio + size_mmio - 1, 0x0000, size_mmio));
+ base_mmio + size_mmio - 1 - size_addr * count,
+ 0x0000, size_mmio - size_addr * count));
aml_append(rbuf,
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
- size_pio));
+ AML_ENTIRE_RANGE, 0x0000, 0x0000,
+ size_pio - 1 - size_io * count, base_pio,
+ size_pio - size_io * count));
if (use_highmem) {
hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
@@ -322,8 +424,9 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
base_mmio_high,
- base_mmio_high + size_mmio_high - 1, 0x0000,
- size_mmio_high));
+ base_mmio_high + size_mmio_high - 1 -
+ size_addr * count,
+ 0x0000, size_mmio_high - size_addr * count));
}
aml_append(method, aml_name_decl("RBUF", rbuf));
@@ -759,7 +862,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
- vms->highmem, vms->highmem_ecam);
+ vms->highmem, vms->highmem_ecam, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
HOTPLUG_HANDLER(vms->acpi_dev),
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 0ca604dc62..2c18cdfec4 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -36,6 +36,7 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
+#include "hw/arm/virt.h"
/****************************************************************************
* GPEX host
@@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
pci_swizzle_map_irq_fn, s, &s->io_mmio,
&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
+#ifdef __aarch64__
+ VIRT_MACHINE(qdev_get_machine())->bus = pci->bus;
+#endif
qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
qdev_init_nofail(DEVICE(&s->gpex_root));
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 71508bf40c..9accaf2b1b 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -140,6 +140,13 @@ typedef struct {
DeviceState *gic;
DeviceState *acpi_dev;
Notifier powerdown_notifier;
+ /*
+ * pointer to devices and objects
+ * Via going through the bus, all
+ * pci devices and related objectes
+ * could be gained.
+ * */
+ PCIBus *bus;
} VirtMachineState;
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
--
2.19.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
2020-02-21 6:35 [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
2020-02-21 6:35 ` [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Yubo Miao
2020-02-21 6:35 ` [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Yubo Miao
@ 2020-02-21 6:35 ` Yubo Miao
2020-02-21 11:19 ` Michael S. Tsirkin
2 siblings, 1 reply; 9+ messages in thread
From: Yubo Miao @ 2020-02-21 6:35 UTC (permalink / raw)
To: peter.maydell, shannon.zhaosl
Cc: imammedo, miaoyubo, qemu-devel, xiexiangyou, mst
From: miaoyubo <miaoyubo@huawei.com>
Currently, pxb-pcie could be defined by the cmdline like
--device pxb-pcie,id=pci.9,bus_nr=128
However pxb-pcie is not described in acpi tables for arm.
The formal two patches support pxb-pcie for arm, escpcially the
specification for pxb-pcie in DSDT table.
Add a testcase to make sure the ACPI table is correct for guest.
Signed-off-by: miaoyubo <miaoyubo@huawei.com>
---
tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes
tests/qtest/bios-tables-test.c | 54 +++++++++++++++++++++++++++++----
2 files changed, 48 insertions(+), 6 deletions(-)
create mode 100644 tests/data/acpi/virt/DSDT.pxb
diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb
new file mode 100644
index 0000000000000000000000000000000000000000..4eea3192c75ff28f7054d626a9363ca025b6c0ad
GIT binary patch
literal 34209
zcmeI*cXU+szJ~D)1PGxe5PG+us9-{<Do8R35G4>YGz}UAMT!L#ks?x*Dx!d5hoIPd
z?}}o>iWL;GW5HgrlKbvVM&HM??^)~qbMIProvd|8p2_U*%qO!m?AgcPkRQ(<wr)WX
zR3DKyBsMVKK5tZUEMJ#Z3xXj0I{cizY-H-_vUpxu>HL<ltgNimvVn#9^>bszg^Hd*
zYT59@{GfDxK}u{$QSzH5MFX?4va_qcnOYVriD$G-YqqdX5KgQUqzA#0T0ymH9aJ-P
zt=#;Qdf_)p=V$jH6t9{xXmH68P3ev)8EFlwrs(=X$_(9dxJh>6UU8FZi5vcVla%Bp
zz50)g^-pXvw4i9XAYFAU@nN}Xb+t___n%u<uhU$chBua*GNL5;Gf3Q8mfgX>w)`8L
z7F4goX88!*;pB+$X8&bG_2BOj*;OO*!h6xx&B+mI)uU#l*o>||BPVi3ji?#5Y(|dH
z=oUF6C2B^h&FJPcx<}5a88su#W_0%%JtAk+ikeZ+X7unGJtJq-j+)WHX7uzKy&`9%
zM$JgK8NGZ)@5mW-qGmL*8NF>rHhzu%+CS2wW@OrogM3EhZpvSh<gVV-W*qD@qW9B!
zQTL;{%{atoMDM5dqh_?U8GU?4^nThPYDR0D(bs20@23r;X0){#hx&}@{WLvlMthsl
z&u2vMrx{T*_OKbbJ|lWRZ4@<QFPo9)Gots?#!)jm+KiaZ=o-DBW=74}*JkAVjOhKe
zNz{z}Y(|04h~7_|M$I_DX7u+N(fet$s2N>s#sHrYy`MIZnvrEQ2KtQX{j^2YjIK7L
z&}T&Nr!Avqbh8<U`HblOv{lrM9ya4}pAo&EwvL+7%VrGn8PWS`o2VHF*^DBakrTb2
zwvC!`h|L)6Gots?c2P6>+KeGpGv;lrQ5@@4bw`Q^7iZ;W_0oY$Ob29%%1Indg_l(x
zNW=>U=<B?^!D(|V57fd>@nIzyEz+7!38n{QgZ4pwa9l7gm>7)H=Rj93E*aK%`Pv$F
zgOo;fQ|eY!1OwuQSwZ6KYWg}mXjCt}JgvH-Ycgsma)L(nQ|eVz=ol|?y{Zbg(iIyd
zzE`=OuA0nnOU<vmt`3zF*R85>%j8vc92DN7u3EXJGTc)4rt-QqDz{ADgBn4&W%8;u
z5?ku3m0K#qEp?A7x70yl;<{B;Wvslaj+?5K$#iE;IBQnkX3|+Rv1RhkE8STOP8|vB
z9we`-<1BY7-B}yX+HlsUQ|ZoBI8!UPO#Vo8T;@)tJL|xyWB9~RukuGyhfbwC)8I^l
zQ^#@cRJyY+oOR)>OQ+JEdLdztXFWJ|+~-cEJL|()AI|!8D&5%t&IWMmIMJO-cQ%Bx
zA)F2ARJv2Iq0E^Mr;aP#sdQ%soEdOt(5ZB1BRCtuspC+0D&5%_&c<*yrc>$8OgJ;)
z)N!jjmF{c;XA?M^(5ZB1Q#hN#spDLCD&5%(&Sr2nqf_Zly~4D|vpJkPE_SEVoh{&O
z0cQ(3mF{c_XG=JB9PLh}J6plo3eHw^D&5%{&em}1xZ9mdcea7E4V-Q0RJyY*oNeLM
zak@K|?raBVJ2>0XsdQ(1INQUi<9c^0-Kn!8+7pt0vvq*81D#5D?g8f>aO!n{JC*L-
z6V5&1+>=hFJNJTfFF5tO!JSHX?hWVOaPCc~(w!aQ><Fh`XSh@8&VAtA2hM%yRJwCt
zIQNB9uS?vibY~|xJHgqBPNh5dgL6MP^*Y9#N_XxL=l*c+Pp8tI2f%p%oO<2kPNh3L
z!`T_m&U7l>*#*unaO!oEJC*J{5Y7YPJdjSMJ9RqFo^P|@)axpDD&48GaQ6F|4QDo;
zN_Xnqo3>0Id3J?UufyD_bf?a^Y0KpCZ4R6{bSmAc^K9nq2B%)Pxl`#*on13$cR0J#
zsdT5#shP6}oO+$-PNh3_Ce55Z;p|DL(w#bgX3k!4>UE(zmG0D8GjsNavp1becj{c3
zIS+zUuOr>5bf?acne$*c52jP;PMsGs=OJ+Fb*DR(?$p^ZbM}F=51mSP>KvFk`@*T$
zsqR#|Q)j-+c_^HR(y4T3KRElr*^f@8J9U=JoVjr3(y4T(&TW}956(O~mG0CTEpx`;
zjM1rdr_N((%j7HId^q#zRJv1VugqBhX91l`cj}y#Is3!epH8Jab*9Rk1K=D$r_!A|
zKV{B=a1NwX=}w)MGG`&2g>)+2sdG{0JPgjm=v2B>XQ0e^IGl&msdT5#JDGD3oP+38
zx>IMH%vl6y5uHkR>Kv0f2g5m-PNh3_X33mG;2c7y(w)U{7Q<Ogr_!B6;T#I*P&$?F
zEP=BG&JsG6?u^43hciy6(w)QL90unwI+gAm4(D(<htsKa=Lk4Qz&V0Wr8`H$ITFs1
zbSm9B3eHh*j-pfP&LiMF0?s4oRJ!v>IFE$$NII47EQPZa&Qdy+?i>y0XgEjHsdVR2
za2^HcQFJQZc{H3y!+A8FN_UpQSq5hrol19(fpZL;W9U@6^B6dff%6zTmF^r1=U6z$
z(y4UkI5@|_IgU=HJCB9)SU8WRQ|V5f@3!aL<KR4wPNh4?!#N(#@pLNPc|4rQ!+AWN
zN_S3xa{`<b=v2CMBAgT9oJgnAos;041m`3=mF}Dj=VUl1)2Vdl32>eO=LvKw-FYIM
zC&GCmol19}1m{U`o<yh8ohQS2GMp#VsdVQQIH$llg-)eAPl59kI8UKd>CRK(JQdDU
z=~TM&G&oO#^E5h@?wkteR5+*7sdVS*aGnn5>2xaHIStNfa89FB>CQ9YJOj=%=v2CM
zI-JwtoKC0GoipH^0p|=lmF}Dg=S(<f(y4UkEI4PuIg3uEJI{pkOgPV^Q|ZpxaL$Hv
zHl0d$o(1PwaGph{(w%eQoCD_^I+gC63+G%o=hCTk=R7#)!8wmkr90=tIUmmXbSm9>
zHk@a}c{ZI&cb)_1IdGmsr_!AZ;9LOb0y>rMTnOhvI2Y2Xbmt;C7s0uRPNh2+!?_sF
z#dIp&xdhH7a4w-!>CUBaE`@U`ol19}3+K6To=d0Foy*`{2In$5mF_$b&hy|rk4~jK
zm&3Un&gFC}-FZHo=finEol19J0Otj8UO=bPoh#s60p|)jmF`>#=SnzN(y4UkDmYic
zxr$DuJ1>OuLO3s^Q|Zo&;JgUVi|ACkb2Xf+;ap9p(w!H>c`=+9)2VdlC2(E>=OuJ1
z-FYdTm%@1|ol19J2IpmPUPh<VotMLTIh>c%sdVQRa9#oD6?7`yc_o}z!g(c~N_Vb-
za}Atp=v2CMEu3rNTuZ0Yo#k+r!&y$J(w*zzTnFbmI+gCc3eKzGyoyexJFkZGYB;Z^
zQ|Zq2aIS}QJ)KH-UIXVfa9%^F(w*1Bc`cmR(y4Ukb#Pt>=XG={-FZEn*TZ=|ol1A!
z0Ot*G-ax0)oj1aHBb+zVsdVQ}aNY#xO>`>Vc{7|h!+A5EN_XA@=PhvFLZ{N5x59ZV
zoVU`cbmwhw-UjDwbSm9>JDj(}c{`m-cisW#9dO=3r_!Bw!g(j0chaeJ=Us5#1?OFK
zD&2WEoOi={H=Rm%-UH`7aNa|w(w+Chc`uyz(y4UkeQ@3f=Y4c4-FZKp_rrNVol18;
z0Otd6K0v3^oe#qKAe;}<sdVQ<a6Sa*Lv$+L`7oRh!}&0sN_Rd2=Ob`FLZ{N5kHYyV
zoR89}bmwDmJ_hGwbSmAs0nQC@ZlF`?&d1?=9L~q-RJ!vCIG=#?2|AVT+z97JI5*O%
zbmx<BJ_+ZObSmBX6r4}N`4pW>cRmg0({Mgbr_!Cz!1)ZE&(NuK=d*A=3+J<RD&4sW
z&P{M`qEqS4=iqz}&gbY<y7PHBpNI2#I+gBx0nQiTe1T4-J70wJML1uiQ|Zo^;Cu<r
zm*`Zw^JO?+hVx}QmG0aO=VmxJ)2VdlD{#I7=PPt7-T5k<ufq8%ol1AU2Ip&VzDB3g
zov*|BI-IZ5sdVQXaJ~WO8+0n&`6iri!uckhN_TF7a|@hX=v2CME1X;5+)Ag?oo~VU
z7MyR<sdVStaJ~)a+jJ`3xed;3aBibh>CSiHd<V{V=v2CMJDl6$+)k&`o$tc=E}ZYu
zsdVRiaJ~oUdvq$@`97TQ!}&g)N_Tz$=Lc|pK&R53AHw+|oFCGubmvEKegx-7bSmBX
zF`OU6`7xbJckY052b??TRJ!vMI6r~&6FQad{1nbl;rx_Nr8_@^^D{U<qf_b5&*A(W
z&d=#ox^pL-JK@|(r_!BY!1)E7U(l&^=a+DP3Fnt|D&6@NoL|BD6`e|Vehuf>aDGjv
z(w*PH`3;=k(5ZCiw{U(7=eKk!-T57y-@*AEol19p59jxAeov>;oj<_&1Drq5sdVR$
zaQ+DAk8~>C`4gN!!TA%NN_YMY=g)BdOsCSFyWrdf=Po*x?)(MLU*P<OPNh44h4WW9
zf2C9D&fnnt4bI=_RJ!wbIDd!pcRH2s`~%KE;QWJ5r91zG^G`Vcq*Lk6-Ei)Pb2ptz
zcUHhz0cQoB%7n9YeqoCK!x&p;8q4ahm7(DqeT3^n;~5Ro>Q=sg$DTpr{X4?<_uyrj
zwaVfp@oH70s+PTmYgGTcQF}#<N?gWKRjaiB-Kf1IMkOxesH(-<|87*rh*62lszzm|
zm&NjOgY^w`#q@sqBXdZ@@a;~5)RMg6{WAvEPMf;8eo(!hzB4z_|1qq016kB82<lbS
zm-<-Sx1wTq-^ABr!tYe8SEI5v1c8>`>Z77>&@Tv<?*I2T;icu3->e8f!u;!FOyyTI
zg7yDrx11UuUR)fc#)g#)3NriGDH{@xr7WEs#PUaGmk+GHYC=ZiwDi)VZ8^KzweGii
z<kZ{^eYT8WIyo&xSLmwGsrsBVC5&)R_(e`QYF7A1TD$Pi^7NIfCRUrR?_^hAJG;E;
z%2mnhB`!`6zd0qma(Mar$?F;<E)Q=cd;R3h&Sm-WqLlIuiF>oT=cXO;?lX&4G}~F!
zVq>hRyw0jg`T^FcRxSKP@A*=<q&Tar@=a<KOSWqXw*PKKEy4b4*|mOO^xig!-<|s5
zcKR}0f88#vb#V|23bp3CeUPR9{c{y|V)^!e)?!z#gG(;H_O%TuiD#?iikO;sZmo&u
z)|z~7Rr+&lEj+i@!gFgaKDR3UxwST)TWjOFwKktym5Jxp#G3Qe$}N-s&3|g;mj79c
z9sY!pk7s>6p7rr~*5~7?^v6@r#F~>_W7PnUX9GT-N`E{X;_+;V$Fm_HPo+Pe>3BTT
z@pz^uwoJY;fYO~AaAv@nL8sE4jo@qqXCpe5?raQaV>lbrsdQ&1oSATD(y4T36F8f|
z*@RA|JDbAU6wan}D&48SXKjzt->u<6P1Tz~G^11L&gO77hqF1IN_Vz^vjv<j=v2D1
zC7dncY)Plmovq+(1!pTdmF{c}XKOfH)2Vc48#vp**@jM~JKMt97S6VGD&5%*&USFN
zqf_b5_Hed`vpt<kcXoiY1DqY`RJwByIQM{a4?30Z)KRtVw|m05C!I=n>VP@1k5|5z
z$zE{oMW@o8IzHBx$u;MD!?`z|N_XmTSX(BaZ#%--kxr#M_knXCIQOAb>CS!O+!xM$
z=~TM26P%sk>_n&1o%_MLADsKqsdT4~-R<$*AI|;hRJ!v3I1hmH06LZK><njTI6Kp+
zbY~YhyTI9nPNh2!g!4c+52RD+&MY{y;LM^^>CS98v*FC9Q|ZpGaCU{WE1gPr=D?W)
zXAYf8cXorb8=T$fRJyY}oZaE<PN&kHJ>cvCXAe4+?(7L?PdIzhsdQ&AID5g_i%z9G
zd&Aiq&fat?-FXn42f=v|ol18e4Cldc9!#gworl1A2%Lw|sdQ%_IQziahfbwCb+*8s
zZ~Ma8mrkWS4~6qkI1i;$>CS#|_Jgw@ol1A+!kG(aE}cqu=E0c<XC9qOcgEn1!5O1d
z>CSvO^Wn^=Q|ZnEI1At`pi}A2{&4n(vp=0mcMgDa0GtEpRJwB@oCDz;NT<@Bg>V+a
zSxBeSorl4B7@UXEsdVSza2^il;dCn9IS9@{a1NqV>CPfJi{LDxQ|ZpZa1MrZFr7+w
z4uNwBoI~hTy0aM0VmOQGRJwC0oI~LpN~hADC2*F&Swg4MopCthaK`CWx^ozu!{8i7
zr_!Cn;T#U<a5|Ol90BJDI7iT_bmvGoN5VOhPNh3X!8r=fQFJQZc?6tCz<C6nN_QR!
z=aFz8NvG1CrEr$QSxTqUoulC#4d-Y&mF_$W&ZFQwicY0FkB0MTIFF`N>CQ4Z%it`d
zQ|V5fme=3e$@6_<;2cAz(w)b^c?_J#(5ZCiSUAVRIhIbPJIBE}4$g6OD&2W3oX5g>
zES*Ys9tY=fa2`je(w*bs91rJsI+gA`9?s+8Jf2RaJ14+70nQ0@D&08|&WUhNq*Lk6
zNpMbra}u3OcTR?LGMtm?RJ!v7I8T7{1Ui-OJQ2<l;XIK}r8`f8^CUP=qEqS4li@rW
z&Xeg>x^oJgQ{bFJr_!CLz<COsr_iZ%=c#a>3g@YGD&2V+oTtHg8l6gaPK9$SoKxvk
zy7P26Plxk#I+gC62In+5r_rf&=NWLG0p}TXD&099&gpPYr&H<98F0>ka|WGCcg}=!
zCY&?rRJwB(oU`DZMW@o8XTo_VoM+Ohbmwe1XTv$0PNh4~g7Yjm&!SW5&N*<-fpZR>
zN_WnMb1s~7=~TLN9-Q;woJXh9o%7+G59fS3mF_$n&a>e>n@*)W&w=wCIM1O|>COdk
zE`W0Zol18ugmWRB3+Yt4a}k`2;9Nwf(w&RpTny)8I+gBR0_PGqm(Zzn=TbPA!nu@A
zr901s^ISO3rBmt7WpFNoa~YjVcb*65d2pUbr_!Cv;am>qaypgnJRi>U;XI#Cr8_Tx
z^8z?8pi}A26>zSAa|NABcdmqUC7dhiRJwB&oU7nmMW@o87s7cVoEOrmbmv8IUIgbw
zbSmAs8qU>luBKDz&Wqu^7|x67RJ!vLI4^<o5;~RcycEt$;k=Yir8_T!^D;Ouqf_b5
z%i+8n&dcdky7LM+uYmIkI+gCc63#2(ypm3(JJ-Ou2F^8fD&4sj&b4r^rBmt7ayZN3
zET>cH&UJ9EgL567N_Sob=T&fCMW@o8SHpQVoLAGSbmw|F*TcD<PNh4qf%6(Tuc1@v
z&THYk7S3zwRJ!vzIIn~AIy#l^ydKW$;k=$sr8{qc^9DF?pi}A28{xbW&Kv1ey7MMD
zZ-VnCI+gCc8P1#GyqQj=J8yyW7C3LAQ|ZoI;k*^jTj^A~^ENndgYz~zmF~P9&fDR<
zold1Y?|}0TIPaiS>CQXhyc5nl=~TM&E;#Rk^Da7-?z|h$yWzZ>PNh5Vf%6_X@1axa
z&U@j!7tVX>RJ!v%IPZh=K01}|ydTc{;k=(tr8^&h^8q*?pi}A22jP4W&IjpKy7M78
zAA<8CI+gBx7|w^`e3(w9J0F4b5jY>AQ|Zn};d~U%N9k0$^D#IdgYz*umG0aC=LR@8
z(5ZCi<8VF>=i_uL-T4HZPr&&Eol19ZgmWXD8|hTK^GP_Lg!4%{mF|2B&ZppficY0F
zpN8{kIG?6d>CR{1d<M>E=v2D%Sva4C^I1BT?%V|DCO9|IsdVRaa6Sj;b95@*`8=G@
z!}&a&N_V~h=L>MYK&R53FT(jEoG;R;bmvQOz69q>bSmBXGMq2N`7)hKcW#DrGn||0
zRJ!vOIA4MD6*`sfd=<`D;e3@&r8{4P^EEhMqf_b5*Wr8}&e!Qwy7LV<-+=QCI+gBx
z6V5l`e3MS4JGa2O1<oyWD&4si&aH56rBmt7x8QsW&bR1Py7O%~--h#TI+gC+2In?7
zx6!F|=R0t|1Lr$*D&4sq&h2n+r&H<9cj0^&&Ufily7N6a--Gi#I+gBxAI|sTe4kFG
zJ3oN)12{jRQ|ZnR;rtNJ59w68^CLJvg7YIfmG1l)&X3{zm`<fTcfh#=&K-0r-T4We
zpTPMEol19p3g@SAeoCj(ou9$^8JwTdsdVS(aDEQw=X5IFxf9NvaPFj2>CP|U`~uD|
z=v2D%OE|xT^GiCF?)(bQui*TOPNh4)hVyGUzot{^&TruS2F`EjRJ!w9IKPGSTRN5Q
z{0`3V;QWqGr8~ce^LseIr&H<9AK?4}&L8Mhy7Nake}wZ#I+gDH3C^G3{E1GbJAa1r
zXE=YRQ|ZoKaPES07oAFX{sQMOaQ;H4(w)D;`74~i(y4UkZ*cww=Wlc>-T6D5zr*=E
zol1B90p}lZ{z0eGoqxjlC!BxMsdVRVICsOjn@*)WE8whvvw}`#!ug-I*ncf7?-=~+
zV)Mjh|MRujK`=+t=3*^&kX})-rmrs6$J#Eo7F%7Ra|e}cu{ZqdTI_I6xLSMdKh|QG
zSA@6m&$Zb9o45S`eJyrTN=ZQ+Z&T1!>#M^zBgje1`sb4Q#PWPCm~Yol4~u=IhhNXo
z((b(4qq~&F^U4Mk<ZHS2K>efIxv}EHtgP(tU)9!|AJo@3s^%x&?4U-qPKizD7L@28
z+ODU6KD$m@O6k11Va5vL1%ujWwkazZF|5v%FvgUpubMR`t-5~I7Z#5!$xEACI=@}`
SMdHR1??VvNE&R1)JoqmftDW!w
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index b4752c644c..91e91e0fec 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -620,12 +620,21 @@ static void test_acpi_one(const char *params, test_data *data)
* TODO: convert '-drive if=pflash' to new syntax (see e33763be7cd3)
* when arm/virt boad starts to support it.
*/
- args = g_strdup_printf("-machine %s %s -accel tcg -nodefaults -nographic "
- "-drive if=pflash,format=raw,file=%s,readonly "
- "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s",
- data->machine, data->tcg_only ? "" : "-accel kvm",
- data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : "");
-
+ if (data->cd) {
+ args = g_strdup_printf("-machine %s %s -accel tcg "
+ "-nodefaults -nographic "
+ "-drive if=pflash,format=raw,file=%s,readonly "
+ "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : "");
+ } else {
+ args = g_strdup_printf("-machine %s %s -accel tcg "
+ "-nodefaults -nographic "
+ "-drive if=pflash,format=raw,file=%s,readonly "
+ "-drive if=pflash,format=raw,file=%s,snapshot=on %s",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ data->uefi_fl1, data->uefi_fl2, params ? params : "");
+ }
} else {
/* Disable kernel irqchip to be able to override apic irq0. */
args = g_strdup_printf("-machine %s,kernel-irqchip=off %s -accel tcg "
@@ -960,6 +969,38 @@ static void test_acpi_virt_tcg_numamem(void)
}
+static void test_acpi_virt_tcg_pxb(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+ /*
+ * While using -cdrom, the cdrom would auto plugged into pxb-pcie,
+ * the reason is the bus of pxb-pcie is also root bus, it would lead
+ * to the error only PCI/PCIE bridge could plug onto pxb.
+ * Therefore,thr cdrom is defined and plugged onto the scsi controller
+ * to solve the conflicts.
+ */
+ data.variant = ".pxb";
+ test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
+ " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
+ " -drive file="
+ "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
+ "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
+ " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
+ "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
+ " -cpu cortex-a57"
+ " -device pxb-pcie,bus_nr=128",
+ &data);
+
+ free_test_data(&data);
+}
+
static void test_acpi_tcg_acpi_hmat(const char *machine)
{
test_data data;
@@ -1052,6 +1093,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
+ qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.19.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
2020-02-21 6:35 ` [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Yubo Miao
@ 2020-02-21 11:17 ` Michael S. Tsirkin
2020-02-22 9:37 ` miaoyubo
0 siblings, 1 reply; 9+ messages in thread
From: Michael S. Tsirkin @ 2020-02-21 11:17 UTC (permalink / raw)
To: Yubo Miao
Cc: peter.maydell, imammedo, qemu-devel, xiexiangyou, shannon.zhaosl
On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote:
> From: miaoyubo <miaoyubo@huawei.com>
>
> Currently virt machine is not supported by pxb-pcie,
> and only one main host bridge described in ACPI tables.
> In this patch,PXB-PCIE is supproted by arm and certain
> resource is allocated for each pxb-pcie in acpi table.
> The resource for the main host bridge is also reallocated.
>
> Signed-off-by: miaoyubo <miaoyubo@huawei.com>
> ---
> hw/arm/virt-acpi-build.c | 125 +++++++++++++++++++++++++++++++++++----
> hw/pci-host/gpex.c | 4 ++
> include/hw/arm/virt.h | 7 +++
> 3 files changed, 125 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 0540234b8a..2c1e0d2aaa 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -49,6 +49,8 @@
> #include "kvm_arm.h"
> #include "migration/vmstate.h"
>
> +#include "hw/arm/virt.h"
> +#include "hw/pci/pci_bus.h"
> #define ARM_SPI_BASE 32
>
> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
> @@ -271,19 +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
> }
>
> static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> - uint32_t irq, bool use_highmem, bool highmem_ecam)
> + uint32_t irq, bool use_highmem, bool highmem_ecam,
> + VirtMachineState *vms)
> {
> int ecam_id = VIRT_ECAM_ID(highmem_ecam);
> - Aml *method, *crs;
> + Aml *method, *dev, *crs;
> + int count = 0;
> hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
> hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
> hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
> hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
> hwaddr base_ecam = memmap[ecam_id].base;
> hwaddr size_ecam = memmap[ecam_id].size;
> + /*
> + * 0x600000 would be enough for pxb device
> + * if it is too small, there is no enough space
> + * for a pcie device plugged in a pcie-root port
> + */
> + hwaddr size_addr = 0x600000;
> + hwaddr size_io = 0x4000;
> int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> + int root_bus_limit = 0xFF;
what's this?
> + PCIBus *bus = NULL;
> + bus = VIRT_MACHINE(vms)->bus;
So just move assignment as part of declaration.
> +
> + if (bus) {
> + QLIST_FOREACH(bus, &bus->child, sibling) {
> + uint8_t bus_num = pci_bus_num(bus);
> + uint8_t numa_node = pci_bus_numa_node(bus);
> +
> + if (!pci_bus_is_root(bus)) {
> + continue;
> + }
> + if (bus_num < root_bus_limit) {
> + root_bus_limit = bus_num - 1;
what is this doing? manually coded up MIN?
> + }
> + count++;
> + dev = aml_device("PC%.02X", bus_num);
> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
> + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
> + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
> + if (numa_node != NUMA_NODE_UNASSIGNED) {
> + method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
> + aml_append(method, aml_return(aml_int(numa_node)));
> + aml_append(dev, method);
> + }
> +
> + acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq);
> +
> + method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
> + aml_append(method, aml_return(aml_int(base_ecam)));
> + aml_append(dev, method);
> +
> + method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
> + Aml *rbuf = aml_resource_template();
> + aml_append(rbuf,
> + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED,
> + AML_POS_DECODE, 0x0000,
> + bus_num, bus_num + 1, 0x0000,
> + 2));
> + aml_append(rbuf,
> + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> + AML_MAX_FIXED, AML_NON_CACHEABLE,
> + AML_READ_WRITE, 0x0000,
> + base_mmio + size_mmio -
> + size_addr * count,
> + base_mmio + size_mmio - 1 -
> + size_addr * (count - 1),
> + 0x0000, size_addr));
> + aml_append(rbuf,
> + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
> + AML_POS_DECODE, AML_ENTIRE_RANGE,
> + 0x0000, size_pio - size_io * count,
> + size_pio - 1 - size_io * (count - 1),
> + base_pio, size_io));
> +
> + if (use_highmem) {
> + hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
> + hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
> +
> + aml_append(rbuf,
> + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> + AML_MAX_FIXED, AML_NON_CACHEABLE,
> + AML_READ_WRITE, 0x0000,
> + base_mmio_high + size_mmio_high -
> + size_addr * count,
> + base_mmio_high + size_mmio_high -
> + 1 - size_addr * (count - 1),
> + 0x0000, size_addr));
> + }
> +
> + aml_append(method, aml_name_decl("RBUF", rbuf));
> + aml_append(method, aml_return(rbuf));
> + aml_append(dev, method);
> +
> + acpi_dsdt_add_pci_osc(dev, scope);
> +
> + Aml *dev_rp0 = aml_device("%s", "RP0");
> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, dev_rp0);
> +
> + aml_append(scope, dev);
> +
> + }
> + }
>
> - Aml *dev = aml_device("%s", "PCI0");
> + dev = aml_device("%s", "PCI0");
> aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> @@ -303,16 +403,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> Aml *rbuf = aml_resource_template();
> aml_append(rbuf,
> aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
> - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
> - nr_pcie_buses));
> + 0x0000, 0x0000, root_bus_limit, 0x0000,
> + root_bus_limit + 1));
> aml_append(rbuf,
> aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
> AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
> - base_mmio + size_mmio - 1, 0x0000, size_mmio));
> + base_mmio + size_mmio - 1 - size_addr * count,
> + 0x0000, size_mmio - size_addr * count));
> aml_append(rbuf,
> aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
> - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
> - size_pio));
> + AML_ENTIRE_RANGE, 0x0000, 0x0000,
> + size_pio - 1 - size_io * count, base_pio,
> + size_pio - size_io * count));
>
> if (use_highmem) {
> hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
> @@ -322,8 +424,9 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
> AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
> base_mmio_high,
> - base_mmio_high + size_mmio_high - 1, 0x0000,
> - size_mmio_high));
> + base_mmio_high + size_mmio_high - 1 -
> + size_addr * count,
> + 0x0000, size_mmio_high - size_addr * count));
> }
>
> aml_append(method, aml_name_decl("RBUF", rbuf));
> @@ -759,7 +862,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
> - vms->highmem, vms->highmem_ecam);
> + vms->highmem, vms->highmem_ecam, vms);
> if (vms->acpi_dev) {
> build_ged_aml(scope, "\\_SB."GED_DEVICE,
> HOTPLUG_HANDLER(vms->acpi_dev),
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index 0ca604dc62..2c18cdfec4 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -36,6 +36,7 @@
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> #include "qemu/module.h"
> +#include "hw/arm/virt.h"
>
> /****************************************************************************
> * GPEX host
> @@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
> pci_swizzle_map_irq_fn, s, &s->io_mmio,
> &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
>
> +#ifdef __aarch64__
> + VIRT_MACHINE(qdev_get_machine())->bus = pci->bus;
> +#endif
I'm repeating myself but - what does this have to do with
building on __aarch64__?
> qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
> pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
> qdev_init_nofail(DEVICE(&s->gpex_root));
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> index 71508bf40c..9accaf2b1b 100644
> --- a/include/hw/arm/virt.h
> +++ b/include/hw/arm/virt.h
> @@ -140,6 +140,13 @@ typedef struct {
> DeviceState *gic;
> DeviceState *acpi_dev;
> Notifier powerdown_notifier;
> + /*
> + * pointer to devices and objects
> + * Via going through the bus, all
> + * pci devices and related objectes
> + * could be gained.
> + * */
> + PCIBus *bus;
That comment doesn't really tell me what this is.
Is this the root bus?
With an extender, don't we have lots of roots?
> } VirtMachineState;
>
> #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
2020-02-21 6:35 ` [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie " Yubo Miao
@ 2020-02-21 11:19 ` Michael S. Tsirkin
2020-02-22 9:40 ` miaoyubo
0 siblings, 1 reply; 9+ messages in thread
From: Michael S. Tsirkin @ 2020-02-21 11:19 UTC (permalink / raw)
To: Yubo Miao
Cc: peter.maydell, imammedo, qemu-devel, xiexiangyou, shannon.zhaosl
On Fri, Feb 21, 2020 at 02:35:12PM +0800, Yubo Miao wrote:
> From: miaoyubo <miaoyubo@huawei.com>
>
> Currently, pxb-pcie could be defined by the cmdline like
> --device pxb-pcie,id=pci.9,bus_nr=128
> However pxb-pcie is not described in acpi tables for arm.
>
> The formal two patches support pxb-pcie for arm, escpcially the
> specification for pxb-pcie in DSDT table.
>
> Add a testcase to make sure the ACPI table is correct for guest.
>
> Signed-off-by: miaoyubo <miaoyubo@huawei.com>
Please look at the top of tests/qtest/bios-tables-test.c
for how to add or update tests.
> ---
> tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes
> tests/qtest/bios-tables-test.c | 54 +++++++++++++++++++++++++++++----
> 2 files changed, 48 insertions(+), 6 deletions(-)
> create mode 100644 tests/data/acpi/virt/DSDT.pxb
>
> diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb
> new file mode 100644
> index 0000000000000000000000000000000000000000..4eea3192c75ff28f7054d626a9363ca025b6c0ad
> GIT binary patch
I can't read this.
> literal 34209
> zcmeI*cXU+szJ~D)1PGxe5PG+us9-{<Do8R35G4>YGz}UAMT!L#ks?x*Dx!d5hoIPd
> z?}}o>iWL;GW5HgrlKbvVM&HM??^)~qbMIProvd|8p2_U*%qO!m?AgcPkRQ(<wr)WX
> zR3DKyBsMVKK5tZUEMJ#Z3xXj0I{cizY-H-_vUpxu>HL<ltgNimvVn#9^>bszg^Hd*
> zYT59@{GfDxK}u{$QSzH5MFX?4va_qcnOYVriD$G-YqqdX5KgQUqzA#0T0ymH9aJ-P
> zt=#;Qdf_)p=V$jH6t9{xXmH68P3ev)8EFlwrs(=X$_(9dxJh>6UU8FZi5vcVla%Bp
> zz50)g^-pXvw4i9XAYFAU@nN}Xb+t___n%u<uhU$chBua*GNL5;Gf3Q8mfgX>w)`8L
> z7F4goX88!*;pB+$X8&bG_2BOj*;OO*!h6xx&B+mI)uU#l*o>||BPVi3ji?#5Y(|dH
> z=oUF6C2B^h&FJPcx<}5a88su#W_0%%JtAk+ikeZ+X7unGJtJq-j+)WHX7uzKy&`9%
...
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
2020-02-21 11:17 ` Michael S. Tsirkin
@ 2020-02-22 9:37 ` miaoyubo
0 siblings, 0 replies; 9+ messages in thread
From: miaoyubo @ 2020-02-22 9:37 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, imammedo, qemu-devel, Xiexiangyou, shannon.zhaosl
> -----Original Message-----
> From: Michael S. Tsirkin [mailto:mst@redhat.com]
> Sent: Friday, February 21, 2020 7:18 PM
> To: miaoyubo <miaoyubo@huawei.com>
> Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; Xiexiangyou
> <xiexiangyou@huawei.com>; imammedo@redhat.com;
> qemu-devel@nongnu.org
> Subject: Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
>
> On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote:
> > From: miaoyubo <miaoyubo@huawei.com>
> >
> > Currently virt machine is not supported by pxb-pcie, and only one main
> > host bridge described in ACPI tables.
> > In this patch,PXB-PCIE is supproted by arm and certain resource is
> > allocated for each pxb-pcie in acpi table.
> > The resource for the main host bridge is also reallocated.
> >
> > Signed-off-by: miaoyubo <miaoyubo@huawei.com>
> > ---
> > hw/arm/virt-acpi-build.c | 125
> +++++++++++++++++++++++++++++++++++----
> > hw/pci-host/gpex.c | 4 ++
> > include/hw/arm/virt.h | 7 +++
> > 3 files changed, 125 insertions(+), 11 deletions(-)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index
> > 0540234b8a..2c1e0d2aaa 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -49,6 +49,8 @@
> > #include "kvm_arm.h"
> > #include "migration/vmstate.h"
> >
> > +#include "hw/arm/virt.h"
> > +#include "hw/pci/pci_bus.h"
> > #define ARM_SPI_BASE 32
> >
> > static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -271,19
> > +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) }
> >
> > static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry
> *memmap,
> > - uint32_t irq, bool use_highmem, bool
> highmem_ecam)
> > + uint32_t irq, bool use_highmem, bool
> highmem_ecam,
> > + VirtMachineState *vms)
> > {
> > int ecam_id = VIRT_ECAM_ID(highmem_ecam);
> > - Aml *method, *crs;
> > + Aml *method, *dev, *crs;
> > + int count = 0;
> > hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
> > hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
> > hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
> > hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
> > hwaddr base_ecam = memmap[ecam_id].base;
> > hwaddr size_ecam = memmap[ecam_id].size;
> > + /*
> > + * 0x600000 would be enough for pxb device
> > + * if it is too small, there is no enough space
> > + * for a pcie device plugged in a pcie-root port
> > + */
> > + hwaddr size_addr = 0x600000;
> > + hwaddr size_io = 0x4000;
> > int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> > + int root_bus_limit = 0xFF;
>
> what's this?
>
Thanks for replying.
This is used to define the bus numbers for the main host bridge,
If no pxb-pcie is defined, the bus number for the main host bridge
would range form 0 to 255.
> > + PCIBus *bus = NULL;
> > + bus = VIRT_MACHINE(vms)->bus;
>
> So just move assignment as part of declaration.
>
Thanks for the suggestion!
> > +
> > + if (bus) {
> > + QLIST_FOREACH(bus, &bus->child, sibling) {
> > + uint8_t bus_num = pci_bus_num(bus);
> > + uint8_t numa_node = pci_bus_numa_node(bus);
> > +
> > + if (!pci_bus_is_root(bus)) {
> > + continue;
> > + }
> > + if (bus_num < root_bus_limit) {
> > + root_bus_limit = bus_num - 1;
>
> what is this doing? manually coded up MIN?
>
This coded up the MIN of busNr defined in pxb-pcie devices,
and the Min busNr-1 would be the MAX bus Number for the main host bridge.
For example, if one pxb-pcie with busNr 128(which is 80) defined,
The bus for the main host bridge would be 0-7F, and the bus for pxb-pcie
would be 80-81(just allocate two buses,keep the same with X86).
If pxb-pcie is not defined, the bus for main host bridge would be 0-FF.
> > + }
> > + count++;
> > + dev = aml_device("PC%.02X", bus_num);
> > + aml_append(dev, aml_name_decl("_HID",
> aml_string("PNP0A08")));
> > + aml_append(dev, aml_name_decl("_CID",
> aml_string("PNP0A03")));
> > + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> > + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> > + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> > + aml_append(dev, aml_name_decl("_BBN",
> aml_int(bus_num)));
> > + aml_append(dev, aml_name_decl("_UID",
> aml_int(bus_num)));
> > + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb
> Device")));
> > + if (numa_node != NUMA_NODE_UNASSIGNED) {
> > + method = aml_method("_PXM", 0,
> AML_NOTSERIALIZED);
> > + aml_append(method,
> aml_return(aml_int(numa_node)));
> > + aml_append(dev, method);
> > + }
> > +
> > * GPEX host
> > @@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error
> **errp)
> > pci_swizzle_map_irq_fn, s,
> &s->io_mmio,
> > &s->io_ioport, 0, 4,
> > TYPE_PCIE_BUS);
> >
> > +#ifdef __aarch64__
> > + VIRT_MACHINE(qdev_get_machine())->bus = pci->bus; #endif
>
> I'm repeating myself but - what does this have to do with building on
> __aarch64__?
>
I would move this into machvirt_init, therefore, the __aarch64__ is not needed.
> > qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
> > pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
> > qdev_init_nofail(DEVICE(&s->gpex_root));
> > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index
> > 71508bf40c..9accaf2b1b 100644
> > --- a/include/hw/arm/virt.h
> > +++ b/include/hw/arm/virt.h
> > @@ -140,6 +140,13 @@ typedef struct {
> > DeviceState *gic;
> > DeviceState *acpi_dev;
> > Notifier powerdown_notifier;
> > + /*
> > + * pointer to devices and objects
> > + * Via going through the bus, all
> > + * pci devices and related objectes
> > + * could be gained.
> > + * */
> > + PCIBus *bus;
>
> That comment doesn't really tell me what this is.
> Is this the root bus?
> With an extender, don't we have lots of roots?
>
>
Yes, this is the root bus.(The pci.0 or pcie.0)
The main root is pci.0 or pcie.0, the extender plays the role of root for devices
plugged on it. For the extender, there is only one root,pci.0 or pcie.0.
But for devices like pcie-root-port, they could also regard pxb-pcie as root.
Hope this solve your question.
> > } VirtMachineState;
> >
> > #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM :
> > VIRT_PCIE_ECAM)
> > --
> > 2.19.1
> >
Regards,
Miao
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
2020-02-21 11:19 ` Michael S. Tsirkin
@ 2020-02-22 9:40 ` miaoyubo
2020-02-23 21:25 ` Michael S. Tsirkin
0 siblings, 1 reply; 9+ messages in thread
From: miaoyubo @ 2020-02-22 9:40 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, imammedo, qemu-devel, Xiexiangyou, shannon.zhaosl
> -----Original Message-----
> From: Michael S. Tsirkin [mailto:mst@redhat.com]
> Sent: Friday, February 21, 2020 7:19 PM
> To: miaoyubo <miaoyubo@huawei.com>
> Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; Xiexiangyou
> <xiexiangyou@huawei.com>; imammedo@redhat.com;
> qemu-devel@nongnu.org
> Subject: Re: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
>
> On Fri, Feb 21, 2020 at 02:35:12PM +0800, Yubo Miao wrote:
> > From: miaoyubo <miaoyubo@huawei.com>
> >
> > Currently, pxb-pcie could be defined by the cmdline like
> > --device pxb-pcie,id=pci.9,bus_nr=128 However pxb-pcie is not
> > described in acpi tables for arm.
> >
> > The formal two patches support pxb-pcie for arm, escpcially the
> > specification for pxb-pcie in DSDT table.
> >
> > Add a testcase to make sure the ACPI table is correct for guest.
> >
> > Signed-off-by: miaoyubo <miaoyubo@huawei.com>
>
>
> Please look at the top of tests/qtest/bios-tables-test.c for how to add or
> update tests.
>
Thanks for replying, I didn't notice that, I would follow the steps to rebuild this patch.
> > ---
> > tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes
> > tests/qtest/bios-tables-test.c | 54 +++++++++++++++++++++++++++++----
> > 2 files changed, 48 insertions(+), 6 deletions(-) create mode 100644
> > tests/data/acpi/virt/DSDT.pxb
> >
> > diff --git a/tests/data/acpi/virt/DSDT.pxb
> > b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index
> >
> 0000000000000000000000000000000000000000..4eea3192c75ff28f7054d626
> a936
> > 3ca025b6c0ad
> > GIT binary patch
>
> I can't read this.
>
I just have a question that is:
I just rebuild this aml with tests/data/acpi/rebuild-expected-aml.sh
and git send it or send the aml with attachment?
> > literal 34209
> >
> zcmeI*cXU+szJ~D)1PGxe5PG+us9-{<Do8R35G4>YGz}UAMT!L#ks?x*Dx!d5hoIP
> d
> >
> z?}}o>iWL;GW5HgrlKbvVM&HM??^)~qbMIProvd|8p2_U*%qO!m?AgcPkRQ(<w
> r)WX
> >
> zR3DKyBsMVKK5tZUEMJ#Z3xXj0I{cizY-H-_vUpxu>HL<ltgNimvVn#9^>bszg^Hd*
> >
> zYT59@{GfDxK}u{$QSzH5MFX?4va_qcnOYVriD$G-YqqdX5KgQUqzA#0T0ymH9a
> J-P
> > zt=#;Qdf_)p=V$jH6t9{xXmH68P3ev)8EFlwrs(=X$_(9dxJh>6UU8FZi5vcVla%Bp
> >
> zz50)g^-pXvw4i9XAYFAU@nN}Xb+t___n%u<uhU$chBua*GNL5;Gf3Q8mfgX>w)`
> 8L
> >
> z7F4goX88!*;pB+$X8&bG_2BOj*;OO*!h6xx&B+mI)uU#l*o>||BPVi3ji?#5Y(|dH
> >
> z=oUF6C2B^h&FJPcx<}5a88su#W_0%%JtAk+ikeZ+X7unGJtJq-j+)WHX7uzKy&`9
> %
>
> ...
Regards,
Miao
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
2020-02-22 9:40 ` miaoyubo
@ 2020-02-23 21:25 ` Michael S. Tsirkin
0 siblings, 0 replies; 9+ messages in thread
From: Michael S. Tsirkin @ 2020-02-23 21:25 UTC (permalink / raw)
To: miaoyubo; +Cc: peter.maydell, imammedo, qemu-devel, Xiexiangyou, shannon.zhaosl
On Sat, Feb 22, 2020 at 09:40:07AM +0000, miaoyubo wrote:
>
> > -----Original Message-----
> > From: Michael S. Tsirkin [mailto:mst@redhat.com]
> > Sent: Friday, February 21, 2020 7:19 PM
> > To: miaoyubo <miaoyubo@huawei.com>
> > Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; Xiexiangyou
> > <xiexiangyou@huawei.com>; imammedo@redhat.com;
> > qemu-devel@nongnu.org
> > Subject: Re: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm
> >
> > On Fri, Feb 21, 2020 at 02:35:12PM +0800, Yubo Miao wrote:
> > > From: miaoyubo <miaoyubo@huawei.com>
> > >
> > > Currently, pxb-pcie could be defined by the cmdline like
> > > --device pxb-pcie,id=pci.9,bus_nr=128 However pxb-pcie is not
> > > described in acpi tables for arm.
> > >
> > > The formal two patches support pxb-pcie for arm, escpcially the
> > > specification for pxb-pcie in DSDT table.
> > >
> > > Add a testcase to make sure the ACPI table is correct for guest.
> > >
> > > Signed-off-by: miaoyubo <miaoyubo@huawei.com>
> >
> >
> > Please look at the top of tests/qtest/bios-tables-test.c for how to add or
> > update tests.
> >
>
> Thanks for replying, I didn't notice that, I would follow the steps to rebuild this patch.
>
> > > ---
> > > tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes
> > > tests/qtest/bios-tables-test.c | 54 +++++++++++++++++++++++++++++----
> > > 2 files changed, 48 insertions(+), 6 deletions(-) create mode 100644
> > > tests/data/acpi/virt/DSDT.pxb
> > >
> > > diff --git a/tests/data/acpi/virt/DSDT.pxb
> > > b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index
> > >
> > 0000000000000000000000000000000000000000..4eea3192c75ff28f7054d626
> > a936
> > > 3ca025b6c0ad
> > > GIT binary patch
> >
> > I can't read this.
> >
>
> I just have a question that is:
> I just rebuild this aml with tests/data/acpi/rebuild-expected-aml.sh
> and git send it or send the aml with attachment?
git send it pls
> > > literal 34209
> > >
> > zcmeI*cXU+szJ~D)1PGxe5PG+us9-{<Do8R35G4>YGz}UAMT!L#ks?x*Dx!d5hoIP
> > d
> > >
> > z?}}o>iWL;GW5HgrlKbvVM&HM??^)~qbMIProvd|8p2_U*%qO!m?AgcPkRQ(<w
> > r)WX
> > >
> > zR3DKyBsMVKK5tZUEMJ#Z3xXj0I{cizY-H-_vUpxu>HL<ltgNimvVn#9^>bszg^Hd*
> > >
> > zYT59@{GfDxK}u{$QSzH5MFX?4va_qcnOYVriD$G-YqqdX5KgQUqzA#0T0ymH9a
> > J-P
> > > zt=#;Qdf_)p=V$jH6t9{xXmH68P3ev)8EFlwrs(=X$_(9dxJh>6UU8FZi5vcVla%Bp
> > >
> > zz50)g^-pXvw4i9XAYFAU@nN}Xb+t___n%u<uhU$chBua*GNL5;Gf3Q8mfgX>w)`
> > 8L
> > >
> > z7F4goX88!*;pB+$X8&bG_2BOj*;OO*!h6xx&B+mI)uU#l*o>||BPVi3ji?#5Y(|dH
> > >
> > z=oUF6C2B^h&FJPcx<}5a88su#W_0%%JtAk+ikeZ+X7unGJtJq-j+)WHX7uzKy&`9
> > %
> >
> > ...
>
> Regards,
> Miao
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-02-23 21:26 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-21 6:35 [RFC v3 0/3] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
2020-02-21 6:35 ` [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Yubo Miao
2020-02-21 6:35 ` [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Yubo Miao
2020-02-21 11:17 ` Michael S. Tsirkin
2020-02-22 9:37 ` miaoyubo
2020-02-21 6:35 ` [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie " Yubo Miao
2020-02-21 11:19 ` Michael S. Tsirkin
2020-02-22 9:40 ` miaoyubo
2020-02-23 21:25 ` Michael S. Tsirkin
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