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* [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash
@ 2020-02-23 23:30 Philippe Mathieu-Daudé
  2020-02-23 23:30 ` [PATCH v2 1/2] hw/arm/integratorcp: Map the audio codec controller Philippe Mathieu-Daudé
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-23 23:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: Peter Maydell, qemu-arm, Philippe Mathieu-Daudé

While looking whether Thomas's test patch [*] requires a respin
or not, I noticed we could complete the integrator model.
Thomas patch still applies properly ;)

Since v1:
- Added uncommitted Kconfig
- Use hobbyist git-identity

[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg675828.html

Philippe Mathieu-Daudé (2):
  hw/arm/integratorcp: Map the audio codec controller
  hw/arm/integratorcp: Map a CFI parallel flash

 hw/arm/integratorcp.c | 12 ++++++++++++
 hw/arm/Kconfig        |  2 ++
 2 files changed, 14 insertions(+)

-- 
2.21.1



^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 1/2] hw/arm/integratorcp: Map the audio codec controller
  2020-02-23 23:30 [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash Philippe Mathieu-Daudé
@ 2020-02-23 23:30 ` Philippe Mathieu-Daudé
  2020-02-23 23:30 ` [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash Philippe Mathieu-Daudé
  2020-02-25 12:48 ` [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and " Peter Maydell
  2 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-23 23:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: Peter Maydell, qemu-arm, Philippe Mathieu-Daudé

The Linux kernel displays errors why trying to detect the PL041
audio interface:

  Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
  CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
  CPU: VIVT data cache, VIVT instruction cache
  OF: fdt: Machine model: ARM Integrator/CP
  ...
  OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000

Since we have it already modelled, simply plug it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Kconfig change was not committed
---
 hw/arm/integratorcp.c | 1 +
 hw/arm/Kconfig        | 1 +
 2 files changed, 2 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 0cd94d9f09..59804140cd 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -644,6 +644,7 @@ static void integratorcp_init(MachineState *machine)
                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
     qdev_connect_gpio_out(dev, 1,
                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
+    sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
 
     if (nd_table[0].used)
         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3d86691ae0..61635f52c4 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -69,6 +69,7 @@ config INTEGRATOR
     select INTEGRATOR_DEBUG
     select PL011 # UART
     select PL031 # RTC
+    select PL041 # audio
     select PL050 # keyboard/mouse
     select PL110 # pl111 LCD controller
     select PL181 # display
-- 
2.21.1



^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash
  2020-02-23 23:30 [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash Philippe Mathieu-Daudé
  2020-02-23 23:30 ` [PATCH v2 1/2] hw/arm/integratorcp: Map the audio codec controller Philippe Mathieu-Daudé
@ 2020-02-23 23:30 ` Philippe Mathieu-Daudé
  2020-02-25 12:47   ` Peter Maydell
  2020-02-25 12:48 ` [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and " Peter Maydell
  2 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-23 23:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: Peter Maydell, qemu-arm, Philippe Mathieu-Daudé

The Linux kernel displays errors why trying to detect the flash:

  Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
  CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
  CPU: VIVT data cache, VIVT instruction cache
  OF: fdt: Machine model: ARM Integrator/CP
  ...
  of-flash 24000000.flash: Integrator/CP flash protection
  of-flash 24000000.flash: do_map_probe() failed for type cfi_probe
  of-flash 24000000.flash: do_map_probe() failed

Since we have a CFI pflash model available, wire it.
The kernel properly detects it:

  of-flash 24000000.flash: Integrator/CP flash protection
  24000000.flash: Found 1 x32 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
  Intel/Sharp Extended Query Table at 0x0031
  Using buffer write method

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Kconfig change was not committed

RFC because I have no idea of the flash model, its ID code, and which
default CFI family (1 or 2).
---
 hw/arm/integratorcp.c | 11 +++++++++++
 hw/arm/Kconfig        |  1 +
 2 files changed, 12 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 59804140cd..40cedfd55a 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -8,6 +8,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
@@ -24,6 +25,7 @@
 #include "hw/char/pl011.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
+#include "hw/block/flash.h"
 
 #define TYPE_INTEGRATOR_CM "integrator_core"
 #define INTEGRATOR_CM(obj) \
@@ -589,6 +591,7 @@ static void integratorcp_init(MachineState *machine)
     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
     qemu_irq pic[32];
     DeviceState *dev, *sic, *icp;
+    DriveInfo *dinfo;
     int i;
 
     cpuobj = object_new(machine->cpu_type);
@@ -646,6 +649,14 @@ static void integratorcp_init(MachineState *machine)
                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
     sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
 
+    dinfo = drive_get(IF_PFLASH, 0, 0);
+    if (!pflash_cfi01_register(0x24000000, "pflash", 16 * MiB,
+                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                               64 * KiB, 4, 0, 0, 0, 0, 0)) {
+        error_report("Error registering flash memory");
+        exit(1);
+    }
+
     if (nd_table[0].used)
         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 61635f52c4..7f179f960f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -73,6 +73,7 @@ config INTEGRATOR
     select PL050 # keyboard/mouse
     select PL110 # pl111 LCD controller
     select PL181 # display
+    select PFLASH_CFI01
     select SMC91C111
 
 config MAINSTONE
-- 
2.21.1



^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash
  2020-02-23 23:30 ` [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash Philippe Mathieu-Daudé
@ 2020-02-25 12:47   ` Peter Maydell
  2020-02-25 14:09     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2020-02-25 12:47 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé; +Cc: qemu-arm, QEMU Developers

On Sun, 23 Feb 2020 at 23:30, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The Linux kernel displays errors why trying to detect the flash:
>
>   Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
>   CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
>   CPU: VIVT data cache, VIVT instruction cache
>   OF: fdt: Machine model: ARM Integrator/CP
>   ...
>   of-flash 24000000.flash: Integrator/CP flash protection
>   of-flash 24000000.flash: do_map_probe() failed for type cfi_probe
>   of-flash 24000000.flash: do_map_probe() failed
>
> Since we have a CFI pflash model available, wire it.
> The kernel properly detects it:
>
>   of-flash 24000000.flash: Integrator/CP flash protection
>   24000000.flash: Found 1 x32 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
>   Intel/Sharp Extended Query Table at 0x0031
>   Using buffer write method
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: Kconfig change was not committed
>
> RFC because I have no idea of the flash model, its ID code, and which
> default CFI family (1 or 2).

ARM DUI 0102G ("ARM Firmware Suite Reference Guide") helpfully has
a few details:

Device                                  Size  Organization     Flash part
Integrator/AP Boot flash               512KB  1x512K block     Atmel AT49LV040
Integrator/AP Application flash         32MB  256x128K blocks  Intel 28F320S3
Integrator/CP Boot/Application flash    16MB  64x256K blocks   Intel 28F640J3A

(of which we only model the CP.) With luck that's enough to
nail down the relevant device properties.

> @@ -646,6 +649,14 @@ static void integratorcp_init(MachineState *machine)
>                            qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
>      sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
>
> +    dinfo = drive_get(IF_PFLASH, 0, 0);
> +    if (!pflash_cfi01_register(0x24000000, "pflash", 16 * MiB,
> +                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
> +                               64 * KiB, 4, 0, 0, 0, 0, 0)) {
> +        error_report("Error registering flash memory");
> +        exit(1);
> +    }

Passing a 'width' argument of 0 means "weird legacy backcompat
device that's a bad emulation of a pair of 16-bit devices";
we should avoid that for new code, and instead set
the width and device-width properties to whatever the
hardware has. (This in turn means you can't use the old
pflash_cfi01_register() function.)

Should we be using blk_by_legacy_dinfo() in new code?
I'm not sure if there's a better way to do this if we don't
need to maintain back-compat with old commandline specifications
of the flash contents.

thanks
-- PMM


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash
  2020-02-23 23:30 [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash Philippe Mathieu-Daudé
  2020-02-23 23:30 ` [PATCH v2 1/2] hw/arm/integratorcp: Map the audio codec controller Philippe Mathieu-Daudé
  2020-02-23 23:30 ` [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash Philippe Mathieu-Daudé
@ 2020-02-25 12:48 ` Peter Maydell
  2 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2020-02-25 12:48 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé; +Cc: qemu-arm, QEMU Developers

On Sun, 23 Feb 2020 at 23:30, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> While looking whether Thomas's test patch [*] requires a respin
> or not, I noticed we could complete the integrator model.
> Thomas patch still applies properly ;)
>
> Since v1:
> - Added uncommitted Kconfig
> - Use hobbyist git-identity
>
> [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg675828.html
>
> Philippe Mathieu-Daudé (2):
>   hw/arm/integratorcp: Map the audio codec controller
>   hw/arm/integratorcp: Map a CFI parallel flash

I've left comments on patch 2, and taken patch 1 into
target-arm.next.

thanks
-- PMM


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash
  2020-02-25 12:47   ` Peter Maydell
@ 2020-02-25 14:09     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-25 14:09 UTC (permalink / raw)
  To: Peter Maydell, Philippe Mathieu-Daudé; +Cc: qemu-arm, QEMU Developers

On 2/25/20 1:47 PM, Peter Maydell wrote:
> On Sun, 23 Feb 2020 at 23:30, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> The Linux kernel displays errors why trying to detect the flash:
>>
>>    Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
>>    CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
>>    CPU: VIVT data cache, VIVT instruction cache
>>    OF: fdt: Machine model: ARM Integrator/CP
>>    ...
>>    of-flash 24000000.flash: Integrator/CP flash protection
>>    of-flash 24000000.flash: do_map_probe() failed for type cfi_probe
>>    of-flash 24000000.flash: do_map_probe() failed
>>
>> Since we have a CFI pflash model available, wire it.
>> The kernel properly detects it:
>>
>>    of-flash 24000000.flash: Integrator/CP flash protection
>>    24000000.flash: Found 1 x32 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
>>    Intel/Sharp Extended Query Table at 0x0031
>>    Using buffer write method
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> v2: Kconfig change was not committed
>>
>> RFC because I have no idea of the flash model, its ID code, and which
>> default CFI family (1 or 2).
> 
> ARM DUI 0102G ("ARM Firmware Suite Reference Guide") helpfully has
> a few details:
> 
> Device                                  Size  Organization     Flash part
> Integrator/AP Boot flash               512KB  1x512K block     Atmel AT49LV040
> Integrator/AP Application flash         32MB  256x128K blocks  Intel 28F320S3
> Integrator/CP Boot/Application flash    16MB  64x256K blocks   Intel 28F640J3A
> 
> (of which we only model the CP.) With luck that's enough to
> nail down the relevant device properties.

"Intel 28F640J3A" is everything we need, thanks!

> 
>> @@ -646,6 +649,14 @@ static void integratorcp_init(MachineState *machine)
>>                             qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
>>       sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
>>
>> +    dinfo = drive_get(IF_PFLASH, 0, 0);
>> +    if (!pflash_cfi01_register(0x24000000, "pflash", 16 * MiB,
>> +                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
>> +                               64 * KiB, 4, 0, 0, 0, 0, 0)) {
>> +        error_report("Error registering flash memory");
>> +        exit(1);
>> +    }
> 
> Passing a 'width' argument of 0 means "weird legacy backcompat
> device that's a bad emulation of a pair of 16-bit devices";
> we should avoid that for new code, and instead set
> the width and device-width properties to whatever the
> hardware has. (This in turn means you can't use the old
> pflash_cfi01_register() function.)

OK I'll try to document that.

> Should we be using blk_by_legacy_dinfo() in new code?
> I'm not sure if there's a better way to do this if we don't
> need to maintain back-compat with old commandline specifications
> of the flash contents.
> 
> thanks
> -- PMM
> 



^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-02-25 14:21 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-23 23:30 [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and parallel flash Philippe Mathieu-Daudé
2020-02-23 23:30 ` [PATCH v2 1/2] hw/arm/integratorcp: Map the audio codec controller Philippe Mathieu-Daudé
2020-02-23 23:30 ` [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash Philippe Mathieu-Daudé
2020-02-25 12:47   ` Peter Maydell
2020-02-25 14:09     ` Philippe Mathieu-Daudé
2020-02-25 12:48 ` [PATCH v2 0/2] hw/arm/integratorcp: Map Audio controller and " Peter Maydell

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