* [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support
@ 2020-02-24 15:32 Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
` (17 more replies)
0 siblings, 18 replies; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
v17: Had to rebase the whole series.
v18: Resent whole series as new patch was introduced.
Stanislav Lisovskiy (8):
drm/i915: Start passing latency as parameter
drm/i915: Introduce skl_plane_wm_level accessor.
drm/i915: Add intel_bw_get_*_state helpers
drm/i915: Introduce more *_state_changed indicators
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Added required new PCode commands
drm/i915: Restrict qgv points which don't have enough bandwidth.
drm/i915: Enable SAGV support for Gen12
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +
drivers/gpu/drm/i915/display/intel_bw.c | 211 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 36 ++
drivers/gpu/drm/i915/display/intel_display.c | 141 ++++-
.../drm/i915/display/intel_display_types.h | 34 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 581 +++++++++++++++---
drivers/gpu/drm/i915/intel_pm.h | 4 +-
drivers/gpu/drm/i915/intel_sideband.c | 2 +
10 files changed, 864 insertions(+), 154 deletions(-)
--
2.24.1.485.gad05a3d8e5
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-27 16:28 ` Ville Syrjälä
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
` (16 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffac0b862ca5..d6933e382657 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
drm_WARN_ON(&dev_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4978,12 +4981,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5112,9 +5115,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-27 15:51 ` Ville Syrjälä
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
` (15 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++++-----------
1 file changed, 81 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6933e382657..e1d167429489 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane->id];
+
+ return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
u64 total_data_rate;
- enum plane_id plane_id;
+ struct intel_plane *plane;
int num_active;
u64 plane_data_rate[I915_MAX_PLANES] = {};
u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
@@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
+
+ if (plane->id == PLANE_CURSOR) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* watermark level, plus an extra share of the leftover blocks
* proportional to its relative data rate.
*/
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
- if (plane_id == PLANE_CURSOR)
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
+
+ if (plane->id == PLANE_CURSOR)
continue;
/*
@@ -4665,22 +4688,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
if (total_data_rate == 0)
break;
- rate = plane_data_rate[plane_id];
+ rate = plane_data_rate[plane->id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane->id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
if (total_data_rate == 0)
break;
- rate = uv_plane_data_rate[plane_id];
+ rate = uv_plane_data_rate[plane->id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane->id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4688,29 +4711,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
/* Set the actual DDB start/end points for each plane */
start = alloc->start;
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
struct skl_ddb_entry *plane_alloc =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ &crtc_state->wm.skl.plane_ddb_y[plane->id];
struct skl_ddb_entry *uv_plane_alloc =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
+ &crtc_state->wm.skl.plane_ddb_uv[plane->id];
- if (plane_id == PLANE_CURSOR)
+ if (plane->id == PLANE_CURSOR)
continue;
/* Gen11+ uses a separate plane for UV watermarks */
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
+ INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
/* Leave disabled planes at (0,0) */
- if (total[plane_id]) {
+ if (total[plane->id]) {
plane_alloc->start = start;
- start += total[plane_id];
+ start += total[plane->id];
plane_alloc->end = start;
}
- if (uv_total[plane_id]) {
+ if (uv_total[plane->id]) {
uv_plane_alloc->start = start;
- start += uv_total[plane_id];
+ start += uv_total[plane->id];
uv_plane_alloc->end = start;
}
}
@@ -4722,9 +4745,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* that aren't actually possible.
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane->id];
+
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
/*
* We only disable the watermarks for each plane if
@@ -4738,9 +4768,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane->id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane->id])
+ memset(&wm->wm[level], 0,
+ sizeof(struct skl_wm_level));
/*
* Wa_1408961008:icl, ehl
@@ -4748,9 +4779,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ 0, false);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -4759,11 +4795,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* Go back and disable the transition watermark if it turns out we
* don't have enough DDB blocks for it.
*/
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane->id];
- if (wm->trans_wm.plane_res_b >= total[plane_id])
+ if (wm->trans_wm.plane_res_b >= total[plane->id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
}
@@ -5354,10 +5390,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
const struct skl_ddb_entry *ddb_uv =
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+ const struct skl_wm_level *wm_level;
for (level = 0; level <= max_level; level++) {
+ wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5388,10 +5427,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.optimal.planes[plane_id];
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_wm_level *wm_level;
for (level = 0; level <= max_level; level++) {
+ wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-27 15:53 ` Ville Syrjälä
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators Stanislav Lisovskiy
` (14 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..bdad7476dc7b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
-intel_atomic_get_bw_state(struct intel_atomic_state *state)
+struct intel_bw_state *
+intel_bw_get_old_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_bw_get_new_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_bw_get_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
@@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
+ bw_state = intel_bw_get_state(state);
if (IS_ERR(bw_state))
return PTR_ERR(bw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..b5f61463922f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_bw_get_old_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_bw_get_new_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_bw_get_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-25 14:57 ` Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
` (13 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
The reasoning behind this is such that current dependencies
in the code are rather implicit in a sense, we have to constantly
check a bunch of different bits like state->modeset,
state->active_pipe_changes, which sometimes can indicate counter
intuitive changes.
By introducing more fine grained state change tracking we achieve
better readability and dependency maintenance for the code.
For example it is no longer needed to evaluate active_pipe_changes
to understand if there were changes for wm/ddb - lets just have
a correspondent bit in a state, called ddb_state_changed.
active_pipe_changes just indicate whether there was some pipe added
or removed. Then we evaluate if wm/ddb had been changed.
Same for sagv/bw state. ddb changes may or may not affect if out
bandwidth constraints have been changed.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
drivers/gpu/drm/i915/display/intel_bw.c | 2 ++
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
.../drm/i915/display/intel_display_types.h | 32 ++++++++++++-------
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
5 files changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index d043057d2fa0..0db9c66d3c0f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
+ state->ddb_state_changed = false;
+ state->bw_state_changed = false;
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bdad7476dc7b..d07918b4a3d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -468,6 +468,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (ret)
return ret;
+ state->bw_state_changed = true;
+
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 48fe3d2e0fa3..530a25e1ad1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15509,8 +15509,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15534,7 +15536,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_encoders_update_prepare(state);
/* Enable all new slices, we might need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_pre_update(state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15591,7 +15593,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Disable all slices, we don't need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_post_update(state);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -15610,8 +15612,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(state)
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d8a64305464..12b47ba3c68d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -471,16 +471,6 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- /*
- * Does this transaction change the pipes that are active? This mask
- * tracks which CRTC's have changed their active state at the end of
- * the transaction (not counting the temporary disable during modesets).
- * This mask should only be non-zero when intel_state->modeset is true,
- * but the converse is not necessarily true; simply changing a mode may
- * not flip the final active status of any CRTC's
- */
- u8 active_pipe_changes;
-
u8 active_pipes;
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
@@ -494,10 +484,30 @@ struct intel_atomic_state {
bool rps_interactive;
/*
- * active_pipes
+ * active pipes
*/
bool global_state_changed;
+ /*
+ * Does this transaction change the pipes that are active? This mask
+ * tracks which CRTC's have changed their active state at the end of
+ * the transaction (not counting the temporary disable during modesets).
+ * This mask should only be non-zero when intel_state->modeset is true,
+ * but the converse is not necessarily true; simply changing a mode may
+ * not flip the final active status of any CRTC's
+ */
+ u8 active_pipe_changes;
+
+ /*
+ * More granular change indicator for ddb changes
+ */
+ bool ddb_state_changed;
+
+ /*
+ * More granular change indicator for bandwidth state changes
+ */
+ bool bw_state_changed;
+
/* Number of enabled DBuf slices */
u8 enabled_dbuf_slices_mask;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1d167429489..7a76b2ed7a87 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
* that changes the active CRTC list or do modeset would need to
* grab _all_ crtc locks, including the one we currently hold.
*/
- if (!intel_state->active_pipe_changes && !intel_state->modeset) {
+ if (!intel_state->ddb_state_changed) {
/*
* alloc may be cleared by clear_intel_crtc_state,
* copy from old state to be sure
@@ -5787,6 +5787,8 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return PTR_ERR(plane_state);
new_crtc_state->update_planes |= BIT(plane_id);
+
+ state->ddb_state_changed = true;
}
return 0;
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-25 14:59 ` Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 6/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
` (12 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 27 +-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 441 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
5 files changed, 448 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index b5f61463922f..c32b5285c12f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_mask;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 530a25e1ad1c..b355be32ed2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13977,7 +13977,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -14032,7 +14035,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -15509,9 +15515,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (state->bw_state_changed) {
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(dev_priv))
+ intel_disable_sagv(dev_priv);
+ }
}
intel_modeset_verify_disabled(dev_priv, state);
@@ -15612,9 +15620,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->bw_state_changed) {
- if (intel_can_enable_sagv(state)
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(dev_priv))
+ intel_enable_sagv(dev_priv);
+ }
}
drm_atomic_helper_commit_hw_done(&state->base);
@@ -15767,7 +15777,6 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
-
dev_priv->active_pipes = state->active_pipes;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 12b47ba3c68d..289461571a0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -664,6 +664,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a76b2ed7a87..853fc9e9084d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -42,6 +42,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3620,7 +3621,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3743,39 +3744,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+ enum pipe pipe)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
-
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3802,13 +3788,181 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
return false;
+ }
}
return true;
}
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ enum pipe pipe;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ if (state->active_pipes != 1) {
+ new_bw_state->pipe_sagv_mask = 0;
+ DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+ return;
+ }
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+
+ if (skl_can_enable_sagv_on_pipe(state, pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+ }
+}
+
+static void intel_compute_sagv_mask(struct intel_atomic_state *state,
+ int total_affected_planes)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *new_bw_state;
+ struct intel_bw_state *old_bw_state;
+
+ /*
+ * No active_pipe_changes and no wm/ddb changes means
+ * we can just bail out.
+ */
+ if (state->active_pipe_changes == 0 && state->ddb_state_changed == false)
+ return;
+
+ /*
+ * If we are here - means either active_pipes config had changed,
+ * or watermarks/ddb has been changed, which means most likely
+ * we had crtcs added to the state(at least state is read locked)
+ * and we definitely need to recalculate SAGV state now.
+ */
+ new_bw_state = intel_bw_get_state(state);
+ old_bw_state = intel_bw_get_old_state(state);
+
+ if (IS_ERR(new_bw_state) || IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ new_bw_state->sagv_calculated = false;
+
+ /*
+ * Now once we got wm levels calculated,
+ * check if we can have SAGV.
+ */
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_compute_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_compute_sagv_mask(state);
+ else
+ skl_compute_sagv_mask(state);
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+
+ state->bw_state_changed = true;
+
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return;
+ }
+ }
+}
+
+static bool intel_calculate_sagv_result(struct drm_i915_private *dev_priv,
+ struct intel_bw_state *bw_state)
+{
+ bool sagv_result = true;
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ /*
+ * TODO: We are depending on active_pipes here,
+ * probably it should be part of some other global state
+ * obj, like modeset_state or smth, which we should depend on.
+ * Don't want to clone it here, really.
+ */
+ int active_pipe_bit = dev_priv->active_pipes & BIT(pipe);
+
+ if (active_pipe_bit) {
+ if ((bw_state->pipe_sagv_mask & BIT(pipe)) == 0) {
+ sagv_result = false;
+ break;
+ }
+ }
+ }
+
+ return sagv_result;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return false;
+ }
+
+ if (!intel_has_sagv(dev_priv)) {
+ DRM_DEBUG_KMS("No SAGV support detected\n");
+ return false;
+ }
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
@@ -3842,6 +3996,35 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
return ddb_size;
}
+/*
+ * To be used after we swap state
+ */
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv)
+{
+ struct intel_global_state *global_state;
+ struct intel_bw_state *bw_state;
+
+ global_state = dev_priv->bw_obj.state;
+ if (IS_ERR(global_state)) {
+ WARN(1, "Could not get global state\n");
+ return false;
+ }
+
+ /*
+ * TODO: Should we still may be lock global state here?
+ */
+ bw_state = to_intel_bw_state(global_state);
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
u32 active_pipes);
@@ -4028,6 +4211,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
u32 latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4554,12 +4738,92 @@ skl_plane_wm_level(struct intel_plane *plane,
int level,
int color_plane)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
+ if (!level) {
+ bool can_sagv = false;
+
+ /*
+ * If we haven't yet swapped our state, we should use
+ * the state to determine SAGV, otherwise use global
+ * state as atomic state pointer might become stale
+ * and zeroed out.
+ */
+ if (state) {
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ can_sagv = intel_can_enable_sagv_for_state(intel_state);
+ } else {
+ can_sagv = intel_can_enable_sagv(dev_priv);
+ }
+
+ if (can_sagv)
+ return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+ }
+
return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return -ENOSPC;
+ }
+ }
+ DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+ blocks, alloc_size);
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5143,11 +5407,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -5158,6 +5430,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5232,7 +5525,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5254,7 +5547,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5585,9 +5878,24 @@ skl_print_wm_changes(struct intel_atomic_state *state)
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
+ const struct skl_wm_level *old_wm_level, *new_wm_level;
+ u16 old_plane_res_l, new_plane_res_l;
+ u8 old_plane_res_b, new_plane_res_b;
+ u16 old_min_ddb_alloc, new_min_ddb_alloc;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
+ old_wm_level = skl_plane_wm_level(plane, old_crtc_state, 0, false);
+ new_wm_level = skl_plane_wm_level(plane, new_crtc_state, 0, false);
+
+ old_plane_res_l = old_wm_level->plane_res_l;
+ old_plane_res_b = old_wm_level->plane_res_b;
+
+ new_plane_res_l = new_wm_level->plane_res_l;
+ new_plane_res_b = new_wm_level->plane_res_b;
+
+ old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
+ new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue;
@@ -5611,7 +5919,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+ enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5621,7 +5929,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+ enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5635,12 +5943,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+ old_plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+ new_plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5650,12 +5958,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+ old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
- new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+ new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5755,7 +6063,8 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
* default value of the watermarks registers is not zero.
*/
static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+ struct intel_crtc *crtc,
+ int *num_affected_planes)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct intel_crtc_state *old_crtc_state =
@@ -5764,6 +6073,8 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane *plane;
+ *num_affected_planes = 0;
+
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
struct intel_plane_state *plane_state;
enum plane_id plane_id = plane->id;
@@ -5789,11 +6100,65 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
new_crtc_state->update_planes |= BIT(plane_id);
state->ddb_state_changed = true;
+ *num_affected_planes += 1;
}
return 0;
}
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ int ret;
+ int i;
+ struct intel_plane *plane;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ int pipe_bit = BIT(crtc->pipe);
+ bool skip = true;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+ const struct skl_plane_wm *old_wm, *new_wm;
+ bool equal_wm;
+
+ old_wm = &old_crtc_state->wm.skl.optimal.planes[plane_id];
+ new_wm = &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ equal_wm = skl_plane_wm_equals(dev_priv, old_wm, new_wm);
+
+ if (!equal_wm) {
+ skip = false;
+ break;
+ }
+ }
+
+ /*
+ * Check if wm levels are actually the same as for previous
+ * state, which means we can just skip doing this long check
+ * and just copy correspondent bit from previous state.
+ */
+ if (skip)
+ continue;
+
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state);
+ if (!ret)
+ new_bw_state->pipe_sagv_mask |= pipe_bit;
+ else
+ new_bw_state->pipe_sagv_mask &= ~pipe_bit;
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5801,6 +6166,7 @@ skl_compute_wm(struct intel_atomic_state *state)
struct intel_crtc_state *new_crtc_state;
struct intel_crtc_state *old_crtc_state;
int ret, i;
+ int affected_planes; int total_affected_planes = 0;
ret = skl_ddb_add_affected_pipes(state);
if (ret)
@@ -5817,11 +6183,15 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
- ret = skl_wm_add_affected_planes(state, crtc);
+ ret = skl_wm_add_affected_planes(state, crtc, &affected_planes);
if (ret)
return ret;
+
+ total_affected_planes += affected_planes;
}
+ intel_compute_sagv_mask(state, total_affected_planes);
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5941,6 +6311,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..561a17a5d4e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 6/8] drm/i915: Added required new PCode commands
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
` (11 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..b3924e9d25bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8997,6 +8997,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9018,6 +9019,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -9030,6 +9032,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 6/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-25 15:00 ` Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
` (10 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 180 +++++++++++++------
drivers/gpu/drm/i915/display/intel_bw.h | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 114 +++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 3 +
4 files changed, 254 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d07918b4a3d5..8f1de95c7c19 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
if (qgv_point >= bi->num_qgv_points)
return UINT_MAX;
- if (num_planes >= bi->num_planes)
+ if (num_planes >= bi->num_planes || !num_planes)
return bi->deratedbw[qgv_point];
}
@@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -418,11 +423,16 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -447,43 +457,113 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_bw_get_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(&dev_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(&bw_state->base);
- if (ret)
+ /*
+ * TODO: Should we just call intel_atomic_serialize_global_state here?
+ * we anyway already have different data rates and this call is
+ * is almost similar, except that it doesn't call duplicate_state
+ * hook.
+ */
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not lock global state\n");
return ret;
+ }
- state->bw_state_changed = true;
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth for display configuration.\n");
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv_for_state(state)) {
+ allowed_points = 1 << max_bw_point;
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+ state, new_bw_state->qgv_points_mask);
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ DRM_DEBUG_KMS("Could not get old bw state!\n");
+ return PTR_ERR(old_bw_state);
+ }
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+
+ state->bw_state_changed = true;
+
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index c32b5285c12f..b3522389a181 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -36,6 +36,13 @@ struct intel_bw_state {
*/
bool can_sagv;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
@@ -56,5 +63,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b355be32ed2f..a762c97cd6c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15473,6 +15473,105 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ unsigned int mask = (1 << num_qgv_points) - 1;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get old bw_state!\n");
+ return;
+ }
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ WARN_ON(new_mask == mask);
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not mask required qgv points(%d)\n",
+ ret);
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not unmask required qgv points(%d)\n",
+ ret);
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -15506,6 +15605,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+ * Now we need to check if SAGV needs to be disabled(i.e QGV points
+ * modified even, when no modeset is done(for example plane updates
+ * can now trigger that).
+ */
+ if ((INTEL_GEN(dev_priv) >= 11))
+ if (state->bw_state_changed)
+ intel_qgv_points_mask(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
@@ -15620,10 +15728,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (INTEL_GEN(dev_priv) < 11) {
- if (state->bw_state_changed) {
+ if (state->bw_state_changed) {
+ if (INTEL_GEN(dev_priv) < 11) {
if (intel_can_enable_sagv(dev_priv))
intel_enable_sagv(dev_priv);
+ } else {
+ intel_qgv_points_unmask(state);
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9928d00ea0b1..1143f67bba0a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -841,6 +841,9 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_MAX,
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define INTEL_PIPE_CRC_ENTRIES_NR 128
struct intel_pipe_crc {
spinlock_t lock;
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 8/8] drm/i915: Enable SAGV support for Gen12
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-02-24 15:32 ` Stanislav Lisovskiy
2020-02-24 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
` (9 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-24 15:32 UTC (permalink / raw)
To: intel-gfx
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 853fc9e9084d..fe2873af7f4b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3624,10 +3624,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (7 preceding siblings ...)
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-02-24 18:37 ` Patchwork
2020-02-24 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (8 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-24 18:37 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
658365e95a33 drm/i915: Start passing latency as parameter
ba654cc920d4 drm/i915: Introduce skl_plane_wm_level accessor.
b339bbdf676c drm/i915: Add intel_bw_get_*_state helpers
4d3ce9ab4bc3 drm/i915: Introduce more *_state_changed indicators
1a4b8e91ea4b drm/i915: Refactor intel_can_enable_sagv
-:357: CHECK:BOOL_COMPARISON: Using comparison to false is error prone
#357: FILE: drivers/gpu/drm/i915/intel_pm.c:3863:
+ if (state->active_pipe_changes == 0 && state->ddb_state_changed == false)
-:394: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#394: FILE: drivers/gpu/drm/i915/intel_pm.c:3900:
+ if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+
total: 0 errors, 0 warnings, 2 checks, 720 lines checked
95a34afc3826 drm/i915: Added required new PCode commands
d9e474c18262 drm/i915: Restrict qgv points which don't have enough bandwidth.
-:357: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#357: FILE: drivers/gpu/drm/i915/display/intel_bw.c:557:
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+
total: 0 errors, 0 warnings, 1 checks, 406 lines checked
a8667395977a drm/i915: Enable SAGV support for Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (8 preceding siblings ...)
2020-02-24 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
@ 2020-02-24 18:39 ` Patchwork
2020-02-24 19:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-24 18:39 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!
Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!
Commit: drm/i915: Add intel_bw_get_*_state helpers
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (9 preceding siblings ...)
2020-02-24 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-02-24 19:04 ` Patchwork
2020-02-26 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev5) Patchwork
` (6 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-24 19:04 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/73856/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7998 -> Patchwork_16691
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16691 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16691, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16691:
### IGT changes ###
#### Possible regressions ####
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_busy@basic@flip}:
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-skl-guc/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-skl-guc/igt@kms_busy@basic@flip.html
- fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-skl-6700k2/igt@kms_busy@basic@flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-skl-6700k2/igt@kms_busy@basic@flip.html
Known issues
------------
Here are the changes found in Patchwork_16691 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][7] -> [INCOMPLETE][8] ([i915#45])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-byt-j1900/igt@gem_close_race@basic-threads.html
- fi-byt-n2820: [PASS][9] -> [INCOMPLETE][10] ([i915#45])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][11] -> [FAIL][12] ([CI#94])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][13] -> [FAIL][14] ([fdo#109635] / [i915#217])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-tgl-y: [PASS][15] -> [DMESG-WARN][16] ([CI#94] / [i915#402]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-tgl-y/igt@prime_vgem@basic-fence-wait-default.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-tgl-y/igt@prime_vgem@basic-fence-wait-default.html
#### Possible fixes ####
* igt@gem_flink_basic@basic:
- fi-tgl-y: [DMESG-WARN][17] ([CI#94] / [i915#402]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-tgl-y/igt@gem_flink_basic@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-tgl-y/igt@gem_flink_basic@basic.html
#### Warnings ####
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [INCOMPLETE][19] ([i915#694] / [i915#816]) -> [TIMEOUT][20] ([fdo#112271] / [i915#1084])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
* igt@runner@aborted:
- fi-byt-j1900: [FAIL][21] ([i915#999]) -> [FAIL][22] ([i915#816])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7998/fi-byt-j1900/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/fi-byt-j1900/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#999]: https://gitlab.freedesktop.org/drm/intel/issues/999
Participating hosts (51 -> 31)
------------------------------
Missing (20): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-cfl-8700k fi-apl-guc fi-kbl-7500u fi-ctg-p8600 fi-bsw-cyan fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u fi-elk-e7500 fi-bsw-kefka fi-skl-lmem fi-byt-clapper fi-skl-6600u fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7998 -> Patchwork_16691
CI-20190529: 20190529
CI_DRM_7998: 7b1bb0188905d180ee11694d9c26c5dd656dc1d1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5463: d519c80219ebe558cd2fa378f26f9d73f9e35310 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16691: a8667395977a27778af8d856121fa030866e3028 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a8667395977a drm/i915: Enable SAGV support for Gen12
d9e474c18262 drm/i915: Restrict qgv points which don't have enough bandwidth.
95a34afc3826 drm/i915: Added required new PCode commands
1a4b8e91ea4b drm/i915: Refactor intel_can_enable_sagv
4d3ce9ab4bc3 drm/i915: Introduce more *_state_changed indicators
b339bbdf676c drm/i915: Add intel_bw_get_*_state helpers
ba654cc920d4 drm/i915: Introduce skl_plane_wm_level accessor.
658365e95a33 drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16691/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators Stanislav Lisovskiy
@ 2020-02-25 14:57 ` Stanislav Lisovskiy
2020-02-27 16:12 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-25 14:57 UTC (permalink / raw)
To: intel-gfx
The reasoning behind this is such that current dependencies
in the code are rather implicit in a sense, we have to constantly
check a bunch of different bits like state->modeset,
state->active_pipe_changes, which sometimes can indicate counter
intuitive changes.
By introducing more fine grained state change tracking we achieve
better readability and dependency maintenance for the code.
For example it is no longer needed to evaluate active_pipe_changes
to understand if there were changes for wm/ddb - lets just have
a correspondent bit in a state, called ddb_state_changed.
active_pipe_changes just indicate whether there was some pipe added
or removed. Then we evaluate if wm/ddb had been changed.
Same for sagv/bw state. ddb changes may or may not affect if out
bandwidth constraints have been changed.
v2: Add support for older Gens in order not to introduce regressions
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
.../drm/i915/display/intel_display_types.h | 32 ++++++++++++-------
drivers/gpu/drm/i915/intel_pm.c | 5 ++-
5 files changed, 62 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index d043057d2fa0..0db9c66d3c0f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
+ state->ddb_state_changed = false;
+ state->bw_state_changed = false;
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bdad7476dc7b..d5be603b8b03 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i, ret;
- /* FIXME earlier gens need some checks too */
- if (INTEL_GEN(dev_priv) < 11)
+ /*
+ * For earlier Gens let's consider bandwidth changed if ddb requirements,
+ * has been changed.
+ */
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->ddb_state_changed) {
+ bw_state = intel_bw_get_state(state);
+ if (IS_ERR(bw_state))
+ return PTR_ERR(bw_state);
+
+ ret = intel_atomic_lock_global_state(&bw_state->base);
+ if (ret)
+ return ret;
+
+ DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
+ state);
+
+ state->bw_state_changed = true;
+ }
return 0;
+ }
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_bw_get_state(state);
+ bw_state = intel_bw_get_state(state);
if (IS_ERR(bw_state))
return PTR_ERR(bw_state);
@@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (ret)
return ret;
+ DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
+
+ state->bw_state_changed = true;
+
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3031e64ee518..137fb645097a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15540,8 +15540,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15565,7 +15567,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_encoders_update_prepare(state);
/* Enable all new slices, we might need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_pre_update(state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15622,7 +15624,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Disable all slices, we don't need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_post_update(state);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -15641,8 +15643,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(state)
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d8a64305464..12b47ba3c68d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -471,16 +471,6 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- /*
- * Does this transaction change the pipes that are active? This mask
- * tracks which CRTC's have changed their active state at the end of
- * the transaction (not counting the temporary disable during modesets).
- * This mask should only be non-zero when intel_state->modeset is true,
- * but the converse is not necessarily true; simply changing a mode may
- * not flip the final active status of any CRTC's
- */
- u8 active_pipe_changes;
-
u8 active_pipes;
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
@@ -494,10 +484,30 @@ struct intel_atomic_state {
bool rps_interactive;
/*
- * active_pipes
+ * active pipes
*/
bool global_state_changed;
+ /*
+ * Does this transaction change the pipes that are active? This mask
+ * tracks which CRTC's have changed their active state at the end of
+ * the transaction (not counting the temporary disable during modesets).
+ * This mask should only be non-zero when intel_state->modeset is true,
+ * but the converse is not necessarily true; simply changing a mode may
+ * not flip the final active status of any CRTC's
+ */
+ u8 active_pipe_changes;
+
+ /*
+ * More granular change indicator for ddb changes
+ */
+ bool ddb_state_changed;
+
+ /*
+ * More granular change indicator for bandwidth state changes
+ */
+ bool bw_state_changed;
+
/* Number of enabled DBuf slices */
u8 enabled_dbuf_slices_mask;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 409b91c17a7f..ac4b317ea1bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
* that changes the active CRTC list or do modeset would need to
* grab _all_ crtc locks, including the one we currently hold.
*/
- if (!intel_state->active_pipe_changes && !intel_state->modeset) {
+ if (!intel_state->ddb_state_changed) {
/*
* alloc may be cleared by clear_intel_crtc_state,
* copy from old state to be sure
@@ -5787,6 +5787,9 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return PTR_ERR(plane_state);
new_crtc_state->update_planes |= BIT(plane_id);
+
+ DRM_DEBUG_KMS("Marking ddb state changed for atomic state %p\n", state);
+ state->ddb_state_changed = true;
}
return 0;
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
@ 2020-02-25 14:59 ` Stanislav Lisovskiy
2020-02-27 11:46 ` Stanislav Lisovskiy
0 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-25 14:59 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
v14: - total_affected_planes is no longer needed to check for ddb changes,
just as active_pipe_changes.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 27 +-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 428 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
5 files changed, 437 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index b5f61463922f..c32b5285c12f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_mask;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 137fb645097a..6df836cbe0cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14007,7 +14007,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -14062,7 +14065,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -15540,9 +15546,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (state->bw_state_changed) {
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(dev_priv))
+ intel_disable_sagv(dev_priv);
+ }
}
intel_modeset_verify_disabled(dev_priv, state);
@@ -15643,9 +15651,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->bw_state_changed) {
- if (intel_can_enable_sagv(state)
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(dev_priv))
+ intel_enable_sagv(dev_priv);
+ }
}
drm_atomic_helper_commit_hw_done(&state->base);
@@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
-
dev_priv->active_pipes = state->active_pipes;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 12b47ba3c68d..289461571a0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -664,6 +664,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac4b317ea1bf..dbe82c268e40 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -42,6 +42,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3620,7 +3621,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3743,39 +3744,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+ enum pipe pipe)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
-
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3802,13 +3788,174 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
return false;
+ }
}
return true;
}
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ enum pipe pipe;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ if (state->active_pipes != 1) {
+ new_bw_state->pipe_sagv_mask = 0;
+ DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+ return;
+ }
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+
+ if (skl_can_enable_sagv_on_pipe(state, pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+ }
+}
+
+static void intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *new_bw_state;
+ struct intel_bw_state *old_bw_state;
+
+ /*
+ * If we are here - means either active_pipes config had changed,
+ * or watermarks/ddb has been changed, which means most likely
+ * we had crtcs added to the state(at least state is read locked)
+ * and we definitely need to recalculate SAGV state now.
+ */
+ new_bw_state = intel_bw_get_state(state);
+ old_bw_state = intel_bw_get_old_state(state);
+
+ if (IS_ERR(new_bw_state) || IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ new_bw_state->sagv_calculated = false;
+
+ /*
+ * Now once we got wm levels calculated,
+ * check if we can have SAGV.
+ */
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_compute_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_compute_sagv_mask(state);
+ else
+ skl_compute_sagv_mask(state);
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
+
+ state->bw_state_changed = true;
+ }
+}
+
+static bool intel_calculate_sagv_result(struct drm_i915_private *dev_priv,
+ struct intel_bw_state *bw_state)
+{
+ bool sagv_result = true;
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ /*
+ * TODO: We are depending on active_pipes here,
+ * probably it should be part of some other global state
+ * obj, like modeset_state or smth, which we should depend on.
+ * Don't want to clone it here, really.
+ */
+ int active_pipe_bit = dev_priv->active_pipes & BIT(pipe);
+
+ if (active_pipe_bit) {
+ if ((bw_state->pipe_sagv_mask & BIT(pipe)) == 0) {
+ sagv_result = false;
+ break;
+ }
+ }
+ }
+
+ return sagv_result;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return false;
+ }
+
+ if (!intel_has_sagv(dev_priv)) {
+ DRM_DEBUG_KMS("No SAGV support detected\n");
+ return false;
+ }
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
@@ -3842,6 +3989,35 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
return ddb_size;
}
+/*
+ * To be used after we swap state
+ */
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv)
+{
+ struct intel_global_state *global_state;
+ struct intel_bw_state *bw_state;
+
+ global_state = dev_priv->bw_obj.state;
+ if (IS_ERR(global_state)) {
+ WARN(1, "Could not get global state\n");
+ return false;
+ }
+
+ /*
+ * TODO: Should we still may be lock global state here?
+ */
+ bw_state = to_intel_bw_state(global_state);
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
u32 active_pipes);
@@ -4028,6 +4204,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
u32 latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4554,12 +4731,92 @@ skl_plane_wm_level(struct intel_plane *plane,
int level,
int color_plane)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
+ if (!level) {
+ bool can_sagv = false;
+
+ /*
+ * If we haven't yet swapped our state, we should use
+ * the state to determine SAGV, otherwise use global
+ * state as atomic state pointer might become stale
+ * and zeroed out.
+ */
+ if (state) {
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ can_sagv = intel_can_enable_sagv_for_state(intel_state);
+ } else {
+ can_sagv = intel_can_enable_sagv(dev_priv);
+ }
+
+ if (can_sagv)
+ return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+ }
+
return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return -ENOSPC;
+ }
+ }
+ DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+ blocks, alloc_size);
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5143,11 +5400,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -5158,6 +5423,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5232,7 +5518,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5254,7 +5540,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5585,9 +5871,24 @@ skl_print_wm_changes(struct intel_atomic_state *state)
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
+ const struct skl_wm_level *old_wm_level, *new_wm_level;
+ u16 old_plane_res_l, new_plane_res_l;
+ u8 old_plane_res_b, new_plane_res_b;
+ u16 old_min_ddb_alloc, new_min_ddb_alloc;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
+ old_wm_level = skl_plane_wm_level(plane, old_crtc_state, 0, false);
+ new_wm_level = skl_plane_wm_level(plane, new_crtc_state, 0, false);
+
+ old_plane_res_l = old_wm_level->plane_res_l;
+ old_plane_res_b = old_wm_level->plane_res_b;
+
+ new_plane_res_l = new_wm_level->plane_res_l;
+ new_plane_res_b = new_wm_level->plane_res_b;
+
+ old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
+ new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue;
@@ -5611,7 +5912,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+ enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5621,7 +5922,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+ enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5635,12 +5936,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+ old_plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+ new_plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5650,12 +5951,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+ old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
- new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+ new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5795,6 +6096,59 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ int ret;
+ int i;
+ struct intel_plane *plane;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ int pipe_bit = BIT(crtc->pipe);
+ bool skip = true;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+ const struct skl_plane_wm *old_wm, *new_wm;
+ bool equal_wm;
+
+ old_wm = &old_crtc_state->wm.skl.optimal.planes[plane_id];
+ new_wm = &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ equal_wm = skl_plane_wm_equals(dev_priv, old_wm, new_wm);
+
+ if (!equal_wm) {
+ skip = false;
+ break;
+ }
+ }
+
+ /*
+ * Check if wm levels are actually the same as for previous
+ * state, which means we can just skip doing this long check
+ * and just copy correspondent bit from previous state.
+ */
+ if (skip)
+ continue;
+
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state);
+ if (!ret)
+ new_bw_state->pipe_sagv_mask |= pipe_bit;
+ else
+ new_bw_state->pipe_sagv_mask &= ~pipe_bit;
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5823,6 +6177,13 @@ skl_compute_wm(struct intel_atomic_state *state)
return ret;
}
+ /*
+ * No active_pipe_changes and no wm/ddb changes means
+ * we can just skip recalculating SAGV mask.
+ */
+ if ((state->active_pipe_changes != 0) || state->ddb_state_changed)
+ intel_compute_sagv_mask(state);
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5942,6 +6303,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..561a17a5d4e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-02-25 15:00 ` Stanislav Lisovskiy
2020-02-27 16:20 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-25 15:00 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 184 +++++++++++++------
drivers/gpu/drm/i915/display/intel_bw.h | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 125 ++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 3 +
4 files changed, 255 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d5be603b8b03..4986a5464700 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
if (qgv_point >= bi->num_qgv_points)
return UINT_MAX;
- if (num_planes >= bi->num_planes)
+ if (num_planes >= bi->num_planes || !num_planes)
return bi->deratedbw[qgv_point];
}
@@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -418,11 +423,16 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/*
* For earlier Gens let's consider bandwidth changed if ddb requirements,
@@ -430,11 +440,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
*/
if (INTEL_GEN(dev_priv) < 11) {
if (state->ddb_state_changed) {
- bw_state = intel_bw_get_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- ret = intel_atomic_lock_global_state(&bw_state->base);
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
return ret;
@@ -465,45 +475,107 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_bw_get_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(&dev_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(&bw_state->base);
- if (ret)
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not lock global state\n");
return ret;
+ }
- DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
-
- state->bw_state_changed = true;
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth for display configuration.\n");
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv_for_state(state)) {
+ allowed_points = 1 << max_bw_point;
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+ state, new_bw_state->qgv_points_mask);
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ DRM_DEBUG_KMS("Could not get old bw state!\n");
+ return PTR_ERR(old_bw_state);
+ }
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+
+ DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
+ state->bw_state_changed = true;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index c32b5285c12f..b3522389a181 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -36,6 +36,13 @@ struct intel_bw_state {
*/
bool can_sagv;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
@@ -56,5 +63,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6df836cbe0cd..cb1d10af88ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15504,6 +15504,105 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ unsigned int mask = (1 << num_qgv_points) - 1;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get old bw_state!\n");
+ return;
+ }
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ WARN_ON(new_mask == mask);
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not mask required qgv points(%d)\n",
+ ret);
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get new bw_state!\n");
+ return;
+ }
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not unmask required qgv points(%d)\n",
+ ret);
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -15537,6 +15636,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+ * Now we need to check if SAGV needs to be disabled(i.e QGV points
+ * modified even, when no modeset is done(for example plane updates
+ * can now trigger that).
+ */
+ if ((INTEL_GEN(dev_priv) >= 11))
+ if (state->bw_state_changed)
+ intel_qgv_points_mask(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
@@ -15546,12 +15654,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (INTEL_GEN(dev_priv) < 11) {
- if (state->bw_state_changed) {
- if (!intel_can_enable_sagv(dev_priv))
- intel_disable_sagv(dev_priv);
- }
- }
+ if ((INTEL_GEN(dev_priv) < 11))
+ if (!intel_can_enable_sagv(dev_priv))
+ intel_disable_sagv(dev_priv);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15652,10 +15757,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_verify_planes(state);
if (INTEL_GEN(dev_priv) < 11) {
- if (state->bw_state_changed) {
- if (intel_can_enable_sagv(dev_priv))
- intel_enable_sagv(dev_priv);
- }
+ if (intel_can_enable_sagv(dev_priv))
+ intel_enable_sagv(dev_priv);
+ } else if (state->bw_state_changed) {
+ intel_qgv_points_unmask(state);
}
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4305ccc4c683..0a589700a071 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -841,6 +841,9 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_MAX,
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define INTEL_PIPE_CRC_ENTRIES_NR 128
struct intel_pipe_crc {
spinlock_t lock;
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev5)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (10 preceding siblings ...)
2020-02-24 19:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-02-26 22:00 ` Patchwork
2020-02-26 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-26 22:00 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9bdbd2c7c9d drm/i915: Start passing latency as parameter
c0db4cbaa46c drm/i915: Introduce skl_plane_wm_level accessor.
dcf925de4a6c drm/i915: Add intel_bw_get_*_state helpers
7983f49f5fc4 drm/i915: Introduce more *_state_changed indicators
3ffbee21ace8 drm/i915: Refactor intel_can_enable_sagv
-:804: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'state->active_pipe_changes != 0'
#804: FILE: drivers/gpu/drm/i915/intel_pm.c:6184:
+ if ((state->active_pipe_changes != 0) || state->ddb_state_changed)
total: 0 errors, 0 warnings, 1 checks, 680 lines checked
ca0b8463a323 drm/i915: Added required new PCode commands
e819fd5ee1d8 drm/i915: Restrict qgv points which don't have enough bandwidth.
467a14ba6c89 drm/i915: Enable SAGV support for Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev5)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (11 preceding siblings ...)
2020-02-26 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev5) Patchwork
@ 2020-02-26 22:02 ` Patchwork
2020-02-26 22:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-26 22:02 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!
Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!
Commit: drm/i915: Add intel_bw_get_*_state helpers
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev5)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (12 preceding siblings ...)
2020-02-26 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-02-26 22:26 ` Patchwork
2020-02-27 15:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev6) Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-26 22:26 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev5)
URL : https://patchwork.freedesktop.org/series/73856/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008 -> Patchwork_16717
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16717 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16717, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16717:
### IGT changes ###
#### Possible regressions ####
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_busy@basic@flip}:
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-skl-guc/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-skl-guc/igt@kms_busy@basic@flip.html
- fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-skl-6700k2/igt@kms_busy@basic@flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-skl-6700k2/igt@kms_busy@basic@flip.html
Known issues
------------
Here are the changes found in Patchwork_16717 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@basic:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-tgl-y/igt@gem_flink_basic@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-tgl-y/igt@gem_flink_basic@basic.html
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-icl-y: [DMESG-FAIL][9] ([fdo#108569]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-icl-y/igt@i915_selftest@live_execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@prime_self_import@basic-llseek-bad:
- fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (52 -> 29)
------------------------------
Additional (1): fi-byt-n2820
Missing (24): fi-kbl-soraka fi-skl-6770hq fi-apl-guc fi-skl-lmem fi-skl-6600u fi-bxt-dsi fi-bsw-n3050 fi-glk-dsi fi-bwr-2160 fi-kbl-7500u fi-ctg-p8600 fi-ivb-3770 fi-bsw-nick fi-kbl-r fi-ilk-m540 fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8008 -> Patchwork_16717
CI-20190529: 20190529
CI_DRM_8008: 13b6e2575f2c05722679bc1c9d0b97c13bde49a1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5469: 4f875016eb1ebc211b8aadb280ae16c7e6cdc8ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16717: 467a14ba6c894306981af6d47fceac533e873f30 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
467a14ba6c89 drm/i915: Enable SAGV support for Gen12
e819fd5ee1d8 drm/i915: Restrict qgv points which don't have enough bandwidth.
ca0b8463a323 drm/i915: Added required new PCode commands
3ffbee21ace8 drm/i915: Refactor intel_can_enable_sagv
7983f49f5fc4 drm/i915: Introduce more *_state_changed indicators
dcf925de4a6c drm/i915: Add intel_bw_get_*_state helpers
c0db4cbaa46c drm/i915: Introduce skl_plane_wm_level accessor.
a9bdbd2c7c9d drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16717/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv
2020-02-25 14:59 ` Stanislav Lisovskiy
@ 2020-02-27 11:46 ` Stanislav Lisovskiy
0 siblings, 0 replies; 33+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-27 11:46 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
v14: - total_affected_planes is no longer needed to check for ddb changes,
just as active_pipe_changes.
v15: - Fixed stupid mistake with uninitialized crtc in
skl_compute_sagv_mask.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 27 +-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 427 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
5 files changed, 436 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index b5f61463922f..c32b5285c12f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_mask;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5fca80b23a0e..2491f464beb9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14016,7 +14016,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -14071,7 +14074,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -15548,9 +15554,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (state->bw_state_changed) {
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(dev_priv))
+ intel_disable_sagv(dev_priv);
+ }
}
intel_modeset_verify_disabled(dev_priv, state);
@@ -15651,9 +15659,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->bw_state_changed) {
- if (intel_can_enable_sagv(state)
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(dev_priv))
+ intel_enable_sagv(dev_priv);
+ }
}
drm_atomic_helper_commit_hw_done(&state->base);
@@ -15806,7 +15816,6 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
-
dev_priv->active_pipes = state->active_pipes;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c57de98553a8..89a73e735b22 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -663,6 +663,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac4b317ea1bf..011c9d4ba015 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -42,6 +42,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3620,7 +3621,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3743,39 +3744,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+ enum pipe pipe)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
-
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3802,13 +3788,173 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
return false;
+ }
}
return true;
}
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ enum pipe pipe;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ if (state->active_pipes != 1) {
+ new_bw_state->pipe_sagv_mask = 0;
+ DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+ return;
+ }
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+
+ if (skl_can_enable_sagv_on_pipe(state, pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+ }
+}
+
+static void intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *new_bw_state;
+ struct intel_bw_state *old_bw_state;
+
+ /*
+ * If we are here - means either active_pipes config had changed,
+ * or watermarks/ddb has been changed, which means most likely
+ * we had crtcs added to the state(at least state is read locked)
+ * and we definitely need to recalculate SAGV state now.
+ */
+ new_bw_state = intel_bw_get_state(state);
+ old_bw_state = intel_bw_get_old_state(state);
+
+ if (IS_ERR(new_bw_state) || IS_ERR(old_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ new_bw_state->sagv_calculated = false;
+
+ /*
+ * Now once we got wm levels calculated,
+ * check if we can have SAGV.
+ */
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_compute_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_compute_sagv_mask(state);
+ else
+ skl_compute_sagv_mask(state);
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
+
+ state->bw_state_changed = true;
+ }
+}
+
+static bool intel_calculate_sagv_result(struct drm_i915_private *dev_priv,
+ struct intel_bw_state *bw_state)
+{
+ bool sagv_result = true;
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ /*
+ * TODO: We are depending on active_pipes here,
+ * probably it should be part of some other global state
+ * obj, like modeset_state or smth, which we should depend on.
+ * Don't want to clone it here, really.
+ */
+ int active_pipe_bit = dev_priv->active_pipes & BIT(pipe);
+
+ if (active_pipe_bit) {
+ if ((bw_state->pipe_sagv_mask & BIT(pipe)) == 0) {
+ sagv_result = false;
+ break;
+ }
+ }
+ }
+
+ return sagv_result;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return false;
+ }
+
+ if (!intel_has_sagv(dev_priv)) {
+ DRM_DEBUG_KMS("No SAGV support detected\n");
+ return false;
+ }
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
@@ -3842,6 +3988,35 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
return ddb_size;
}
+/*
+ * To be used after we swap state
+ */
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv)
+{
+ struct intel_global_state *global_state;
+ struct intel_bw_state *bw_state;
+
+ global_state = dev_priv->bw_obj.state;
+ if (IS_ERR(global_state)) {
+ WARN(1, "Could not get global state\n");
+ return false;
+ }
+
+ /*
+ * TODO: Should we still may be lock global state here?
+ */
+ bw_state = to_intel_bw_state(global_state);
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
u32 active_pipes);
@@ -4028,6 +4203,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
u32 latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4554,12 +4730,92 @@ skl_plane_wm_level(struct intel_plane *plane,
int level,
int color_plane)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
+ if (!level) {
+ bool can_sagv = false;
+
+ /*
+ * If we haven't yet swapped our state, we should use
+ * the state to determine SAGV, otherwise use global
+ * state as atomic state pointer might become stale
+ * and zeroed out.
+ */
+ if (state) {
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ can_sagv = intel_can_enable_sagv_for_state(intel_state);
+ } else {
+ can_sagv = intel_can_enable_sagv(dev_priv);
+ }
+
+ if (can_sagv)
+ return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+ }
+
return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return -ENOSPC;
+ }
+ }
+ DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+ blocks, alloc_size);
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5143,11 +5399,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -5158,6 +5422,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5232,7 +5517,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5254,7 +5539,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5585,9 +5870,24 @@ skl_print_wm_changes(struct intel_atomic_state *state)
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
+ const struct skl_wm_level *old_wm_level, *new_wm_level;
+ u16 old_plane_res_l, new_plane_res_l;
+ u8 old_plane_res_b, new_plane_res_b;
+ u16 old_min_ddb_alloc, new_min_ddb_alloc;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
+ old_wm_level = skl_plane_wm_level(plane, old_crtc_state, 0, false);
+ new_wm_level = skl_plane_wm_level(plane, new_crtc_state, 0, false);
+
+ old_plane_res_l = old_wm_level->plane_res_l;
+ old_plane_res_b = old_wm_level->plane_res_b;
+
+ new_plane_res_l = new_wm_level->plane_res_l;
+ new_plane_res_b = new_wm_level->plane_res_b;
+
+ old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
+ new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue;
@@ -5611,7 +5911,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+ enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5621,7 +5921,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+ enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5635,12 +5935,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+ old_plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+ new_plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5650,12 +5950,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+ old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
- new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+ new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5795,6 +6095,59 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ int ret;
+ int i;
+ struct intel_plane *plane;
+ struct intel_bw_state *new_bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ int pipe_bit = BIT(crtc->pipe);
+ bool skip = true;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+ const struct skl_plane_wm *old_wm, *new_wm;
+ bool equal_wm;
+
+ old_wm = &old_crtc_state->wm.skl.optimal.planes[plane_id];
+ new_wm = &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ equal_wm = skl_plane_wm_equals(dev_priv, old_wm, new_wm);
+
+ if (!equal_wm) {
+ skip = false;
+ break;
+ }
+ }
+
+ /*
+ * Check if wm levels are actually the same as for previous
+ * state, which means we can just skip doing this long check
+ * and just copy correspondent bit from previous state.
+ */
+ if (skip)
+ continue;
+
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state);
+ if (!ret)
+ new_bw_state->pipe_sagv_mask |= pipe_bit;
+ else
+ new_bw_state->pipe_sagv_mask &= ~pipe_bit;
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5823,6 +6176,13 @@ skl_compute_wm(struct intel_atomic_state *state)
return ret;
}
+ /*
+ * No active_pipe_changes and no wm/ddb changes means
+ * we can just skip recalculating SAGV mask.
+ */
+ if ((state->active_pipe_changes != 0) || state->ddb_state_changed)
+ intel_compute_sagv_mask(state);
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5942,6 +6302,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..561a17a5d4e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev6)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (13 preceding siblings ...)
2020-02-26 22:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-02-27 15:33 ` Patchwork
2020-02-27 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 15:33 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev6)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a72659eb4666 drm/i915: Start passing latency as parameter
81ddfe1ca471 drm/i915: Introduce skl_plane_wm_level accessor.
bb8fb326c38f drm/i915: Add intel_bw_get_*_state helpers
1f6cb30bce42 drm/i915: Introduce more *_state_changed indicators
0aad2ca03244 drm/i915: Refactor intel_can_enable_sagv
-:806: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'state->active_pipe_changes != 0'
#806: FILE: drivers/gpu/drm/i915/intel_pm.c:6183:
+ if ((state->active_pipe_changes != 0) || state->ddb_state_changed)
total: 0 errors, 0 warnings, 1 checks, 679 lines checked
8b626dac4931 drm/i915: Added required new PCode commands
227852eaaaf7 drm/i915: Restrict qgv points which don't have enough bandwidth.
92ef8dc6a4f2 drm/i915: Enable SAGV support for Gen12
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev6)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (14 preceding siblings ...)
2020-02-27 15:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev6) Patchwork
@ 2020-02-27 15:35 ` Patchwork
2020-02-27 15:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28 17:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 15:35 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev6)
URL : https://patchwork.freedesktop.org/series/73856/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!
Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!
Commit: drm/i915: Add intel_bw_get_*_state helpers
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-02-27 15:51 ` Ville Syrjälä
2020-02-28 12:23 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 15:51 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Feb 24, 2020 at 05:32:34PM +0200, Stanislav Lisovskiy wrote:
> For future Gen12 SAGV implementation we need to
> seemlessly alter wm levels calculated, depending
> on whether we are allowed to enable SAGV or not.
>
> So this accessor will give additional flexibility
> to do that.
>
> Currently this accessor is still simply working
> as "pass-through" function. This will be changed
> in next coming patches from this series.
>
> v2: - plane_id -> plane->id(Ville Syrjälä)
When did I say that? Can't find a previous review of this patch.
Anywyas, that change seems to cause a lot of needless noise into the
patch, and atm I can't see why we'd require it.
> - Moved wm_level var to have more local scope
> (Ville Syrjälä)
> - Renamed yuv to color_plane(Ville Syrjälä) in
> skl_plane_wm_level
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++++-----------
> 1 file changed, 81 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d6933e382657..e1d167429489 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static const struct skl_wm_level *
> +skl_plane_wm_level(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
nit: I'd put the crtc_state as the first parameter as that's the thing
we're operating on. The other stuff just specifies which piece we want
to dig out.
> + int level,
> + int color_plane)
> +{
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane->id];
> +
> + return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> u64 total_data_rate;
> - enum plane_id plane_id;
> + struct intel_plane *plane;
> int num_active;
> u64 plane_data_rate[I915_MAX_PLANES] = {};
> u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> @@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> blocks = 0;
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR) {
> - if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> +
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
false/true aren't particularly sensible color plane indices.
> +
> + if (plane->id == PLANE_CURSOR) {
> + if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
> drm_WARN_ON(&dev_priv->drm,
> - wm->wm[level].min_ddb_alloc != U16_MAX);
> + wm_level->min_ddb_alloc != U16_MAX);
> blocks = U32_MAX;
> break;
> }
> continue;
> }
>
> - blocks += wm->wm[level].min_ddb_alloc;
> - blocks += wm->uv_wm[level].min_ddb_alloc;
> + blocks += wm_level->min_ddb_alloc;
> + blocks += wm_uv_level->min_ddb_alloc;
> }
>
> if (blocks <= alloc_size) {
> @@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * watermark level, plus an extra share of the leftover blocks
> * proportional to its relative data rate.
> */
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> u64 rate;
> u16 extra;
>
> - if (plane_id == PLANE_CURSOR)
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
> +
> + if (plane->id == PLANE_CURSOR)
> continue;
>
> /*
> @@ -4665,22 +4688,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> if (total_data_rate == 0)
> break;
>
> - rate = plane_data_rate[plane_id];
> + rate = plane_data_rate[plane->id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> + total[plane->id] = wm_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
>
> if (total_data_rate == 0)
> break;
>
> - rate = uv_plane_data_rate[plane_id];
> + rate = uv_plane_data_rate[plane->id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> + uv_total[plane->id] = wm_uv_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> @@ -4688,29 +4711,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>
> /* Set the actual DDB start/end points for each plane */
> start = alloc->start;
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> struct skl_ddb_entry *plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + &crtc_state->wm.skl.plane_ddb_y[plane->id];
> struct skl_ddb_entry *uv_plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> + &crtc_state->wm.skl.plane_ddb_uv[plane->id];
>
> - if (plane_id == PLANE_CURSOR)
> + if (plane->id == PLANE_CURSOR)
> continue;
>
> /* Gen11+ uses a separate plane for UV watermarks */
> drm_WARN_ON(&dev_priv->drm,
> - INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> + INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
>
> /* Leave disabled planes at (0,0) */
> - if (total[plane_id]) {
> + if (total[plane->id]) {
> plane_alloc->start = start;
> - start += total[plane_id];
> + start += total[plane->id];
> plane_alloc->end = start;
> }
>
> - if (uv_total[plane_id]) {
> + if (uv_total[plane->id]) {
> uv_plane_alloc->start = start;
> - start += uv_total[plane_id];
> + start += uv_total[plane->id];
> uv_plane_alloc->end = start;
> }
> }
> @@ -4722,9 +4745,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * that aren't actually possible.
> */
> for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane->id];
> +
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
>
> /*
> * We only disable the watermarks for each plane if
> @@ -4738,9 +4768,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * planes must be enabled before the level will be used."
> * So this is actually safe to do.
> */
> - if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> - memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> + if (wm_level->min_ddb_alloc > total[plane->id] ||
> + wm_uv_level->min_ddb_alloc > uv_total[plane->id])
> + memset(&wm->wm[level], 0,
> + sizeof(struct skl_wm_level));
>
> /*
> * Wa_1408961008:icl, ehl
> @@ -4748,9 +4779,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> - wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + 0, false);
> + wm->wm[level].plane_res_b =
> + wm_level->plane_res_b;
> + wm->wm[level].plane_res_l =
> + wm_level->plane_res_l;
> + wm->wm[level].ignore_lines =
> + wm_level->ignore_lines;
> }
> }
> }
> @@ -4759,11 +4795,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * Go back and disable the transition watermark if it turns out we
> * don't have enough DDB blocks for it.
> */
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane->id];
>
> - if (wm->trans_wm.plane_res_b >= total[plane_id])
> + if (wm->trans_wm.plane_res_b >= total[plane->id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> }
>
> @@ -5354,10 +5390,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> const struct skl_ddb_entry *ddb_uv =
> &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> + const struct skl_wm_level *wm_level;
These can be in tighter scope.
>
> for (level = 0; level <= max_level; level++) {
> + wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
> skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> &wm->trans_wm);
> @@ -5388,10 +5427,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.optimal.planes[plane_id];
> const struct skl_ddb_entry *ddb =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + const struct skl_wm_level *wm_level;
>
> for (level = 0; level <= max_level; level++) {
> + wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
> skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
@ 2020-02-27 15:53 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 15:53 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Feb 24, 2020 at 05:32:35PM +0200, Stanislav Lisovskiy wrote:
> Add correspondent helpers to be able to get old/new bandwidth
> global state object.
>
> v2: - Fixed typo in function call
> v3: - Changed new functions naming to use convention proposed
> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
And now they no longer match the naming pattern used by all the
other simialr functions.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
> 2 files changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..bdad7476dc7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> return data_rate;
> }
>
> -static struct intel_bw_state *
> -intel_atomic_get_bw_state(struct intel_atomic_state *state)
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
> +
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_global_state *bw_state;
> @@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_atomic_get_bw_state(state);
> + bw_state = intel_bw_get_state(state);
> if (IS_ERR(bw_state))
> return PTR_ERR(bw_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index a8aa7624c5aa..b5f61463922f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -24,6 +24,15 @@ struct intel_bw_state {
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
>
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state);
> +
> void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev6)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (15 preceding siblings ...)
2020-02-27 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-02-27 15:56 ` Patchwork
2020-02-28 17:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 15:56 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev6)
URL : https://patchwork.freedesktop.org/series/73856/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8018 -> Patchwork_16732
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/index.html
Known issues
------------
Here are the changes found in Patchwork_16732 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-skl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#88]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-skl-guc/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-skl-guc/igt@kms_busy@basic@flip.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-s: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cml-s/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cml-s/igt@kms_frontbuffer_tracking@basic.html
- fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-kbl-7500u/igt@kms_frontbuffer_tracking@basic.html
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#95]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#88]: https://gitlab.freedesktop.org/drm/intel/issues/88
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 41)
------------------------------
Additional (1): fi-byt-n2820
Missing (9): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-tgl-y fi-bdw-samus fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8018 -> Patchwork_16732
CI-20190529: 20190529
CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16732: 92ef8dc6a4f25ddc463b7cc74d4dfafe8913e708 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
92ef8dc6a4f2 drm/i915: Enable SAGV support for Gen12
227852eaaaf7 drm/i915: Restrict qgv points which don't have enough bandwidth.
8b626dac4931 drm/i915: Added required new PCode commands
0aad2ca03244 drm/i915: Refactor intel_can_enable_sagv
1f6cb30bce42 drm/i915: Introduce more *_state_changed indicators
bb8fb326c38f drm/i915: Add intel_bw_get_*_state helpers
81ddfe1ca471 drm/i915: Introduce skl_plane_wm_level accessor.
a72659eb4666 drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-25 14:57 ` Stanislav Lisovskiy
@ 2020-02-27 16:12 ` Ville Syrjälä
2020-02-28 8:56 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 16:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Feb 25, 2020 at 04:57:33PM +0200, Stanislav Lisovskiy wrote:
> The reasoning behind this is such that current dependencies
> in the code are rather implicit in a sense, we have to constantly
> check a bunch of different bits like state->modeset,
> state->active_pipe_changes, which sometimes can indicate counter
> intuitive changes.
>
> By introducing more fine grained state change tracking we achieve
> better readability and dependency maintenance for the code.
>
> For example it is no longer needed to evaluate active_pipe_changes
> to understand if there were changes for wm/ddb - lets just have
> a correspondent bit in a state, called ddb_state_changed.
>
> active_pipe_changes just indicate whether there was some pipe added
> or removed. Then we evaluate if wm/ddb had been changed.
> Same for sagv/bw state. ddb changes may or may not affect if out
> bandwidth constraints have been changed.
>
> v2: Add support for older Gens in order not to introduce regressions
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
> drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
> .../drm/i915/display/intel_display_types.h | 32 ++++++++++++-------
> drivers/gpu/drm/i915/intel_pm.c | 5 ++-
> 5 files changed, 62 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index d043057d2fa0..0db9c66d3c0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> state->active_pipes = 0;
> + state->ddb_state_changed = false;
> + state->bw_state_changed = false;
Not really liking these.
After some pondering I was thinking along the lines of something simple
like this:
struct bw_state {
u8 sagv_reject;
};
bw_check()
{
for_each_crtc_in_state() {
if (sagv_possible(crtc_state))
new->sagv_reject &= ~BIT(pipe);
else
new->sagv_reject |= BIT(pipe);
}
calculate new->qgv_mask
}
> }
>
> struct intel_crtc_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index bdad7476dc7b..d5be603b8b03 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int i, ret;
>
> - /* FIXME earlier gens need some checks too */
> - if (INTEL_GEN(dev_priv) < 11)
> + /*
> + * For earlier Gens let's consider bandwidth changed if ddb requirements,
> + * has been changed.
> + */
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (state->ddb_state_changed) {
> + bw_state = intel_bw_get_state(state);
> + if (IS_ERR(bw_state))
> + return PTR_ERR(bw_state);
> +
> + ret = intel_atomic_lock_global_state(&bw_state->base);
> + if (ret)
> + return ret;
> +
> + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
> + state);
> +
> + state->bw_state_changed = true;
> + }
> return 0;
> + }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> @@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_bw_get_state(state);
> + bw_state = intel_bw_get_state(state);
> if (IS_ERR(bw_state))
> return PTR_ERR(bw_state);
>
> @@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
> +
> + state->bw_state_changed = true;
> +
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3031e64ee518..137fb645097a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15540,8 +15540,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * SKL workaround: bspec recommends we disable the SAGV when we
> * have more then one pipe enabled
> */
> - if (!intel_can_enable_sagv(state))
> - intel_disable_sagv(dev_priv);
> + if (state->bw_state_changed) {
> + if (!intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
> + }
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -15565,7 +15567,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> intel_encoders_update_prepare(state);
>
> /* Enable all new slices, we might need */
> - if (state->modeset)
> + if (state->ddb_state_changed)
> icl_dbuf_slice_pre_update(state);
>
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> @@ -15622,7 +15624,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
>
> /* Disable all slices, we don't need */
> - if (state->modeset)
> + if (state->ddb_state_changed)
> icl_dbuf_slice_post_update(state);
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> @@ -15641,8 +15643,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset)
> intel_verify_planes(state);
>
> - if (state->modeset && intel_can_enable_sagv(state))
> - intel_enable_sagv(dev_priv);
> + if (state->bw_state_changed) {
> + if (intel_can_enable_sagv(state)
> + intel_enable_sagv(dev_priv);
> + }
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0d8a64305464..12b47ba3c68d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -471,16 +471,6 @@ struct intel_atomic_state {
>
> bool dpll_set, modeset;
>
> - /*
> - * Does this transaction change the pipes that are active? This mask
> - * tracks which CRTC's have changed their active state at the end of
> - * the transaction (not counting the temporary disable during modesets).
> - * This mask should only be non-zero when intel_state->modeset is true,
> - * but the converse is not necessarily true; simply changing a mode may
> - * not flip the final active status of any CRTC's
> - */
> - u8 active_pipe_changes;
> -
> u8 active_pipes;
>
> struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
> @@ -494,10 +484,30 @@ struct intel_atomic_state {
> bool rps_interactive;
>
> /*
> - * active_pipes
> + * active pipes
> */
> bool global_state_changed;
>
> + /*
> + * Does this transaction change the pipes that are active? This mask
> + * tracks which CRTC's have changed their active state at the end of
> + * the transaction (not counting the temporary disable during modesets).
> + * This mask should only be non-zero when intel_state->modeset is true,
> + * but the converse is not necessarily true; simply changing a mode may
> + * not flip the final active status of any CRTC's
> + */
> + u8 active_pipe_changes;
> +
> + /*
> + * More granular change indicator for ddb changes
> + */
> + bool ddb_state_changed;
> +
> + /*
> + * More granular change indicator for bandwidth state changes
> + */
> + bool bw_state_changed;
> +
> /* Number of enabled DBuf slices */
> u8 enabled_dbuf_slices_mask;
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 409b91c17a7f..ac4b317ea1bf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> * that changes the active CRTC list or do modeset would need to
> * grab _all_ crtc locks, including the one we currently hold.
> */
> - if (!intel_state->active_pipe_changes && !intel_state->modeset) {
> + if (!intel_state->ddb_state_changed) {
> /*
> * alloc may be cleared by clear_intel_crtc_state,
> * copy from old state to be sure
> @@ -5787,6 +5787,9 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> return PTR_ERR(plane_state);
>
> new_crtc_state->update_planes |= BIT(plane_id);
> +
> + DRM_DEBUG_KMS("Marking ddb state changed for atomic state %p\n", state);
> + state->ddb_state_changed = true;
> }
>
> return 0;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-02-25 15:00 ` Stanislav Lisovskiy
@ 2020-02-27 16:20 ` Ville Syrjälä
2020-03-02 13:15 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 16:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Feb 25, 2020 at 05:00:43PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
>
> v4:
> - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
> masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
> as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
> can't be enabled(BSpec)
>
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
> time for TGL and indicate that QGV setting is not yet available.
>
> v6:
> - Increase number of supported QGV points to be in sync with BSpec.
>
> v7: - Rebased and resolved conflict to fix build failure.
> - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
>
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
> can be disabled by BIOS, which is completely legal. So don't
> make CI panic. Instead if we detect that there is only 1 QGV
> point accessible just analyze if we can fit the required bandwidth
> requirements, but no need in restricting.
>
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> simultaneously.
>
> v10: - Fix CDCLK corruption, because of global state getting serialized
> without modeset, which caused copying of non-calculated cdclk
> to be copied to dev_priv(thanks to Ville for the hint).
>
> v11: - Remove unneeded headers and spaces(Matthew Roper)
> - Remove unneeded intel_qgv_info qi struct from bw check and zero
> out the needed one(Matthew Roper)
> - Changed QGV error message to have more clear meaning(Matthew Roper)
> - Use state->modeset_set instead of any_ms(Matthew Roper)
> - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
> - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
> - Moved unrelated changes to other patch(using latency as parameter
> for plane wm calculation, moved to SAGV refactoring patch)
>
> v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
> - Remove unnecessary mask being zero check when unmasking
> qgv points as this is completely legal(Matt Roper)
> - Check if we are setting the same mask as already being set
> in hardware to prevent error from PCode.
> - Fix error message when restricting/unrestricting qgv points
> to "mask/unmask" which sounds more accurate(Matt Roper)
> - Move sagv status setting to icl_get_bw_info from atomic check
> as this should be calculated only once.(Matt Roper)
> - Edited comments for the case when we can't enable SAGV and
> use only 1 QGV point with highest bandwidth to be more
> understandable.(Matt Roper)
>
> v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
> - Changed comment for zero new_mask in qgv points masking function
> to better reflect reality(Ville Syrjälä)
> - Simplified bit mask operation in qgv points masking function
> (Ville Syrjälä)
> - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
> however this still can't be under modeset condition(Ville Syrjälä)
> - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
> (Ville Syrjälä)
> - Extracted PCode changes to separate patch.(Ville Syrjälä)
> - Now treat num_planes 0 same as 1 to avoid confusion and
> returning max_bw as 0, which would prevent choosing QGV
> point having max bandwidth in case if SAGV is not allowed,
> as per BSpec(Ville Syrjälä)
> - Do the actual qgv_points_mask swap in the same place as
> all other global state parts like cdclk are swapped.
> In the next patch, this all will be moved to bw state as
> global state, once new global state patch series from Ville
> lands
>
> v14: - Now using global state to serialize access to qgv points
> - Added global state locking back, otherwise we seem to read
> bw state in a wrong way.
>
> v15: - Added TODO comment for near atomic global state locking in
> bw code.
>
> v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
> with Jani Nikula.
> - Take bw_state_changed flag into use.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 184 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_bw.h | 9 +
> drivers/gpu/drm/i915/display/intel_display.c | 125 ++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 4 files changed, 255 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index d5be603b8b03..4986a5464700 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
> #include "intel_bw.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi)
> {
> @@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
> break;
> }
>
> + /*
> + * In case if SAGV is disabled in BIOS, we always get 1
> + * SAGV point, but we can't send PCode commands to restrict it
> + * as it will fail and pointless anyway.
> + */
> + if (qi.num_points == 1)
> + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> + else
> + dev_priv->sagv_status = I915_SAGV_ENABLED;
> +
> return 0;
> }
>
> @@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
> if (qgv_point >= bi->num_qgv_points)
> return UINT_MAX;
>
> - if (num_planes >= bi->num_planes)
> + if (num_planes >= bi->num_planes || !num_planes)
> return bi->deratedbw[qgv_point];
> }
>
> @@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> icl_get_bw_info(dev_priv, &icl_sa_info);
> }
>
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> - int num_planes)
> -{
> - if (INTEL_GEN(dev_priv) >= 11) {
> - /*
> - * Any bw group has same amount of QGV points
> - */
> - const struct intel_bw_info *bi =
> - &dev_priv->max_bw[0];
> - unsigned int min_bw = UINT_MAX;
> - int i;
> -
> - /*
> - * FIXME with SAGV disabled maybe we can assume
> - * point 1 will always be used? Seems to match
> - * the behaviour observed in the wild.
> - */
> - for (i = 0; i < bi->num_qgv_points; i++) {
> - unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
> -
> - min_bw = min(bw, min_bw);
> - }
> - return min_bw;
> - } else {
> - return UINT_MAX;
> - }
> -}
> -
> static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
> {
> /*
> @@ -418,11 +423,16 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> - struct intel_bw_state *bw_state = NULL;
> - unsigned int data_rate, max_data_rate;
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> + unsigned int data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> int i, ret;
> + u32 allowed_points = 0;
> + unsigned int max_bw_point = 0, max_bw = 0;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + u32 mask = (1 << num_qgv_points) - 1;
>
> /*
> * For earlier Gens let's consider bandwidth changed if ddb requirements,
> @@ -430,11 +440,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> */
> if (INTEL_GEN(dev_priv) < 11) {
> if (state->ddb_state_changed) {
> - bw_state = intel_bw_get_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + new_bw_state = intel_bw_get_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
Lot's of rename noise in the patch. Can't really see what's going on
unless those are split out.
>
> - ret = intel_atomic_lock_global_state(&bw_state->base);
> + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> if (ret)
> return ret;
>
> @@ -465,45 +475,107 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_bw_get_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + new_bw_state = intel_bw_get_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
>
> - bw_state->data_rate[crtc->pipe] = new_data_rate;
> - bw_state->num_active_planes[crtc->pipe] = new_active_planes;
> + new_bw_state->data_rate[crtc->pipe] = new_data_rate;
> + new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
>
> drm_dbg_kms(&dev_priv->drm,
> "pipe %c data rate %u num active planes %u\n",
> pipe_name(crtc->pipe),
> - bw_state->data_rate[crtc->pipe],
> - bw_state->num_active_planes[crtc->pipe]);
> + new_bw_state->data_rate[crtc->pipe],
> + new_bw_state->num_active_planes[crtc->pipe]);
> }
>
> - if (!bw_state)
> + if (!new_bw_state)
> return 0;
>
> - ret = intel_atomic_lock_global_state(&bw_state->base);
> - if (ret)
> + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> + if (ret) {
> + DRM_DEBUG_KMS("Could not lock global state\n");
> return ret;
> + }
>
> - DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
> -
> - state->bw_state_changed = true;
> + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> + data_rate = DIV_ROUND_UP(data_rate, 1000);
>
> - data_rate = intel_bw_data_rate(dev_priv, bw_state);
> - num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
> + num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
>
> - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> + for (i = 0; i < num_qgv_points; i++) {
> + unsigned int max_data_rate;
>
> - data_rate = DIV_ROUND_UP(data_rate, 1000);
> + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> + /*
> + * We need to know which qgv point gives us
> + * maximum bandwidth in order to disable SAGV
> + * if we find that we exceed SAGV block time
> + * with watermarks. By that moment we already
> + * have those, as it is calculated earlier in
> + * intel_atomic_check,
> + */
> + if (max_data_rate > max_bw) {
> + max_bw_point = i;
> + max_bw = max_data_rate;
> + }
> + if (max_data_rate >= data_rate)
> + allowed_points |= BIT(i);
> + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> + i, max_data_rate, data_rate);
> + }
>
> - if (data_rate > max_data_rate) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> - data_rate, max_data_rate, num_active_planes);
> + /*
> + * BSpec states that we always should have at least one allowed point
> + * left, so if we couldn't - simply reject the configuration for obvious
> + * reasons.
> + */
> + if (allowed_points == 0) {
> + DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> + " bandwidth for display configuration.\n");
> return -EINVAL;
> }
>
> + /*
> + * Leave only single point with highest bandwidth, if
> + * we can't enable SAGV due to the increased memory latency it may
> + * cause.
> + */
> + if (!intel_can_enable_sagv_for_state(state)) {
> + allowed_points = 1 << max_bw_point;
> + DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> + max_bw_point);
> + }
> + /*
> + * We store the ones which need to be masked as that is what PCode
> + * actually accepts as a parameter.
> + */
> + new_bw_state->qgv_points_mask = (~allowed_points) & mask;
> +
> + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> + state, new_bw_state->qgv_points_mask);
> +
> + old_bw_state = intel_bw_get_old_state(state);
> + if (IS_ERR(old_bw_state)) {
> + DRM_DEBUG_KMS("Could not get old bw state!\n");
> + return PTR_ERR(old_bw_state);
> + }
> +
> + /*
> + * If the actual mask had changed we need to make sure that
> + * the commits are serialized(in case this is a nomodeset, nonblocking)
> + */
> + if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
> + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> + if (ret) {
> + DRM_DEBUG_KMS("Could not serialize global state\n");
> + return ret;
> + }
> +
> + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
> + state->bw_state_changed = true;
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index c32b5285c12f..b3522389a181 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -36,6 +36,13 @@ struct intel_bw_state {
> */
> bool can_sagv;
>
> + /*
> + * Current QGV points mask, which restricts
> + * some particular SAGV states, not to confuse
> + * with pipe_sagv_mask.
> + */
> + u8 qgv_points_mask;
> +
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> };
> @@ -56,5 +63,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask);
>
> #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6df836cbe0cd..cb1d10af88ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15504,6 +15504,105 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
> intel_atomic_helper_free_state(i915);
> }
>
> +static void intel_qgv_points_mask(struct intel_atomic_state *state)
I think we should move these next to the other sagv code and just
call them somehting like intel_sagv_{pre,post}_plane_update() to
a) avoid the caller having to know anything about them, b) match
the pattern used for other similar things.
And I think the internals should just be something like:
intel_sagv_pre/post_plane_update()
{
new_bw_state = get_new_bw_state();
old_bw_state = get_old_bw_state();
if (!new_bw_state ||
new_bw_state->sagv_mask == old_bw_state->sagv_mask)
return;
do the pcode dance
}
I don't see a need for any more checks than than because that
would just mean that bw_check() is broken and needs to be fixed.
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> + u32 new_mask = 0;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + unsigned int mask = (1 << num_qgv_points) - 1;
> +
> + new_bw_state = intel_bw_get_state(state);
> + if (IS_ERR(new_bw_state)) {
> + WARN(1, "Could not get new bw_state!\n");
> + return;
> + }
> +
> + old_bw_state = intel_bw_get_old_state(state);
> + if (IS_ERR(old_bw_state)) {
> + WARN(1, "Could not get old bw_state!\n");
> + return;
> + }
> +
> + new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
> +
> + /*
> + * If new mask is zero - means there is nothing to mask,
> + * we can only unmask, which should be done in unmask.
> + */
> + if (!new_mask)
> + return;
> +
> + WARN_ON(new_mask == mask);
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Restrict required qgv points before updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not mask required qgv points(%d)\n",
> + ret);
> +}
> +
> +static void intel_qgv_points_unmask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> + u32 new_mask = 0;
> +
> + new_bw_state = intel_bw_get_state(state);
> + if (IS_ERR(new_bw_state)) {
> + WARN(1, "Could not get new bw_state!\n");
> + return;
> + }
> +
> + old_bw_state = intel_bw_get_old_state(state);
> + if (IS_ERR(old_bw_state)) {
> + WARN(1, "Could not get new bw_state!\n");
> + return;
> + }
> +
> + new_mask = new_bw_state->qgv_points_mask;
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Nothing to unmask
> + */
> + if (new_mask == old_bw_state->qgv_points_mask)
> + return;
> +
> + /*
> + * Allow required qgv points after updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not unmask required qgv points(%d)\n",
> + ret);
> +}
> +
> static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> @@ -15537,6 +15636,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
> + /*
> + * Now we need to check if SAGV needs to be disabled(i.e QGV points
> + * modified even, when no modeset is done(for example plane updates
> + * can now trigger that).
> + */
> + if ((INTEL_GEN(dev_priv) >= 11))
> + if (state->bw_state_changed)
> + intel_qgv_points_mask(state);
> +
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
>
> @@ -15546,12 +15654,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * SKL workaround: bspec recommends we disable the SAGV when we
> * have more then one pipe enabled
> */
> - if (INTEL_GEN(dev_priv) < 11) {
> - if (state->bw_state_changed) {
> - if (!intel_can_enable_sagv(dev_priv))
> - intel_disable_sagv(dev_priv);
> - }
> - }
> + if ((INTEL_GEN(dev_priv) < 11))
> + if (!intel_can_enable_sagv(dev_priv))
> + intel_disable_sagv(dev_priv);
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -15652,10 +15757,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> intel_verify_planes(state);
>
> if (INTEL_GEN(dev_priv) < 11) {
> - if (state->bw_state_changed) {
> - if (intel_can_enable_sagv(dev_priv))
> - intel_enable_sagv(dev_priv);
> - }
> + if (intel_can_enable_sagv(dev_priv))
> + intel_enable_sagv(dev_priv);
> + } else if (state->bw_state_changed) {
> + intel_qgv_points_unmask(state);
> }
>
> drm_atomic_helper_commit_hw_done(&state->base);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4305ccc4c683..0a589700a071 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -841,6 +841,9 @@ enum intel_pipe_crc_source {
> INTEL_PIPE_CRC_SOURCE_MAX,
> };
>
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
> #define INTEL_PIPE_CRC_ENTRIES_NR 128
> struct intel_pipe_crc {
> spinlock_t lock;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
@ 2020-02-27 16:28 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 16:28 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Feb 24, 2020 at 05:32:33PM +0200, Stanislav Lisovskiy wrote:
> We need to start passing memory latency as a
> parameter when calculating plane wm levels,
> as latency can get changed in different
> circumstances(for example with or without SAGV).
> So we need to be more flexible on that matter.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ffac0b862ca5..d6933e382657 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
I'd make it just unsigned int or something all over. Otherwise lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */);
> @@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> drm_WARN_ON(&dev_priv->drm, ret);
>
> for (level = 0; level <= max_level; level++) {
> - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> + u32 latency = dev_priv->wm.skl_latency[level];
> +
> + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4978,12 +4981,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -5112,9 +5115,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, wm_params,
> - result_prev, result);
> + skl_compute_plane_wm(crtc_state, level, latency,
> + wm_params, result_prev, result);
>
> result_prev = result;
> }
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-27 16:12 ` Ville Syrjälä
@ 2020-02-28 8:56 ` Lisovskiy, Stanislav
2020-02-28 16:12 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Lisovskiy, Stanislav @ 2020-02-28 8:56 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2020-02-27 at 18:12 +0200, Ville Syrjälä wrote:
> On Tue, Feb 25, 2020 at 04:57:33PM +0200, Stanislav Lisovskiy wrote:
> > The reasoning behind this is such that current dependencies
> > in the code are rather implicit in a sense, we have to constantly
> > check a bunch of different bits like state->modeset,
> > state->active_pipe_changes, which sometimes can indicate counter
> > intuitive changes.
> >
> > By introducing more fine grained state change tracking we achieve
> > better readability and dependency maintenance for the code.
> >
> > For example it is no longer needed to evaluate active_pipe_changes
> > to understand if there were changes for wm/ddb - lets just have
> > a correspondent bit in a state, called ddb_state_changed.
> >
> > active_pipe_changes just indicate whether there was some pipe added
> > or removed. Then we evaluate if wm/ddb had been changed.
> > Same for sagv/bw state. ddb changes may or may not affect if out
> > bandwidth constraints have been changed.
> >
> > v2: Add support for older Gens in order not to introduce
> > regressions
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
> > drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++-
> > -
> > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
> > .../drm/i915/display/intel_display_types.h | 32 ++++++++++++---
> > ----
> > drivers/gpu/drm/i915/intel_pm.c | 5 ++-
> > 5 files changed, 62 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index d043057d2fa0..0db9c66d3c0f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct
> > drm_atomic_state *s)
> > state->dpll_set = state->modeset = false;
> > state->global_state_changed = false;
> > state->active_pipes = 0;
> > + state->ddb_state_changed = false;
> > + state->bw_state_changed = false;
>
> Not really liking these.
>
> After some pondering I was thinking along the lines of something
> simple
> like this:
>
> struct bw_state {
> u8 sagv_reject;
> };
>
> bw_check()
> {
> for_each_crtc_in_state() {
> if (sagv_possible(crtc_state))
> new->sagv_reject &= ~BIT(pipe);
> else
> new->sagv_reject |= BIT(pipe);
> }
>
> calculate new->qgv_mask
> }
This is exactly what's done in the next patch, except
that I store pipe, which are allowed to have SAGV, i.e:
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether
correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_mask;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
Also the mask is calculated almost exactly same way:
static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+ struct intel_bw_state *new_bw_state =
intel_bw_get_state(state);
+
+ if (IS_ERR(new_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return;
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+ new_bw_state->pipe_sagv_mask |= BIT(crtc-
>pipe);
+ else
+ new_bw_state->pipe_sagv_mask &= ~BIT(crtc-
>pipe);
+ }
+}
But this patch is not about that - it is about how we signal/determine
that some change has to be written at commit stage.
As you remember when we were discussed offline, I just wanted to have
some expicit way to mark if some global state subsystem had changed,
without having to do any additional checks, because imho all the checks
we should do during atomic check, while commit simply applies what has
to be applied.
If you are really against having those boolean or any other way to be
able so simply mark some stage object "dirty" (just like mem pages
analogy) then would vote at least to have some helper functions to do
that.
i.e smth like:
bool pipe_sagv_mask_changed(..)
bool ddb_state_changed(...)
Stan
>
> > }
> >
> > struct intel_crtc_state *
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index bdad7476dc7b..d5be603b8b03 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > struct intel_crtc *crtc;
> > int i, ret;
> >
> > - /* FIXME earlier gens need some checks too */
> > - if (INTEL_GEN(dev_priv) < 11)
> > + /*
> > + * For earlier Gens let's consider bandwidth changed if ddb
> > requirements,
> > + * has been changed.
> > + */
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + if (state->ddb_state_changed) {
> > + bw_state = intel_bw_get_state(state);
> > + if (IS_ERR(bw_state))
> > + return PTR_ERR(bw_state);
> > +
> > + ret = intel_atomic_lock_global_state(&bw_state-
> > >base);
> > + if (ret)
> > + return ret;
> > +
> > + DRM_DEBUG_KMS("Marking bw state changed for
> > atomic state %p\n",
> > + state);
> > +
> > + state->bw_state_changed = true;
> > + }
> > return 0;
> > + }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > new_crtc_state, i) {
> > @@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > old_active_planes == new_active_planes)
> > continue;
> >
> > - bw_state = intel_bw_get_state(state);
> > + bw_state = intel_bw_get_state(state);
> > if (IS_ERR(bw_state))
> > return PTR_ERR(bw_state);
> >
> > @@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
> > state);
> > +
> > + state->bw_state_changed = true;
> > +
> > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 3031e64ee518..137fb645097a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15540,8 +15540,10 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > * SKL workaround: bspec recommends we disable the SAGV
> > when we
> > * have more then one pipe enabled
> > */
> > - if (!intel_can_enable_sagv(state))
> > - intel_disable_sagv(dev_priv);
> > + if (state->bw_state_changed) {
> > + if (!intel_can_enable_sagv(state))
> > + intel_disable_sagv(dev_priv);
> > + }
> >
> > intel_modeset_verify_disabled(dev_priv, state);
> > }
> > @@ -15565,7 +15567,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > intel_encoders_update_prepare(state);
> >
> > /* Enable all new slices, we might need */
> > - if (state->modeset)
> > + if (state->ddb_state_changed)
> > icl_dbuf_slice_pre_update(state);
> >
> > /* Now enable the clocks, plane, pipe, and connectors that we
> > set up. */
> > @@ -15622,7 +15624,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > }
> >
> > /* Disable all slices, we don't need */
> > - if (state->modeset)
> > + if (state->ddb_state_changed)
> > icl_dbuf_slice_post_update(state);
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> > @@ -15641,8 +15643,10 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (state->modeset)
> > intel_verify_planes(state);
> >
> > - if (state->modeset && intel_can_enable_sagv(state))
> > - intel_enable_sagv(dev_priv);
> > + if (state->bw_state_changed) {
> > + if (intel_can_enable_sagv(state)
> > + intel_enable_sagv(dev_priv);
> > + }
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 0d8a64305464..12b47ba3c68d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -471,16 +471,6 @@ struct intel_atomic_state {
> >
> > bool dpll_set, modeset;
> >
> > - /*
> > - * Does this transaction change the pipes that are
> > active? This mask
> > - * tracks which CRTC's have changed their active state at the
> > end of
> > - * the transaction (not counting the temporary disable during
> > modesets).
> > - * This mask should only be non-zero when intel_state->modeset
> > is true,
> > - * but the converse is not necessarily true; simply changing a
> > mode may
> > - * not flip the final active status of any CRTC's
> > - */
> > - u8 active_pipe_changes;
> > -
> > u8 active_pipes;
> >
> > struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
> > @@ -494,10 +484,30 @@ struct intel_atomic_state {
> > bool rps_interactive;
> >
> > /*
> > - * active_pipes
> > + * active pipes
> > */
> > bool global_state_changed;
> >
> > + /*
> > + * Does this transaction change the pipes that are
> > active? This mask
> > + * tracks which CRTC's have changed their active state at the
> > end of
> > + * the transaction (not counting the temporary disable during
> > modesets).
> > + * This mask should only be non-zero when intel_state->modeset
> > is true,
> > + * but the converse is not necessarily true; simply changing a
> > mode may
> > + * not flip the final active status of any CRTC's
> > + */
> > + u8 active_pipe_changes;
> > +
> > + /*
> > + * More granular change indicator for ddb changes
> > + */
> > + bool ddb_state_changed;
> > +
> > + /*
> > + * More granular change indicator for bandwidth state changes
> > + */
> > + bool bw_state_changed;
> > +
> > /* Number of enabled DBuf slices */
> > u8 enabled_dbuf_slices_mask;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 409b91c17a7f..ac4b317ea1bf 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> > drm_i915_private *dev_priv,
> > * that changes the active CRTC list or do modeset would need
> > to
> > * grab _all_ crtc locks, including the one we currently hold.
> > */
> > - if (!intel_state->active_pipe_changes && !intel_state->modeset)
> > {
> > + if (!intel_state->ddb_state_changed) {
> > /*
> > * alloc may be cleared by clear_intel_crtc_state,
> > * copy from old state to be sure
> > @@ -5787,6 +5787,9 @@ static int skl_wm_add_affected_planes(struct
> > intel_atomic_state *state,
> > return PTR_ERR(plane_state);
> >
> > new_crtc_state->update_planes |= BIT(plane_id);
> > +
> > + DRM_DEBUG_KMS("Marking ddb state changed for atomic
> > state %p\n", state);
> > + state->ddb_state_changed = true;
> > }
> >
> > return 0;
> > --
> > 2.24.1.485.gad05a3d8e5
>
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
2020-02-27 15:51 ` Ville Syrjälä
@ 2020-02-28 12:23 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 33+ messages in thread
From: Lisovskiy, Stanislav @ 2020-02-28 12:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15211 bytes --]
>> v2: - plane_id -> plane->id(Ville Syrjälä)
>When did I say that? Can't find a previous review of this patch.
>Anywyas, that change seems to cause a lot of needless noise into the
>patch, and atm I can't see why we'd require it.
Your comment was in https://patchwork.freedesktop.org/patch/345025/?series=68028&rev=14,
however I seem to have wrongly interpreted it. I think my motivation to switch
to plane based iteration was because its way easier to call skl_plane_wm_level
function then, because it takes plane itself as a parameter, also as it had already
an id, thought it is also better that way, rather than keeping one more variable
instead. Whatever.. I'm fine with both, that is not critical anyways.
Stan
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Thursday, February 27, 2020 5:51:52 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
Subject: Re: [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
On Mon, Feb 24, 2020 at 05:32:34PM +0200, Stanislav Lisovskiy wrote:
> For future Gen12 SAGV implementation we need to
> seemlessly alter wm levels calculated, depending
> on whether we are allowed to enable SAGV or not.
>
> So this accessor will give additional flexibility
> to do that.
>
> Currently this accessor is still simply working
> as "pass-through" function. This will be changed
> in next coming patches from this series.
>
> v2: - plane_id -> plane->id(Ville Syrjälä)
When did I say that? Can't find a previous review of this patch.
Anywyas, that change seems to cause a lot of needless noise into the
patch, and atm I can't see why we'd require it.
> - Moved wm_level var to have more local scope
> (Ville Syrjälä)
> - Renamed yuv to color_plane(Ville Syrjälä) in
> skl_plane_wm_level
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++++-----------
> 1 file changed, 81 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d6933e382657..e1d167429489 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static const struct skl_wm_level *
> +skl_plane_wm_level(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
nit: I'd put the crtc_state as the first parameter as that's the thing
we're operating on. The other stuff just specifies which piece we want
to dig out.
> + int level,
> + int color_plane)
> +{
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane->id];
> +
> + return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> u64 total_data_rate;
> - enum plane_id plane_id;
> + struct intel_plane *plane;
> int num_active;
> u64 plane_data_rate[I915_MAX_PLANES] = {};
> u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> @@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> blocks = 0;
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR) {
> - if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> +
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
false/true aren't particularly sensible color plane indices.
> +
> + if (plane->id == PLANE_CURSOR) {
> + if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
> drm_WARN_ON(&dev_priv->drm,
> - wm->wm[level].min_ddb_alloc != U16_MAX);
> + wm_level->min_ddb_alloc != U16_MAX);
> blocks = U32_MAX;
> break;
> }
> continue;
> }
>
> - blocks += wm->wm[level].min_ddb_alloc;
> - blocks += wm->uv_wm[level].min_ddb_alloc;
> + blocks += wm_level->min_ddb_alloc;
> + blocks += wm_uv_level->min_ddb_alloc;
> }
>
> if (blocks <= alloc_size) {
> @@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * watermark level, plus an extra share of the leftover blocks
> * proportional to its relative data rate.
> */
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> u64 rate;
> u16 extra;
>
> - if (plane_id == PLANE_CURSOR)
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
> +
> + if (plane->id == PLANE_CURSOR)
> continue;
>
> /*
> @@ -4665,22 +4688,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> if (total_data_rate == 0)
> break;
>
> - rate = plane_data_rate[plane_id];
> + rate = plane_data_rate[plane->id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> + total[plane->id] = wm_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
>
> if (total_data_rate == 0)
> break;
>
> - rate = uv_plane_data_rate[plane_id];
> + rate = uv_plane_data_rate[plane->id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> + uv_total[plane->id] = wm_uv_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> @@ -4688,29 +4711,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>
> /* Set the actual DDB start/end points for each plane */
> start = alloc->start;
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> struct skl_ddb_entry *plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + &crtc_state->wm.skl.plane_ddb_y[plane->id];
> struct skl_ddb_entry *uv_plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> + &crtc_state->wm.skl.plane_ddb_uv[plane->id];
>
> - if (plane_id == PLANE_CURSOR)
> + if (plane->id == PLANE_CURSOR)
> continue;
>
> /* Gen11+ uses a separate plane for UV watermarks */
> drm_WARN_ON(&dev_priv->drm,
> - INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> + INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
>
> /* Leave disabled planes at (0,0) */
> - if (total[plane_id]) {
> + if (total[plane->id]) {
> plane_alloc->start = start;
> - start += total[plane_id];
> + start += total[plane->id];
> plane_alloc->end = start;
> }
>
> - if (uv_total[plane_id]) {
> + if (uv_total[plane->id]) {
> uv_plane_alloc->start = start;
> - start += uv_total[plane_id];
> + start += uv_total[plane->id];
> uv_plane_alloc->end = start;
> }
> }
> @@ -4722,9 +4745,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * that aren't actually possible.
> */
> for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane->id];
> +
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
>
> /*
> * We only disable the watermarks for each plane if
> @@ -4738,9 +4768,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * planes must be enabled before the level will be used."
> * So this is actually safe to do.
> */
> - if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> - memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> + if (wm_level->min_ddb_alloc > total[plane->id] ||
> + wm_uv_level->min_ddb_alloc > uv_total[plane->id])
> + memset(&wm->wm[level], 0,
> + sizeof(struct skl_wm_level));
>
> /*
> * Wa_1408961008:icl, ehl
> @@ -4748,9 +4779,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> - wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + 0, false);
> + wm->wm[level].plane_res_b =
> + wm_level->plane_res_b;
> + wm->wm[level].plane_res_l =
> + wm_level->plane_res_l;
> + wm->wm[level].ignore_lines =
> + wm_level->ignore_lines;
> }
> }
> }
> @@ -4759,11 +4795,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * Go back and disable the transition watermark if it turns out we
> * don't have enough DDB blocks for it.
> */
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + &crtc_state->wm.skl.optimal.planes[plane->id];
>
> - if (wm->trans_wm.plane_res_b >= total[plane_id])
> + if (wm->trans_wm.plane_res_b >= total[plane->id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> }
>
> @@ -5354,10 +5390,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> const struct skl_ddb_entry *ddb_uv =
> &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> + const struct skl_wm_level *wm_level;
These can be in tighter scope.
>
> for (level = 0; level <= max_level; level++) {
> + wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
> skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> &wm->trans_wm);
> @@ -5388,10 +5427,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.optimal.planes[plane_id];
> const struct skl_ddb_entry *ddb =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + const struct skl_wm_level *wm_level;
>
> for (level = 0; level <= max_level; level++) {
> + wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
> skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-28 8:56 ` Lisovskiy, Stanislav
@ 2020-02-28 16:12 ` Ville Syrjälä
2020-02-29 9:34 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-28 16:12 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Fri, Feb 28, 2020 at 08:56:58AM +0000, Lisovskiy, Stanislav wrote:
> On Thu, 2020-02-27 at 18:12 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 25, 2020 at 04:57:33PM +0200, Stanislav Lisovskiy wrote:
> > > The reasoning behind this is such that current dependencies
> > > in the code are rather implicit in a sense, we have to constantly
> > > check a bunch of different bits like state->modeset,
> > > state->active_pipe_changes, which sometimes can indicate counter
> > > intuitive changes.
> > >
> > > By introducing more fine grained state change tracking we achieve
> > > better readability and dependency maintenance for the code.
> > >
> > > For example it is no longer needed to evaluate active_pipe_changes
> > > to understand if there were changes for wm/ddb - lets just have
> > > a correspondent bit in a state, called ddb_state_changed.
> > >
> > > active_pipe_changes just indicate whether there was some pipe added
> > > or removed. Then we evaluate if wm/ddb had been changed.
> > > Same for sagv/bw state. ddb changes may or may not affect if out
> > > bandwidth constraints have been changed.
> > >
> > > v2: Add support for older Gens in order not to introduce
> > > regressions
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
> > > drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++-
> > > -
> > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
> > > .../drm/i915/display/intel_display_types.h | 32 ++++++++++++---
> > > ----
> > > drivers/gpu/drm/i915/intel_pm.c | 5 ++-
> > > 5 files changed, 62 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index d043057d2fa0..0db9c66d3c0f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct
> > > drm_atomic_state *s)
> > > state->dpll_set = state->modeset = false;
> > > state->global_state_changed = false;
> > > state->active_pipes = 0;
> > > + state->ddb_state_changed = false;
> > > + state->bw_state_changed = false;
> >
> > Not really liking these.
> >
> > After some pondering I was thinking along the lines of something
> > simple
> > like this:
> >
> > struct bw_state {
> > u8 sagv_reject;
> > };
> >
> > bw_check()
> > {
> > for_each_crtc_in_state() {
> > if (sagv_possible(crtc_state))
> > new->sagv_reject &= ~BIT(pipe);
> > else
> > new->sagv_reject |= BIT(pipe);
> > }
> >
> > calculate new->qgv_mask
> > }
>
> This is exactly what's done in the next patch, except
> that I store pipe, which are allowed to have SAGV, i.e:
I think inverted mask idea leads to neater code because then we
don't have to care which pipes are actually present in the hw
and which are fused off/not present:
sagv_reject == 0 -> SAGV possible
sagv_reject != 0 -> SAGV not possible
>
> struct intel_bw_state {
> struct intel_global_state base;
>
> + /*
> + * Contains a bit mask, used to determine, whether
> correspondent
> + * pipe allows SAGV or not.
> + */
> + u8 pipe_sagv_mask;
> +
> + /*
> + * Used to determine if we already had calculated
> + * SAGV mask for this state once.
> + */
> + bool sagv_calculated;
> +
> + /*
> + * Contains final SAGV decision based on current mask,
> + * to prevent doing the same job over and over again.
> + */
> + bool can_sagv;
> +
>
> Also the mask is calculated almost exactly same way:
>
> static void icl_compute_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int i;
> + struct intel_bw_state *new_bw_state =
> intel_bw_get_state(state);
> +
> + if (IS_ERR(new_bw_state)) {
> + WARN(1, "Could not get bw_state\n");
> + return;
> + }
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
> + new_bw_state->pipe_sagv_mask |= BIT(crtc-
> >pipe);
> + else
> + new_bw_state->pipe_sagv_mask &= ~BIT(crtc-
> >pipe);
> + }
> +}
>
> But this patch is not about that - it is about how we signal/determine
> that some change has to be written at commit stage.
> As you remember when we were discussed offline, I just wanted to have
> some expicit way to mark if some global state subsystem had changed,
> without having to do any additional checks, because imho all the checks
> we should do during atomic check, while commit simply applies what has
> to be applied.
>
> If you are really against having those boolean or any other way to be
> able so simply mark some stage object "dirty" (just like mem pages
> analogy) then would vote at least to have some helper functions to do
> that.
> i.e smth like:
>
> bool pipe_sagv_mask_changed(..)
This is just a !=, no? Don't see a function really making it any more clear.
>
> bool ddb_state_changed(...)
So far I don't see any real need to check for that.
>
> Stan
>
> >
> > > }
> > >
> > > struct intel_crtc_state *
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index bdad7476dc7b..d5be603b8b03 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > struct intel_crtc *crtc;
> > > int i, ret;
> > >
> > > - /* FIXME earlier gens need some checks too */
> > > - if (INTEL_GEN(dev_priv) < 11)
> > > + /*
> > > + * For earlier Gens let's consider bandwidth changed if ddb
> > > requirements,
> > > + * has been changed.
> > > + */
> > > + if (INTEL_GEN(dev_priv) < 11) {
> > > + if (state->ddb_state_changed) {
> > > + bw_state = intel_bw_get_state(state);
> > > + if (IS_ERR(bw_state))
> > > + return PTR_ERR(bw_state);
> > > +
> > > + ret = intel_atomic_lock_global_state(&bw_state-
> > > >base);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + DRM_DEBUG_KMS("Marking bw state changed for
> > > atomic state %p\n",
> > > + state);
> > > +
> > > + state->bw_state_changed = true;
> > > + }
> > > return 0;
> > > + }
> > >
> > > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > new_crtc_state, i) {
> > > @@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > old_active_planes == new_active_planes)
> > > continue;
> > >
> > > - bw_state = intel_bw_get_state(state);
> > > + bw_state = intel_bw_get_state(state);
> > > if (IS_ERR(bw_state))
> > > return PTR_ERR(bw_state);
> > >
> > > @@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
> > > state);
> > > +
> > > + state->bw_state_changed = true;
> > > +
> > > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > > bw_state);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 3031e64ee518..137fb645097a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15540,8 +15540,10 @@ static void
> > > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > * SKL workaround: bspec recommends we disable the SAGV
> > > when we
> > > * have more then one pipe enabled
> > > */
> > > - if (!intel_can_enable_sagv(state))
> > > - intel_disable_sagv(dev_priv);
> > > + if (state->bw_state_changed) {
> > > + if (!intel_can_enable_sagv(state))
> > > + intel_disable_sagv(dev_priv);
> > > + }
> > >
> > > intel_modeset_verify_disabled(dev_priv, state);
> > > }
> > > @@ -15565,7 +15567,7 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > intel_encoders_update_prepare(state);
> > >
> > > /* Enable all new slices, we might need */
> > > - if (state->modeset)
> > > + if (state->ddb_state_changed)
> > > icl_dbuf_slice_pre_update(state);
> > >
> > > /* Now enable the clocks, plane, pipe, and connectors that we
> > > set up. */
> > > @@ -15622,7 +15624,7 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > }
> > >
> > > /* Disable all slices, we don't need */
> > > - if (state->modeset)
> > > + if (state->ddb_state_changed)
> > > icl_dbuf_slice_post_update(state);
> > >
> > > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state, new_crtc_state, i) {
> > > @@ -15641,8 +15643,10 @@ static void
> > > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > if (state->modeset)
> > > intel_verify_planes(state);
> > >
> > > - if (state->modeset && intel_can_enable_sagv(state))
> > > - intel_enable_sagv(dev_priv);
> > > + if (state->bw_state_changed) {
> > > + if (intel_can_enable_sagv(state)
> > > + intel_enable_sagv(dev_priv);
> > > + }
> > >
> > > drm_atomic_helper_commit_hw_done(&state->base);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 0d8a64305464..12b47ba3c68d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -471,16 +471,6 @@ struct intel_atomic_state {
> > >
> > > bool dpll_set, modeset;
> > >
> > > - /*
> > > - * Does this transaction change the pipes that are
> > > active? This mask
> > > - * tracks which CRTC's have changed their active state at the
> > > end of
> > > - * the transaction (not counting the temporary disable during
> > > modesets).
> > > - * This mask should only be non-zero when intel_state->modeset
> > > is true,
> > > - * but the converse is not necessarily true; simply changing a
> > > mode may
> > > - * not flip the final active status of any CRTC's
> > > - */
> > > - u8 active_pipe_changes;
> > > -
> > > u8 active_pipes;
> > >
> > > struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
> > > @@ -494,10 +484,30 @@ struct intel_atomic_state {
> > > bool rps_interactive;
> > >
> > > /*
> > > - * active_pipes
> > > + * active pipes
> > > */
> > > bool global_state_changed;
> > >
> > > + /*
> > > + * Does this transaction change the pipes that are
> > > active? This mask
> > > + * tracks which CRTC's have changed their active state at the
> > > end of
> > > + * the transaction (not counting the temporary disable during
> > > modesets).
> > > + * This mask should only be non-zero when intel_state->modeset
> > > is true,
> > > + * but the converse is not necessarily true; simply changing a
> > > mode may
> > > + * not flip the final active status of any CRTC's
> > > + */
> > > + u8 active_pipe_changes;
> > > +
> > > + /*
> > > + * More granular change indicator for ddb changes
> > > + */
> > > + bool ddb_state_changed;
> > > +
> > > + /*
> > > + * More granular change indicator for bandwidth state changes
> > > + */
> > > + bool bw_state_changed;
> > > +
> > > /* Number of enabled DBuf slices */
> > > u8 enabled_dbuf_slices_mask;
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 409b91c17a7f..ac4b317ea1bf 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> > > drm_i915_private *dev_priv,
> > > * that changes the active CRTC list or do modeset would need
> > > to
> > > * grab _all_ crtc locks, including the one we currently hold.
> > > */
> > > - if (!intel_state->active_pipe_changes && !intel_state->modeset)
> > > {
> > > + if (!intel_state->ddb_state_changed) {
> > > /*
> > > * alloc may be cleared by clear_intel_crtc_state,
> > > * copy from old state to be sure
> > > @@ -5787,6 +5787,9 @@ static int skl_wm_add_affected_planes(struct
> > > intel_atomic_state *state,
> > > return PTR_ERR(plane_state);
> > >
> > > new_crtc_state->update_planes |= BIT(plane_id);
> > > +
> > > + DRM_DEBUG_KMS("Marking ddb state changed for atomic
> > > state %p\n", state);
> > > + state->ddb_state_changed = true;
> > > }
> > >
> > > return 0;
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> >
--
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor Gen11+ SAGV support (rev6)
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (16 preceding siblings ...)
2020-02-27 15:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-28 17:22 ` Patchwork
17 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-28 17:22 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev6)
URL : https://patchwork.freedesktop.org/series/73856/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8018_full -> Patchwork_16732_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16732_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16732_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16732_full:
### IGT changes ###
#### Possible regressions ####
* igt@debugfs_test@read_all_entries_display_on:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk6/igt@debugfs_test@read_all_entries_display_on.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk1/igt@debugfs_test@read_all_entries_display_on.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_rotation_crc@sprite-rotation-180:
- shard-tglb: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb5/igt@kms_rotation_crc@sprite-rotation-180.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] +10 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb2/igt@kms_rotation_crc@sprite-rotation-270.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb5/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@runner@aborted:
- shard-tglb: NOTRUN -> ([FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb7/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb8/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb2/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb6/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb5/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb6/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb5/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb7/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb8/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb2/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb3/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb6/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb5/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- shard-kbl: [FAIL][21] ([i915#92]) -> ([FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35]) ([fdo#109383] / [fdo#111012] / [i915#92])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl6/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl7/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl6/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl7/igt@runner@aborted.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl4/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl6/igt@runner@aborted.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl1/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl7/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl4/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl6/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl4/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl3/igt@runner@aborted.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl2/igt@runner@aborted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl2/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl1/igt@runner@aborted.html
- shard-apl: [FAIL][36] ([fdo#103927]) -> ([FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44]) ([fdo#103927] / [i915#211])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl7/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl6/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl3/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl3/igt@runner@aborted.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl7/igt@runner@aborted.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl8/igt@runner@aborted.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl8/igt@runner@aborted.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl8/igt@runner@aborted.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl1/igt@runner@aborted.html
New tests
---------
New tests have been introduced between CI_DRM_8018_full and Patchwork_16732_full:
### New IGT tests (4) ###
* igt@drm_mm@all:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@mock:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@perf:
- Statuses :
- Exec time: [None] s
* igt@kms_selftest@all:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_16732_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@implicit-read-write-bsd2:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109276] / [i915#677])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd2.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb3/igt@gem_exec_schedule@implicit-read-write-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#112146]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][49] -> [FAIL][50] ([i915#413]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb3/igt@i915_pm_rps@reset.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb1/igt@i915_pm_rps@reset.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-kbl: [PASS][51] -> [INCOMPLETE][52] ([fdo#103665] / [i915#639])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl4/igt@kms_atomic_transition@plane-all-modeset-transition.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: [PASS][53] -> [INCOMPLETE][54] ([fdo#103927]) +6 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][55] -> [INCOMPLETE][56] ([i915#300])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
- shard-skl: [PASS][57] -> [FAIL][58] ([i915#54])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
* igt@kms_cursor_legacy@all-pipes-torture-move:
- shard-skl: [PASS][59] -> [INCOMPLETE][60] ([i915#69])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl8/igt@kms_cursor_legacy@all-pipes-torture-move.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl9/igt@kms_cursor_legacy@all-pipes-torture-move.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-kbl: [PASS][61] -> [INCOMPLETE][62] ([fdo#103665]) +11 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-skl: [PASS][63] -> [FAIL][64] ([IGT#5]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-glk: [PASS][65] -> [DMESG-FAIL][66] ([i915#118] / [i915#54] / [i915#95]) +16 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk6/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk2/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
* igt@kms_draw_crc@fill-fb:
- shard-glk: [PASS][67] -> [DMESG-FAIL][68] ([i915#118] / [i915#95])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk6/igt@kms_draw_crc@fill-fb.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk4/igt@kms_draw_crc@fill-fb.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
- shard-glk: [PASS][71] -> [DMESG-WARN][72] ([i915#118] / [i915#95]) +42 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk9/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: [PASS][73] -> [DMESG-FAIL][74] ([i915#118] / [i915#49] / [i915#95]) +7 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][75] -> [FAIL][76] ([i915#1188]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-skl: [PASS][77] -> [INCOMPLETE][78] ([i915#648])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl6/igt@kms_plane@pixel-format-pipe-a-planes.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl2/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][79] -> [FAIL][80] ([fdo#108145] / [i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-overlay-size-256:
- shard-glk: [PASS][81] -> [INCOMPLETE][82] ([i915#58] / [k.org#198133]) +12 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk7/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk6/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
- shard-skl: [PASS][83] -> [INCOMPLETE][84] ([i915#198])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl9/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl1/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][85] -> [SKIP][86] ([fdo#109441]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-tglb: [PASS][87] -> [INCOMPLETE][88] ([i915#750])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][89] -> [FAIL][90] ([i915#31])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl2/igt@kms_setmode@basic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl1/igt@kms_setmode@basic.html
- shard-kbl: [PASS][91] -> [FAIL][92] ([i915#31])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl2/igt@kms_setmode@basic.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl4/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-accuracy-2-vcs1:
- shard-iclb: [PASS][93] -> [SKIP][94] ([fdo#112080]) +5 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@perf_pmu@busy-accuracy-2-vcs1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@perf_pmu@busy-accuracy-2-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][95] -> [SKIP][96] ([fdo#109276]) +14 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][97] ([fdo#110841]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-independent-blt:
- shard-tglb: [FAIL][99] -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb7/igt@gem_ctx_shared@q-independent-blt.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb2/igt@gem_ctx_shared@q-independent-blt.html
* igt@gem_exec_schedule@implicit-write-read-bsd1:
- shard-iclb: [SKIP][101] ([fdo#109276] / [i915#677]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb3/igt@gem_exec_schedule@implicit-write-read-bsd1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb1/igt@gem_exec_schedule@implicit-write-read-bsd1.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [SKIP][103] ([fdo#109276]) -> [PASS][104] +13 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb3/igt@gem_exec_schedule@out-order-bsd2.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][105] ([i915#677]) -> [PASS][106] +3 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][107] ([fdo#112146]) -> [PASS][108] +5 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][109] ([i915#644]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [DMESG-WARN][111] ([i915#180]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
- shard-skl: [FAIL][113] ([i915#54]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][115] ([fdo#109441]) -> [PASS][116] +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][117] ([i915#180]) -> [PASS][118] +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@busy-vcs1:
- shard-iclb: [SKIP][119] ([fdo#112080]) -> [PASS][120] +10 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb3/igt@perf_pmu@busy-vcs1.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb1/igt@perf_pmu@busy-vcs1.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [SKIP][121] ([fdo#112080]) -> [FAIL][122] ([IGT#28])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][123] ([i915#454]) -> [SKIP][124] ([i915#468])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb7/igt@i915_pm_dc@dc6-psr.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [FAIL][125] ([i915#899]) -> [INCOMPLETE][126] ([i915#58] / [k.org#198133])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#211]: https://gitlab.freedesktop.org/drm/intel/issues/211
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#639]: https://gitlab.freedesktop.org/drm/intel/issues/639
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8018 -> Patchwork_16732
CI-20190529: 20190529
CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16732: 92ef8dc6a4f25ddc463b7cc74d4dfafe8913e708 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
2020-02-28 16:12 ` Ville Syrjälä
@ 2020-02-29 9:34 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 33+ messages in thread
From: Lisovskiy, Stanislav @ 2020-02-29 9:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15875 bytes --]
>> But this patch is not about that - it is about how we signal/determine
>> that some change has to be written at commit stage.
>>As you remember when we were discussed offline, I just wanted to have
>> some expicit way to mark if some global state subsystem had changed,
>>without having to do any additional checks, because imho all the checks
>> we should do during atomic check, while commit simply applies what has
>> to be applied.
>>
>>If you are really against having those boolean or any other way to be
>>able so simply mark some stage object "dirty" (just like mem pages
>>analogy) then would vote at least to have some helper functions to do
>>that.
>>i.e smth like:
>>
>>bool pipe_sagv_mask_changed(..)
>This is just a !=, no? Don't see a function really making it any more clear.
it is more compact at least(imho) and also it makes it more clear why
we do this "!=".
>>
>> bool ddb_state_changed(...)
>So far I don't see any real need to check for that.
The idea behind this is that we need to recompute SAGV only
when either active pipes had changed or wm/ddb allocations had changed(lets
say we now use a different mode or less planes and so on).
Currently we have _no_ flag that indicates if ddb/wm had changed and
recomputing SAGV everytime "just in case" looks redundant.
To me it looks easier rather than having comparisons with implicit
meaning.
Would be even nicer to unify that idea in a sense that any global object
like bw_state, dbuf_state can be checked if it's state had changed and to
have it as some helper functions for that in intel_global_state.c or something like that.
If you can propose a better way, please do: I think you got the idea,
what I mean.
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Friday, February 28, 2020 6:12:36 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
Subject: Re: [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
On Fri, Feb 28, 2020 at 08:56:58AM +0000, Lisovskiy, Stanislav wrote:
> On Thu, 2020-02-27 at 18:12 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 25, 2020 at 04:57:33PM +0200, Stanislav Lisovskiy wrote:
> > > The reasoning behind this is such that current dependencies
> > > in the code are rather implicit in a sense, we have to constantly
> > > check a bunch of different bits like state->modeset,
> > > state->active_pipe_changes, which sometimes can indicate counter
> > > intuitive changes.
> > >
> > > By introducing more fine grained state change tracking we achieve
> > > better readability and dependency maintenance for the code.
> > >
> > > For example it is no longer needed to evaluate active_pipe_changes
> > > to understand if there were changes for wm/ddb - lets just have
> > > a correspondent bit in a state, called ddb_state_changed.
> > >
> > > active_pipe_changes just indicate whether there was some pipe added
> > > or removed. Then we evaluate if wm/ddb had been changed.
> > > Same for sagv/bw state. ddb changes may or may not affect if out
> > > bandwidth constraints have been changed.
> > >
> > > v2: Add support for older Gens in order not to introduce
> > > regressions
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
> > > drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++-
> > > -
> > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++----
> > > .../drm/i915/display/intel_display_types.h | 32 ++++++++++++---
> > > ----
> > > drivers/gpu/drm/i915/intel_pm.c | 5 ++-
> > > 5 files changed, 62 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index d043057d2fa0..0db9c66d3c0f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct
> > > drm_atomic_state *s)
> > > state->dpll_set = state->modeset = false;
> > > state->global_state_changed = false;
> > > state->active_pipes = 0;
> > > + state->ddb_state_changed = false;
> > > + state->bw_state_changed = false;
> >
> > Not really liking these.
> >
> > After some pondering I was thinking along the lines of something
> > simple
> > like this:
> >
> > struct bw_state {
> > u8 sagv_reject;
> > };
> >
> > bw_check()
> > {
> > for_each_crtc_in_state() {
> > if (sagv_possible(crtc_state))
> > new->sagv_reject &= ~BIT(pipe);
> > else
> > new->sagv_reject |= BIT(pipe);
> > }
> >
> > calculate new->qgv_mask
> > }
>
> This is exactly what's done in the next patch, except
> that I store pipe, which are allowed to have SAGV, i.e:
I think inverted mask idea leads to neater code because then we
don't have to care which pipes are actually present in the hw
and which are fused off/not present:
sagv_reject == 0 -> SAGV possible
sagv_reject != 0 -> SAGV not possible
>
> struct intel_bw_state {
> struct intel_global_state base;
>
> + /*
> + * Contains a bit mask, used to determine, whether
> correspondent
> + * pipe allows SAGV or not.
> + */
> + u8 pipe_sagv_mask;
> +
> + /*
> + * Used to determine if we already had calculated
> + * SAGV mask for this state once.
> + */
> + bool sagv_calculated;
> +
> + /*
> + * Contains final SAGV decision based on current mask,
> + * to prevent doing the same job over and over again.
> + */
> + bool can_sagv;
> +
>
> Also the mask is calculated almost exactly same way:
>
> static void icl_compute_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int i;
> + struct intel_bw_state *new_bw_state =
> intel_bw_get_state(state);
> +
> + if (IS_ERR(new_bw_state)) {
> + WARN(1, "Could not get bw_state\n");
> + return;
> + }
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
> + new_bw_state->pipe_sagv_mask |= BIT(crtc-
> >pipe);
> + else
> + new_bw_state->pipe_sagv_mask &= ~BIT(crtc-
> >pipe);
> + }
> +}
>
> But this patch is not about that - it is about how we signal/determine
> that some change has to be written at commit stage.
> As you remember when we were discussed offline, I just wanted to have
> some expicit way to mark if some global state subsystem had changed,
> without having to do any additional checks, because imho all the checks
> we should do during atomic check, while commit simply applies what has
> to be applied.
>
> If you are really against having those boolean or any other way to be
> able so simply mark some stage object "dirty" (just like mem pages
> analogy) then would vote at least to have some helper functions to do
> that.
> i.e smth like:
>
> bool pipe_sagv_mask_changed(..)
This is just a !=, no? Don't see a function really making it any more clear.
>
> bool ddb_state_changed(...)
So far I don't see any real need to check for that.
>
> Stan
>
> >
> > > }
> > >
> > > struct intel_crtc_state *
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index bdad7476dc7b..d5be603b8b03 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > struct intel_crtc *crtc;
> > > int i, ret;
> > >
> > > - /* FIXME earlier gens need some checks too */
> > > - if (INTEL_GEN(dev_priv) < 11)
> > > + /*
> > > + * For earlier Gens let's consider bandwidth changed if ddb
> > > requirements,
> > > + * has been changed.
> > > + */
> > > + if (INTEL_GEN(dev_priv) < 11) {
> > > + if (state->ddb_state_changed) {
> > > + bw_state = intel_bw_get_state(state);
> > > + if (IS_ERR(bw_state))
> > > + return PTR_ERR(bw_state);
> > > +
> > > + ret = intel_atomic_lock_global_state(&bw_state-
> > > >base);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + DRM_DEBUG_KMS("Marking bw state changed for
> > > atomic state %p\n",
> > > + state);
> > > +
> > > + state->bw_state_changed = true;
> > > + }
> > > return 0;
> > > + }
> > >
> > > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > new_crtc_state, i) {
> > > @@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > old_active_planes == new_active_planes)
> > > continue;
> > >
> > > - bw_state = intel_bw_get_state(state);
> > > + bw_state = intel_bw_get_state(state);
> > > if (IS_ERR(bw_state))
> > > return PTR_ERR(bw_state);
> > >
> > > @@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct
> > > intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
> > > state);
> > > +
> > > + state->bw_state_changed = true;
> > > +
> > > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > > bw_state);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 3031e64ee518..137fb645097a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15540,8 +15540,10 @@ static void
> > > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > * SKL workaround: bspec recommends we disable the SAGV
> > > when we
> > > * have more then one pipe enabled
> > > */
> > > - if (!intel_can_enable_sagv(state))
> > > - intel_disable_sagv(dev_priv);
> > > + if (state->bw_state_changed) {
> > > + if (!intel_can_enable_sagv(state))
> > > + intel_disable_sagv(dev_priv);
> > > + }
> > >
> > > intel_modeset_verify_disabled(dev_priv, state);
> > > }
> > > @@ -15565,7 +15567,7 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > intel_encoders_update_prepare(state);
> > >
> > > /* Enable all new slices, we might need */
> > > - if (state->modeset)
> > > + if (state->ddb_state_changed)
> > > icl_dbuf_slice_pre_update(state);
> > >
> > > /* Now enable the clocks, plane, pipe, and connectors that we
> > > set up. */
> > > @@ -15622,7 +15624,7 @@ static void intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > }
> > >
> > > /* Disable all slices, we don't need */
> > > - if (state->modeset)
> > > + if (state->ddb_state_changed)
> > > icl_dbuf_slice_post_update(state);
> > >
> > > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state, new_crtc_state, i) {
> > > @@ -15641,8 +15643,10 @@ static void
> > > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > if (state->modeset)
> > > intel_verify_planes(state);
> > >
> > > - if (state->modeset && intel_can_enable_sagv(state))
> > > - intel_enable_sagv(dev_priv);
> > > + if (state->bw_state_changed) {
> > > + if (intel_can_enable_sagv(state)
> > > + intel_enable_sagv(dev_priv);
> > > + }
> > >
> > > drm_atomic_helper_commit_hw_done(&state->base);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 0d8a64305464..12b47ba3c68d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -471,16 +471,6 @@ struct intel_atomic_state {
> > >
> > > bool dpll_set, modeset;
> > >
> > > - /*
> > > - * Does this transaction change the pipes that are
> > > active? This mask
> > > - * tracks which CRTC's have changed their active state at the
> > > end of
> > > - * the transaction (not counting the temporary disable during
> > > modesets).
> > > - * This mask should only be non-zero when intel_state->modeset
> > > is true,
> > > - * but the converse is not necessarily true; simply changing a
> > > mode may
> > > - * not flip the final active status of any CRTC's
> > > - */
> > > - u8 active_pipe_changes;
> > > -
> > > u8 active_pipes;
> > >
> > > struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
> > > @@ -494,10 +484,30 @@ struct intel_atomic_state {
> > > bool rps_interactive;
> > >
> > > /*
> > > - * active_pipes
> > > + * active pipes
> > > */
> > > bool global_state_changed;
> > >
> > > + /*
> > > + * Does this transaction change the pipes that are
> > > active? This mask
> > > + * tracks which CRTC's have changed their active state at the
> > > end of
> > > + * the transaction (not counting the temporary disable during
> > > modesets).
> > > + * This mask should only be non-zero when intel_state->modeset
> > > is true,
> > > + * but the converse is not necessarily true; simply changing a
> > > mode may
> > > + * not flip the final active status of any CRTC's
> > > + */
> > > + u8 active_pipe_changes;
> > > +
> > > + /*
> > > + * More granular change indicator for ddb changes
> > > + */
> > > + bool ddb_state_changed;
> > > +
> > > + /*
> > > + * More granular change indicator for bandwidth state changes
> > > + */
> > > + bool bw_state_changed;
> > > +
> > > /* Number of enabled DBuf slices */
> > > u8 enabled_dbuf_slices_mask;
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 409b91c17a7f..ac4b317ea1bf 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> > > drm_i915_private *dev_priv,
> > > * that changes the active CRTC list or do modeset would need
> > > to
> > > * grab _all_ crtc locks, including the one we currently hold.
> > > */
> > > - if (!intel_state->active_pipe_changes && !intel_state->modeset)
> > > {
> > > + if (!intel_state->ddb_state_changed) {
> > > /*
> > > * alloc may be cleared by clear_intel_crtc_state,
> > > * copy from old state to be sure
> > > @@ -5787,6 +5787,9 @@ static int skl_wm_add_affected_planes(struct
> > > intel_atomic_state *state,
> > > return PTR_ERR(plane_state);
> > >
> > > new_crtc_state->update_planes |= BIT(plane_id);
> > > +
> > > + DRM_DEBUG_KMS("Marking ddb state changed for atomic
> > > state %p\n", state);
> > > + state->ddb_state_changed = true;
> > > }
> > >
> > > return 0;
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> >
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-02-27 16:20 ` Ville Syrjälä
@ 2020-03-02 13:15 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 33+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-02 13:15 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2020-02-27 at 18:20 +0200, Ville Syrjälä wrote:
> On Tue, Feb 25, 2020 at 05:00:43PM +0200, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> >
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> > values.
> >
> > v3: Forbid simultaneous legacy SAGV PCode requests and
> > restricting qgv points. Put the actual restriction
> > to commit function, added serialization(thanks to Ville)
> > to prevent commit being applied out of order in case of
> > nonblocking and/or nomodeset commits.
> >
> > v4:
> > - Minor code refactoring, fixed few typos(thanks to James
> > Ausmus)
> > - Change the naming of qgv point
> > masking/unmasking functions(James Ausmus).
> > - Simplify the masking/unmasking operation itself,
> > as we don't need to mask only single point per request(James
> > Ausmus)
> > - Reject and stick to highest bandwidth point if SAGV
> > can't be enabled(BSpec)
> >
> > v5:
> > - Add new mailbox reply codes, which seems to happen during
> > boot
> > time for TGL and indicate that QGV setting is not yet
> > available.
> >
> > v6:
> > - Increase number of supported QGV points to be in sync with
> > BSpec.
> >
> > v7: - Rebased and resolved conflict to fix build failure.
> > - Fix NUM_QGV_POINTS to 8 and moved that to header file(James
> > Ausmus)
> >
> > v8: - Don't report an error if we can't restrict qgv points, as
> > SAGV
> > can be disabled by BIOS, which is completely legal. So don't
> > make CI panic. Instead if we detect that there is only 1 QGV
> > point accessible just analyze if we can fit the required
> > bandwidth
> > requirements, but no need in restricting.
> >
> > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> > simultaneously.
> >
> > v10: - Fix CDCLK corruption, because of global state getting
> > serialized
> > without modeset, which caused copying of non-calculated
> > cdclk
> > to be copied to dev_priv(thanks to Ville for the hint).
> >
> > v11: - Remove unneeded headers and spaces(Matthew Roper)
> > - Remove unneeded intel_qgv_info qi struct from bw check and
> > zero
> > out the needed one(Matthew Roper)
> > - Changed QGV error message to have more clear meaning(Matthew
> > Roper)
> > - Use state->modeset_set instead of any_ms(Matthew Roper)
> > - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where
> > it's used
> > - Keep using crtc_state->hw.active instead of .enable(Matthew
> > Roper)
> > - Moved unrelated changes to other patch(using latency as
> > parameter
> > for plane wm calculation, moved to SAGV refactoring patch)
> >
> > v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
> > - Remove unnecessary mask being zero check when unmasking
> > qgv points as this is completely legal(Matt Roper)
> > - Check if we are setting the same mask as already being set
> > in hardware to prevent error from PCode.
> > - Fix error message when restricting/unrestricting qgv points
> > to "mask/unmask" which sounds more accurate(Matt Roper)
> > - Move sagv status setting to icl_get_bw_info from atomic
> > check
> > as this should be calculated only once.(Matt Roper)
> > - Edited comments for the case when we can't enable SAGV and
> > use only 1 QGV point with highest bandwidth to be more
> > understandable.(Matt Roper)
> >
> > v13: - Moved max_data_rate in bw check to closer scope(Ville
> > Syrjälä)
> > - Changed comment for zero new_mask in qgv points masking
> > function
> > to better reflect reality(Ville Syrjälä)
> > - Simplified bit mask operation in qgv points masking function
> > (Ville Syrjälä)
> > - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
> > however this still can't be under modeset condition(Ville
> > Syrjälä)
> > - Packed qgv_points_mask as u8 and moved closer to
> > pipe_sagv_mask
> > (Ville Syrjälä)
> > - Extracted PCode changes to separate patch.(Ville Syrjälä)
> > - Now treat num_planes 0 same as 1 to avoid confusion and
> > returning max_bw as 0, which would prevent choosing QGV
> > point having max bandwidth in case if SAGV is not allowed,
> > as per BSpec(Ville Syrjälä)
> > - Do the actual qgv_points_mask swap in the same place as
> > all other global state parts like cdclk are swapped.
> > In the next patch, this all will be moved to bw state as
> > global state, once new global state patch series from Ville
> > lands
> >
> > v14: - Now using global state to serialize access to qgv points
> > - Added global state locking back, otherwise we seem to read
> > bw state in a wrong way.
> >
> > v15: - Added TODO comment for near atomic global state locking in
> > bw code.
> >
> > v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as
> > discussed
> > with Jani Nikula.
> > - Take bw_state_changed flag into use.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 184 +++++++++++++
> > ------
> > drivers/gpu/drm/i915/display/intel_bw.h | 9 +
> > drivers/gpu/drm/i915/display/intel_display.c | 125 ++++++++++++-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 4 files changed, 255 insertions(+), 66 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index d5be603b8b03..4986a5464700 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -8,6 +8,9 @@
> > #include "intel_bw.h"
> > #include "intel_display_types.h"
> > #include "intel_sideband.h"
> > +#include "intel_atomic.h"
> > +#include "intel_pm.h"
> > +
> >
> > /* Parameters for Qclk Geyserville (QGV) */
> > struct intel_qgv_point {
> > @@ -113,6 +116,26 @@ static int
> > icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> > return 0;
> > }
> >
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > + u32 points_mask)
> > +{
> > + int ret;
> > +
> > + /* bspec says to keep retrying for at least 1 ms */
> > + ret = skl_pcode_request(dev_priv,
> > ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> > + points_mask,
> > + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> > + GEN11_PCODE_POINTS_RESTRICTED,
> > + 1);
> > +
> > + if (ret < 0) {
> > + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> > struct intel_qgv_info *qi)
> > {
> > @@ -240,6 +263,16 @@ static int icl_get_bw_info(struct
> > drm_i915_private *dev_priv, const struct intel
> > break;
> > }
> >
> > + /*
> > + * In case if SAGV is disabled in BIOS, we always get 1
> > + * SAGV point, but we can't send PCode commands to restrict it
> > + * as it will fail and pointless anyway.
> > + */
> > + if (qi.num_points == 1)
> > + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> > + else
> > + dev_priv->sagv_status = I915_SAGV_ENABLED;
> > +
> > return 0;
> > }
> >
> > @@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct
> > drm_i915_private *dev_priv,
> > if (qgv_point >= bi->num_qgv_points)
> > return UINT_MAX;
> >
> > - if (num_planes >= bi->num_planes)
> > + if (num_planes >= bi->num_planes || !num_planes)
> > return bi->deratedbw[qgv_point];
> > }
> >
> > @@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private
> > *dev_priv)
> > icl_get_bw_info(dev_priv, &icl_sa_info);
> > }
> >
> > -static unsigned int intel_max_data_rate(struct drm_i915_private
> > *dev_priv,
> > - int num_planes)
> > -{
> > - if (INTEL_GEN(dev_priv) >= 11) {
> > - /*
> > - * Any bw group has same amount of QGV points
> > - */
> > - const struct intel_bw_info *bi =
> > - &dev_priv->max_bw[0];
> > - unsigned int min_bw = UINT_MAX;
> > - int i;
> > -
> > - /*
> > - * FIXME with SAGV disabled maybe we can assume
> > - * point 1 will always be used? Seems to match
> > - * the behaviour observed in the wild.
> > - */
> > - for (i = 0; i < bi->num_qgv_points; i++) {
> > - unsigned int bw = icl_max_bw(dev_priv,
> > num_planes, i);
> > -
> > - min_bw = min(bw, min_bw);
> > - }
> > - return min_bw;
> > - } else {
> > - return UINT_MAX;
> > - }
> > -}
> > -
> > static unsigned int intel_bw_crtc_num_active_planes(const struct
> > intel_crtc_state *crtc_state)
> > {
> > /*
> > @@ -418,11 +423,16 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > - struct intel_bw_state *bw_state = NULL;
> > - unsigned int data_rate, max_data_rate;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + struct intel_bw_state *old_bw_state = NULL;
> > + unsigned int data_rate;
> > unsigned int num_active_planes;
> > struct intel_crtc *crtc;
> > int i, ret;
> > + u32 allowed_points = 0;
> > + unsigned int max_bw_point = 0, max_bw = 0;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + u32 mask = (1 << num_qgv_points) - 1;
> >
> > /*
> > * For earlier Gens let's consider bandwidth changed if ddb
> > requirements,
> > @@ -430,11 +440,11 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > */
> > if (INTEL_GEN(dev_priv) < 11) {
> > if (state->ddb_state_changed) {
> > - bw_state = intel_bw_get_state(state);
> > - if (IS_ERR(bw_state))
> > - return PTR_ERR(bw_state);
> > + new_bw_state = intel_bw_get_state(state);
> > + if (IS_ERR(new_bw_state))
> > + return PTR_ERR(new_bw_state);
>
> Lot's of rename noise in the patch. Can't really see what's going on
> unless those are split out.
>
> >
> > - ret = intel_atomic_lock_global_state(&bw_state-
> > >base);
> > + ret =
> > intel_atomic_lock_global_state(&new_bw_state->base);
> > if (ret)
> > return ret;
> >
> > @@ -465,45 +475,107 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > old_active_planes == new_active_planes)
> > continue;
> >
> > - bw_state = intel_bw_get_state(state);
> > - if (IS_ERR(bw_state))
> > - return PTR_ERR(bw_state);
> > + new_bw_state = intel_bw_get_state(state);
> > + if (IS_ERR(new_bw_state))
> > + return PTR_ERR(new_bw_state);
> >
> > - bw_state->data_rate[crtc->pipe] = new_data_rate;
> > - bw_state->num_active_planes[crtc->pipe] =
> > new_active_planes;
> > + new_bw_state->data_rate[crtc->pipe] = new_data_rate;
> > + new_bw_state->num_active_planes[crtc->pipe] =
> > new_active_planes;
> >
> > drm_dbg_kms(&dev_priv->drm,
> > "pipe %c data rate %u num active planes
> > %u\n",
> > pipe_name(crtc->pipe),
> > - bw_state->data_rate[crtc->pipe],
> > - bw_state->num_active_planes[crtc->pipe]);
> > + new_bw_state->data_rate[crtc->pipe],
> > + new_bw_state->num_active_planes[crtc-
> > >pipe]);
> > }
> >
> > - if (!bw_state)
> > + if (!new_bw_state)
> > return 0;
> >
> > - ret = intel_atomic_lock_global_state(&bw_state->base);
> > - if (ret)
> > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > + if (ret) {
> > + DRM_DEBUG_KMS("Could not lock global state\n");
> > return ret;
> > + }
> >
> > - DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n",
> > state);
> > -
> > - state->bw_state_changed = true;
> > + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> > + data_rate = DIV_ROUND_UP(data_rate, 1000);
> >
> > - data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > - num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> > + num_active_planes = intel_bw_num_active_planes(dev_priv,
> > new_bw_state);
> >
> > - max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > + for (i = 0; i < num_qgv_points; i++) {
> > + unsigned int max_data_rate;
> >
> > - data_rate = DIV_ROUND_UP(data_rate, 1000);
> > + max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > + /*
> > + * We need to know which qgv point gives us
> > + * maximum bandwidth in order to disable SAGV
> > + * if we find that we exceed SAGV block time
> > + * with watermarks. By that moment we already
> > + * have those, as it is calculated earlier in
> > + * intel_atomic_check,
> > + */
> > + if (max_data_rate > max_bw) {
> > + max_bw_point = i;
> > + max_bw = max_data_rate;
> > + }
> > + if (max_data_rate >= data_rate)
> > + allowed_points |= BIT(i);
> > + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> > + i, max_data_rate, data_rate);
> > + }
> >
> > - if (data_rate > max_data_rate) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "Bandwidth %u MB/s exceeds max available %d
> > MB/s (%d active planes)\n",
> > - data_rate, max_data_rate,
> > num_active_planes);
> > + /*
> > + * BSpec states that we always should have at least one allowed
> > point
> > + * left, so if we couldn't - simply reject the configuration
> > for obvious
> > + * reasons.
> > + */
> > + if (allowed_points == 0) {
> > + DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> > + " bandwidth for display
> > configuration.\n");
> > return -EINVAL;
> > }
> >
> > + /*
> > + * Leave only single point with highest bandwidth, if
> > + * we can't enable SAGV due to the increased memory latency it
> > may
> > + * cause.
> > + */
> > + if (!intel_can_enable_sagv_for_state(state)) {
> > + allowed_points = 1 << max_bw_point;
> > + DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> > + max_bw_point);
> > + }
> > + /*
> > + * We store the ones which need to be masked as that is what
> > PCode
> > + * actually accepts as a parameter.
> > + */
> > + new_bw_state->qgv_points_mask = (~allowed_points) & mask;
> > +
> > + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> > + state, new_bw_state->qgv_points_mask);
> > +
> > + old_bw_state = intel_bw_get_old_state(state);
> > + if (IS_ERR(old_bw_state)) {
> > + DRM_DEBUG_KMS("Could not get old bw state!\n");
> > + return PTR_ERR(old_bw_state);
> > + }
> > +
> > + /*
> > + * If the actual mask had changed we need to make sure that
> > + * the commits are serialized(in case this is a nomodeset,
> > nonblocking)
> > + */
> > + if (new_bw_state->qgv_points_mask != old_bw_state-
> > >qgv_points_mask) {
> > + ret =
> > intel_atomic_serialize_global_state(&new_bw_state->base);
> > + if (ret) {
> > + DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > + return ret;
> > + }
> > +
> > + DRM_DEBUG_KMS("Marking bw state changed for atomic
> > state %p\n", state);
> > + state->bw_state_changed = true;
> > + }
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index c32b5285c12f..b3522389a181 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -36,6 +36,13 @@ struct intel_bw_state {
> > */
> > bool can_sagv;
> >
> > + /*
> > + * Current QGV points mask, which restricts
> > + * some particular SAGV states, not to confuse
> > + * with pipe_sagv_mask.
> > + */
> > + u8 qgv_points_mask;
> > +
> > unsigned int data_rate[I915_MAX_PIPES];
> > u8 num_active_planes[I915_MAX_PIPES];
> > };
> > @@ -56,5 +63,7 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > const struct intel_crtc_state *crtc_state);
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > + u32 points_mask);
> >
> > #endif /* __INTEL_BW_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6df836cbe0cd..cb1d10af88ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15504,6 +15504,105 @@ static void
> > intel_atomic_cleanup_work(struct work_struct *work)
> > intel_atomic_helper_free_state(i915);
> > }
> >
> > +static void intel_qgv_points_mask(struct intel_atomic_state
> > *state)
>
> I think we should move these next to the other sagv code and just
> call them somehting like intel_sagv_{pre,post}_plane_update() to
> a) avoid the caller having to know anything about them, b) match
> the pattern used for other similar things.
>
> And I think the internals should just be something like:
> intel_sagv_pre/post_plane_update()
> {
> new_bw_state = get_new_bw_state();
> old_bw_state = get_old_bw_state();
>
> if (!new_bw_state ||
> new_bw_state->sagv_mask == old_bw_state->sagv_mask)
> return;
>
> do the pcode dance
> }
>
> I don't see a need for any more checks than than because that
> would just mean that bw_check() is broken and needs to be fixed.
Those are actually qgv points mask, also you _have to_ do some
other checks - for example when we are masking qgv points - it means
we can only mask those however for example transition 0x001 (qgv point
0 masked) to 0x000(new mask), means that there is nothing to mask here
and moreover it will be wrong to call PCode at this point.
Stan
>
>
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + struct intel_bw_state *old_bw_state = NULL;
> > + u32 new_mask = 0;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + unsigned int mask = (1 << num_qgv_points) - 1;
> > +
> > + new_bw_state = intel_bw_get_state(state);
> > + if (IS_ERR(new_bw_state)) {
> > + WARN(1, "Could not get new bw_state!\n");
> > + return;
> > + }
> > +
> > + old_bw_state = intel_bw_get_old_state(state);
> > + if (IS_ERR(old_bw_state)) {
> > + WARN(1, "Could not get old bw_state!\n");
> > + return;
> > + }
> > +
> > + new_mask = old_bw_state->qgv_points_mask | new_bw_state-
> > >qgv_points_mask;
> > +
> > + /*
> > + * If new mask is zero - means there is nothing to mask,
> > + * we can only unmask, which should be done in unmask.
> > + */
> > + if (!new_mask)
> > + return;
> > +
> > + WARN_ON(new_mask == mask);
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Restrict required qgv points before updating the
> > configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not mask required qgv
> > points(%d)\n",
> > + ret);
> > +}
> > +
> > +static void intel_qgv_points_unmask(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + struct intel_bw_state *old_bw_state = NULL;
> > + u32 new_mask = 0;
> > +
> > + new_bw_state = intel_bw_get_state(state);
> > + if (IS_ERR(new_bw_state)) {
> > + WARN(1, "Could not get new bw_state!\n");
> > + return;
> > + }
> > +
> > + old_bw_state = intel_bw_get_old_state(state);
> > + if (IS_ERR(old_bw_state)) {
> > + WARN(1, "Could not get new bw_state!\n");
> > + return;
> > + }
> > +
> > + new_mask = new_bw_state->qgv_points_mask;
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Nothing to unmask
> > + */
> > + if (new_mask == old_bw_state->qgv_points_mask)
> > + return;
> > +
> > + /*
> > + * Allow required qgv points after updating the configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not unmask required qgv
> > points(%d)\n",
> > + ret);
> > +}
> > +
> > static void intel_atomic_commit_tail(struct intel_atomic_state
> > *state)
> > {
> > struct drm_device *dev = state->base.dev;
> > @@ -15537,6 +15636,15 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> > i)
> > crtc->config = new_crtc_state;
> >
> > + /*
> > + * Now we need to check if SAGV needs to be disabled(i.e QGV
> > points
> > + * modified even, when no modeset is done(for example plane
> > updates
> > + * can now trigger that).
> > + */
> > + if ((INTEL_GEN(dev_priv) >= 11))
> > + if (state->bw_state_changed)
> > + intel_qgv_points_mask(state);
> > +
> > if (state->modeset) {
> > drm_atomic_helper_update_legacy_modeset_state(dev,
> > &state->base);
> >
> > @@ -15546,12 +15654,9 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > * SKL workaround: bspec recommends we disable the SAGV
> > when we
> > * have more then one pipe enabled
> > */
> > - if (INTEL_GEN(dev_priv) < 11) {
> > - if (state->bw_state_changed) {
> > - if (!intel_can_enable_sagv(dev_priv))
> > - intel_disable_sagv(dev_priv);
> > - }
> > - }
> > + if ((INTEL_GEN(dev_priv) < 11))
> > + if (!intel_can_enable_sagv(dev_priv))
> > + intel_disable_sagv(dev_priv);
> >
> > intel_modeset_verify_disabled(dev_priv, state);
> > }
> > @@ -15652,10 +15757,10 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > intel_verify_planes(state);
> >
> > if (INTEL_GEN(dev_priv) < 11) {
> > - if (state->bw_state_changed) {
> > - if (intel_can_enable_sagv(dev_priv))
> > - intel_enable_sagv(dev_priv);
> > - }
> > + if (intel_can_enable_sagv(dev_priv))
> > + intel_enable_sagv(dev_priv);
> > + } else if (state->bw_state_changed) {
> > + intel_qgv_points_unmask(state);
> > }
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 4305ccc4c683..0a589700a071 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -841,6 +841,9 @@ enum intel_pipe_crc_source {
> > INTEL_PIPE_CRC_SOURCE_MAX,
> > };
> >
> > +/* BSpec precisely defines this */
> > +#define NUM_SAGV_POINTS 8
> > +
> > #define INTEL_PIPE_CRC_ENTRIES_NR 128
> > struct intel_pipe_crc {
> > spinlock_t lock;
> > --
> > 2.24.1.485.gad05a3d8e5
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2020-03-02 13:15 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-24 15:32 [Intel-gfx] [PATCH v18 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-02-27 16:28 ` Ville Syrjälä
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-02-27 15:51 ` Ville Syrjälä
2020-02-28 12:23 ` Lisovskiy, Stanislav
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
2020-02-27 15:53 ` Ville Syrjälä
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators Stanislav Lisovskiy
2020-02-25 14:57 ` Stanislav Lisovskiy
2020-02-27 16:12 ` Ville Syrjälä
2020-02-28 8:56 ` Lisovskiy, Stanislav
2020-02-28 16:12 ` Ville Syrjälä
2020-02-29 9:34 ` Lisovskiy, Stanislav
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2020-02-25 14:59 ` Stanislav Lisovskiy
2020-02-27 11:46 ` Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 6/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-02-25 15:00 ` Stanislav Lisovskiy
2020-02-27 16:20 ` Ville Syrjälä
2020-03-02 13:15 ` Lisovskiy, Stanislav
2020-02-24 15:32 ` [Intel-gfx] [PATCH v18 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-02-24 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
2020-02-24 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-24 19:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-02-26 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev5) Patchwork
2020-02-26 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-26 22:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-02-27 15:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev6) Patchwork
2020-02-27 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-27 15:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28 17:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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