From mboxrd@z Thu Jan 1 00:00:00 1970 From: Giulio Benetti Date: Wed, 26 Feb 2020 18:15:46 +0100 Subject: [PATCH 03/18] clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL In-Reply-To: <20200226171601.31142-1-giulio.benetti@benettiengineering.com> References: <20200226171601.31142-1-giulio.benetti@benettiengineering.com> Message-ID: <20200226171601.31142-4-giulio.benetti@benettiengineering.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de mxsfb needs PLL5 as source, so let's setup it and set it as source for mxsfb(lcdif). Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-imxrt1050.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index e33d426363..2819ffb9ac 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_dm(IMXRT1050_CLK_LCDIF, imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); -#ifdef CONFIG_SPL_BUILD struct clk *clk, *clk1; +#ifdef CONFIG_SPL_BUILD /* bypass pll1 before setting its rate */ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk); clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1); @@ -271,7 +271,18 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1); clk_set_parent(clk1, clk); +#else + /* Set PLL5 for LCDIF to its default 650Mhz */ + clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk); + clk_enable(clk); + clk_set_rate(clk, 650000000UL); + + clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1); + clk_set_parent(clk1, clk); + /* Configure PLL5 as LCDIF source */ + clk_get_by_id(IMXRT1050_CLK_LCDIF_SEL, &clk1); + clk_set_parent(clk1, clk); #endif return 0; -- 2.20.1