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Wed, 26 Feb 2020 13:25:36 -0500 (EST) Date: Wed, 26 Feb 2020 19:25:34 +0100 From: Maxime Ripard To: Andre Przywara Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas , Jens Axboe Subject: Re: [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller to json-schema Message-ID: <20200226182534.rjdzoam4zdyduvos@gilmour.lan> References: <20200226180901.89940-1-andre.przywara@arm.com> <20200226180901.89940-7-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="avyufeofezvwvp7g" Content-Disposition: inline In-Reply-To: <20200226180901.89940-7-andre.przywara@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --avyufeofezvwvp7g Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 26, 2020 at 06:08:54PM +0000, Andre Przywara wrote: > Convert the Calxeda Highbank SATA controller binding to DT schema format > using json-schema. > > Signed-off-by: Andre Przywara > Cc: Jens Axboe > --- > .../devicetree/bindings/ata/sata_highbank.txt | 44 --------- > .../bindings/ata/sata_highbank.yaml | 96 +++++++++++++++++++ > 2 files changed, 96 insertions(+), 44 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt > create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml > > diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt > deleted file mode 100644 > index aa83407cb7a4..000000000000 > --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt > +++ /dev/null > @@ -1,44 +0,0 @@ > -* Calxeda AHCI SATA Controller > - > -SATA nodes are defined to describe on-chip Serial ATA controllers. > -The Calxeda SATA controller mostly conforms to the AHCI interface > -with some special extensions to add functionality. > -Each SATA controller should have its own node. > - > -Required properties: > -- compatible : compatible list, contains "calxeda,hb-ahci" > -- interrupts : > -- reg : > - > -Optional properties: > -- dma-coherent : Present if dma operations are coherent > -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each > - SATA port to a combophy and a lane within that > - combophy > -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, > - which indicates that the driver supports SGPIO > - indicator lights using the indicated GPIOs > -- calxeda,led-order : a u32 array that map port numbers to offsets within the > - SGPIO bitstream. > -- calxeda,tx-atten : a u32 array that contains TX attenuation override > - codes, one per port. The upper 3 bytes are always > - 0 and thus ignored. > -- calxeda,pre-clocks : a u32 that indicates the number of additional clock > - cycles to transmit before sending an SGPIO pattern > -- calxeda,post-clocks: a u32 that indicates the number of additional clock > - cycles to transmit after sending an SGPIO pattern > - > -Example: > - sata@ffe08000 { > - compatible = "calxeda,hb-ahci"; > - reg = <0xffe08000 0x1000>; > - interrupts = <115>; > - dma-coherent; > - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 > - &combophy0 2 &combophy0 3>; > - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; > - calxeda,led-order = <4 0 1 2 3>; > - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; > - calxeda,pre-clocks = <10>; > - calxeda,post-clocks = <0>; > - }; > diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml > new file mode 100644 > index 000000000000..392a3efc9833 > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Calxeda AHCI SATA Controller > + > +description: | > + The Calxeda SATA controller mostly conforms to the AHCI interface > + with some special extensions to add functionality, to map GPIOs for > + activity LEDs and for mapping the ComboPHYs. > + > +maintainers: > + - Andre Przywara > + > +properties: > + compatible: > + const: calxeda,hb-ahci > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + dma-coherent: true > + > + calxeda,pre-clocks: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Indicates the number of additional clock cycles to transmit before > + sending an SGPIO pattern. > + > + calxeda,post-clocks: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Indicates the number of additional clock cycles to transmit after > + sending an SGPIO pattern. > + > + calxeda,led-order: > + description: Maps port numbers to offsets within the SGPIO bitstream. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,port-phys: > + description: | > + phandle-combophy and lane assignment, which maps each SATA port to a > + combophy and a lane within that combophy > + allOf: > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,tx-atten: > + description: | > + Contains TX attenuation override codes, one per port. > + The upper 24 bits of each entry are always 0 and thus ignored. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,sgpio-gpio: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + phandle-gpio bank, bit offset, and default on or off, which indicates > + that the driver supports SGPIO indicator lights using the indicated > + GPIOs. Ditto, this is being checked already: https://github.com/devicetree-org/dt-schema/blob/master/schemas/gpio/gpio.yaml#L37 --avyufeofezvwvp7g Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXla4HgAKCRDj7w1vZxhR xXwXAP9E9Nhzi9/iGC+DcEi2dO3dN9AdHfN5WZ299wBfbz7logD9FWasp+ZIwAPI gZzzMwdkwUcsGs8WM6shA0zZiW2XNg0= =oHQS -----END PGP SIGNATURE----- --avyufeofezvwvp7g-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FE22C4BA1E for ; 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Wed, 26 Feb 2020 13:25:36 -0500 (EST) Date: Wed, 26 Feb 2020 19:25:34 +0100 From: Maxime Ripard To: Andre Przywara Subject: Re: [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller to json-schema Message-ID: <20200226182534.rjdzoam4zdyduvos@gilmour.lan> References: <20200226180901.89940-1-andre.przywara@arm.com> <20200226180901.89940-7-andre.przywara@arm.com> MIME-Version: 1.0 In-Reply-To: <20200226180901.89940-7-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200226_102541_105043_5F29D878 X-CRM114-Status: GOOD ( 19.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jens Axboe , Rob Herring , Jon Loeliger , Mark Langsdorf , Robert Richter , devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Eric Auger , soc@kernel.org, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============3839758642025556854==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============3839758642025556854== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="avyufeofezvwvp7g" Content-Disposition: inline --avyufeofezvwvp7g Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 26, 2020 at 06:08:54PM +0000, Andre Przywara wrote: > Convert the Calxeda Highbank SATA controller binding to DT schema format > using json-schema. > > Signed-off-by: Andre Przywara > Cc: Jens Axboe > --- > .../devicetree/bindings/ata/sata_highbank.txt | 44 --------- > .../bindings/ata/sata_highbank.yaml | 96 +++++++++++++++++++ > 2 files changed, 96 insertions(+), 44 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt > create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml > > diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt > deleted file mode 100644 > index aa83407cb7a4..000000000000 > --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt > +++ /dev/null > @@ -1,44 +0,0 @@ > -* Calxeda AHCI SATA Controller > - > -SATA nodes are defined to describe on-chip Serial ATA controllers. > -The Calxeda SATA controller mostly conforms to the AHCI interface > -with some special extensions to add functionality. > -Each SATA controller should have its own node. > - > -Required properties: > -- compatible : compatible list, contains "calxeda,hb-ahci" > -- interrupts : > -- reg : > - > -Optional properties: > -- dma-coherent : Present if dma operations are coherent > -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each > - SATA port to a combophy and a lane within that > - combophy > -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, > - which indicates that the driver supports SGPIO > - indicator lights using the indicated GPIOs > -- calxeda,led-order : a u32 array that map port numbers to offsets within the > - SGPIO bitstream. > -- calxeda,tx-atten : a u32 array that contains TX attenuation override > - codes, one per port. The upper 3 bytes are always > - 0 and thus ignored. > -- calxeda,pre-clocks : a u32 that indicates the number of additional clock > - cycles to transmit before sending an SGPIO pattern > -- calxeda,post-clocks: a u32 that indicates the number of additional clock > - cycles to transmit after sending an SGPIO pattern > - > -Example: > - sata@ffe08000 { > - compatible = "calxeda,hb-ahci"; > - reg = <0xffe08000 0x1000>; > - interrupts = <115>; > - dma-coherent; > - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 > - &combophy0 2 &combophy0 3>; > - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; > - calxeda,led-order = <4 0 1 2 3>; > - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; > - calxeda,pre-clocks = <10>; > - calxeda,post-clocks = <0>; > - }; > diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml > new file mode 100644 > index 000000000000..392a3efc9833 > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Calxeda AHCI SATA Controller > + > +description: | > + The Calxeda SATA controller mostly conforms to the AHCI interface > + with some special extensions to add functionality, to map GPIOs for > + activity LEDs and for mapping the ComboPHYs. > + > +maintainers: > + - Andre Przywara > + > +properties: > + compatible: > + const: calxeda,hb-ahci > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + dma-coherent: true > + > + calxeda,pre-clocks: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Indicates the number of additional clock cycles to transmit before > + sending an SGPIO pattern. > + > + calxeda,post-clocks: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Indicates the number of additional clock cycles to transmit after > + sending an SGPIO pattern. > + > + calxeda,led-order: > + description: Maps port numbers to offsets within the SGPIO bitstream. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,port-phys: > + description: | > + phandle-combophy and lane assignment, which maps each SATA port to a > + combophy and a lane within that combophy > + allOf: > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,tx-atten: > + description: | > + Contains TX attenuation override codes, one per port. > + The upper 24 bits of each entry are always 0 and thus ignored. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + - minItems: 1 > + maxItems: 8 > + > + calxeda,sgpio-gpio: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + phandle-gpio bank, bit offset, and default on or off, which indicates > + that the driver supports SGPIO indicator lights using the indicated > + GPIOs. Ditto, this is being checked already: https://github.com/devicetree-org/dt-schema/blob/master/schemas/gpio/gpio.yaml#L37 --avyufeofezvwvp7g Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXla4HgAKCRDj7w1vZxhR xXwXAP9E9Nhzi9/iGC+DcEi2dO3dN9AdHfN5WZ299wBfbz7logD9FWasp+ZIwAPI gZzzMwdkwUcsGs8WM6shA0zZiW2XNg0= =oHQS -----END PGP SIGNATURE----- --avyufeofezvwvp7g-- --===============3839758642025556854== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============3839758642025556854==--