* [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking
@ 2020-02-26 20:34 Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
` (21 more replies)
0 siblings, 22 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
This patchset moves the platforms specific functions calculating the
DPLL frequency next to the counterpart functions calculating DPLL params
from a given frequency.
It also adds a way to track the DPLL reference clock frequencies in a
unified way across platforms.
Imre Deak (13):
drm/i915: Fix bounds check in intel_get_shared_dpll_id()
drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
drm/i915: Keep the global DPLL state in a DPLL specific struct
drm/i915: Move the DPLL vfunc inits after the func defines
drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
drm/i915/hsw: Split out the SPLL parameter calculation
drm/i915/hsw: Split out the WRPLL,LCPLL,SPLL frequency calculation
drm/i915/skl,cnl: Split out the WRPLL/LCPLL frequency calculation
drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out
again
drm/i915: Unify the DPLL ref clock frequency tracking
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 455 +---------
drivers/gpu/drm/i915/display/intel_ddi.h | 2 -
drivers/gpu/drm/i915/display/intel_display.c | 52 +-
.../drm/i915/display/intel_display_debugfs.c | 9 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 808 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 27 +-
8 files changed, 736 insertions(+), 643 deletions(-)
--
2.23.1
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^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id()
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c Imre Deak
` (20 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Fix an off-by-one error in the upper-bound check and while at it clear
up a bit the function.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e5bfe5245276..6cf291754390 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -103,11 +103,14 @@ enum intel_dpll_id
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- if (drm_WARN_ON(&dev_priv->drm, pll < dev_priv->shared_dplls ||
- pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
+ long pll_idx = pll - dev_priv->shared_dplls;
+
+ if (drm_WARN_ON(&dev_priv->drm,
+ pll_idx < 0 ||
+ pll_idx >= dev_priv->num_shared_dpll))
return -1;
- return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
+ return pll_idx;
}
/* For ILK+ */
--
2.23.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct Imre Deak
` (19 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Move the HW readout/sanitize functions to intel_dpll_mgr.c which
contains the rest of shared DPLL functionality.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +-------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +
3 files changed, 63 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2fd3ccd33e30..6eedf7254563 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18329,7 +18329,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
u8 active_pipes = 0;
- int i;
for_each_intel_crtc(dev, crtc) {
struct intel_crtc_state *crtc_state =
@@ -18358,33 +18357,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
readout_plane_state(dev_priv);
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
-
- pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
- &pll->state.hw_state);
-
- if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
- pll->wakeref = intel_display_power_get(dev_priv,
- POWER_DOMAIN_DPLL_DC_OFF);
- }
-
- pll->state.crtc_mask = 0;
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.active &&
- crtc_state->shared_dpll == pll)
- pll->state.crtc_mask |= 1 << crtc->pipe;
- }
- pll->active_mask = pll->state.crtc_mask;
-
- drm_dbg_kms(&dev_priv->drm,
- "%s hw state readout: crtc_mask 0x%08x, on %i\n",
- pll->info->name, pll->state.crtc_mask, pll->on);
- }
+ intel_dpll_readout_hw_state(dev_priv);
for_each_intel_encoder(dev, encoder) {
pipe = 0;
@@ -18641,7 +18614,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
- int i;
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -18694,19 +18666,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_modeset_update_connector_atomic_state(dev);
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
-
- if (!pll->on || pll->active_mask)
- continue;
-
- drm_dbg_kms(&dev_priv->drm,
- "%s enabled but not in use, disabling\n",
- pll->info->name);
-
- pll->info->funcs->disable(dev_priv, pll);
- pll->on = false;
- }
+ intel_dpll_sanitize_state(dev_priv);
if (IS_G4X(dev_priv)) {
g4x_wm_get_hw_state(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6cf291754390..3a937b94d487 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3919,6 +3919,65 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
dpll_mgr->update_active_dpll(state, crtc, encoder);
}
+static void readout_dpll_hw_state(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll)
+{
+ struct intel_crtc *crtc;
+
+ pll->on = pll->info->funcs->get_hw_state(i915, pll,
+ &pll->state.hw_state);
+
+ if (IS_ELKHARTLAKE(i915) && pll->on &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ pll->wakeref = intel_display_power_get(i915,
+ POWER_DOMAIN_DPLL_DC_OFF);
+ }
+
+ pll->state.crtc_mask = 0;
+ for_each_intel_crtc(&i915->drm, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
+ pll->state.crtc_mask |= 1 << crtc->pipe;
+ }
+ pll->active_mask = pll->state.crtc_mask;
+
+ drm_dbg_kms(&i915->drm,
+ "%s hw state readout: crtc_mask 0x%08x, on %i\n",
+ pll->info->name, pll->state.crtc_mask, pll->on);
+}
+
+void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+{
+ int i;
+
+ for (i = 0; i < i915->num_shared_dpll; i++)
+ readout_dpll_hw_state(i915, &i915->shared_dplls[i]);
+}
+
+static void sanitize_dpll_state(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll)
+{
+ if (!pll->on || pll->active_mask)
+ return;
+
+ drm_dbg_kms(&i915->drm,
+ "%s enabled but not in use, disabling\n",
+ pll->info->name);
+
+ pll->info->funcs->disable(i915, pll);
+ pll->on = false;
+}
+
+void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+{
+ int i;
+
+ for (i = 0; i < i915->num_shared_dpll; i++)
+ sanitize_dpll_state(i915, &i915->shared_dplls[i]);
+}
+
/**
* intel_shared_dpll_dump_hw_state - write hw_state to dmesg
* @dev_priv: i915 drm device
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2a104c64291d..fe27a5dfc51e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -377,6 +377,8 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_device *dev);
+void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
+void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state);
--
2.23.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines Imre Deak
` (18 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
For clarity add a new DPLL specific struct to the i915 device struct and
move all DPLL fields into it. Accordingly remove the dpll_ prefixes, as
the new struct already provides the required namespacing.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
drivers/gpu/drm/i915/display/intel_display.c | 8 ++-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 60 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 22 +++----
6 files changed, 61 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d842e280699d..c7214ace963a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -599,13 +599,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
@@ -615,13 +615,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void gen11_dsi_map_pll(struct intel_encoder *encoder,
@@ -633,7 +633,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
@@ -652,7 +652,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9f7d1d7189ae..e09ab0d44afa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3049,7 +3049,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
drm_WARN_ON(&dev_priv->drm,
@@ -3075,7 +3075,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
@@ -3084,13 +3084,13 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
@@ -3189,7 +3189,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
if (drm_WARN_ON(&dev_priv->drm, !pll))
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
if (INTEL_GEN(dev_priv) >= 11) {
if (!intel_phy_is_combo(dev_priv, phy))
@@ -3233,7 +3233,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
hsw_pll_to_ddi_pll_sel(pll));
}
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static void intel_ddi_clk_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6eedf7254563..0506562b2d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9552,7 +9552,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Check if any DPLLs are using the SSC source */
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
if (!(temp & DPLL_VCO_ENABLE))
@@ -14369,8 +14369,10 @@ verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
{
int i;
- for (i = 0; i < dev_priv->num_shared_dpll; i++)
- verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
+ verify_single_dpll_state(dev_priv,
+ &dev_priv->dpll.shared_dplls[i],
+ NULL, NULL);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 46954cc7b6c0..d2461d7946bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -920,8 +920,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
int i;
drm_modeset_lock_all(dev);
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
pll->info->id);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3a937b94d487..c02de061a166 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -52,8 +52,8 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
enum intel_dpll_id i;
/* Copy shared dpll state */
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
shared_dpll[i] = pll->state;
}
@@ -88,7 +88,7 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
{
- return &dev_priv->shared_dplls[id];
+ return &dev_priv->dpll.shared_dplls[id];
}
/**
@@ -103,11 +103,11 @@ enum intel_dpll_id
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- long pll_idx = pll - dev_priv->shared_dplls;
+ long pll_idx = pll - dev_priv->dpll.shared_dplls;
if (drm_WARN_ON(&dev_priv->drm,
pll_idx < 0 ||
- pll_idx >= dev_priv->num_shared_dpll))
+ pll_idx >= dev_priv->dpll.num_shared_dpll))
return -1;
return pll_idx;
@@ -147,7 +147,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask);
if (!pll->active_mask) {
drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);
@@ -156,7 +156,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->info->funcs->prepare(dev_priv, pll);
}
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
/**
@@ -176,7 +176,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
old_mask = pll->active_mask;
if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask)) ||
@@ -202,7 +202,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = true;
out:
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
/**
@@ -225,7 +225,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (pll == NULL)
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll.lock);
if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask)))
goto out;
@@ -246,7 +246,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = false;
out:
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll.lock);
}
static struct intel_shared_dpll *
@@ -265,7 +265,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
- pll = &dev_priv->shared_dplls[i];
+ pll = &dev_priv->dpll.shared_dplls[i];
/* Only want to check enabled timings first */
if (shared_dpll[i].crtc_mask == 0) {
@@ -365,9 +365,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll =
- &dev_priv->shared_dplls[i];
+ &dev_priv->dpll.shared_dplls[i];
swap(pll->state, shared_dpll[i]);
}
@@ -465,7 +465,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(dev_priv)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
- pll = &dev_priv->shared_dplls[i];
+ pll = &dev_priv->dpll.shared_dplls[i];
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
@@ -3817,7 +3817,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &pch_pll_mgr;
if (!dpll_mgr) {
- dev_priv->num_shared_dpll = 0;
+ dev_priv->dpll.num_shared_dpll = 0;
return;
}
@@ -3825,14 +3825,14 @@ void intel_shared_dpll_init(struct drm_device *dev)
for (i = 0; dpll_info[i].name; i++) {
drm_WARN_ON(dev, i != dpll_info[i].id);
- dev_priv->shared_dplls[i].info = &dpll_info[i];
+ dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
}
- dev_priv->dpll_mgr = dpll_mgr;
- dev_priv->num_shared_dpll = i;
- mutex_init(&dev_priv->dpll_lock);
+ dev_priv->dpll.mgr = dpll_mgr;
+ dev_priv->dpll.num_shared_dpll = i;
+ mutex_init(&dev_priv->dpll.lock);
- BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
+ BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
}
/**
@@ -3859,7 +3859,7 @@ bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return false;
@@ -3882,7 +3882,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
/*
* FIXME: this function is called for every platform having a
@@ -3911,7 +3911,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return;
@@ -3952,8 +3952,8 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->num_shared_dpll; i++)
- readout_dpll_hw_state(i915, &i915->shared_dplls[i]);
+ for (i = 0; i < i915->dpll.num_shared_dpll; i++)
+ readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
}
static void sanitize_dpll_state(struct drm_i915_private *i915,
@@ -3974,8 +3974,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->num_shared_dpll; i++)
- sanitize_dpll_state(i915, &i915->shared_dplls[i]);
+ for (i = 0; i < i915->dpll.num_shared_dpll; i++)
+ sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
}
/**
@@ -3988,8 +3988,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
- if (dev_priv->dpll_mgr) {
- dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
+ if (dev_priv->dpll.mgr) {
+ dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea13fc0b409b..fe4eefc5e7e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1047,17 +1047,19 @@ struct drm_i915_private {
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif
- /* dpll and cdclk state is protected by connection_mutex */
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
- const struct intel_dpll_mgr *dpll_mgr;
-
- /*
- * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
- * Must be global rather than per dpll, because on some platforms
- * plls share registers.
+ /**
+ * dpll and cdclk state is protected by connection_mutex
+ * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
+ * Must be global rather than per dpll, because on some platforms plls
+ * share registers.
*/
- struct mutex dpll_lock;
+ struct {
+ struct mutex lock;
+
+ int num_shared_dpll;
+ struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ const struct intel_dpll_mgr *mgr;
+ } dpll;
struct list_head global_obj_list;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (2 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock Imre Deak
` (17 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Move the per-platform DPLL and DPLL-manager vfunc initializations right
after the corresponding function definitions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 120 +++++++++---------
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c02de061a166..724ab356ea77 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -45,6 +45,21 @@
* commit phase.
*/
+struct intel_dpll_mgr {
+ const struct dpll_info *dpll_info;
+
+ bool (*get_dplls)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+ void (*put_dplls)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*update_active_dpll)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+ void (*dump_hw_state)(struct drm_i915_private *dev_priv,
+ const struct intel_dpll_hw_state *hw_state);
+};
+
static void
intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll_state *shared_dpll)
@@ -509,6 +524,19 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
.get_hw_state = ibx_pch_dpll_get_hw_state,
};
+static const struct dpll_info pch_plls[] = {
+ { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
+ { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr pch_pll_mgr = {
+ .dpll_info = pch_plls,
+ .get_dplls = ibx_get_dpll,
+ .put_dplls = intel_put_dpll,
+ .dump_hw_state = ibx_dump_hw_state,
+};
+
static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -963,6 +991,23 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
};
+static const struct dpll_info hsw_plls[] = {
+ { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
+ { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
+ { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
+ { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
+ { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
+ { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
+ { },
+};
+
+static const struct intel_dpll_mgr hsw_pll_mgr = {
+ .dpll_info = hsw_plls,
+ .get_dplls = hsw_get_dpll,
+ .put_dplls = intel_put_dpll,
+ .dump_hw_state = hsw_dump_hw_state,
+};
+
struct skl_dpll_regs {
i915_reg_t ctl, cfgcr1, cfgcr2;
};
@@ -1518,6 +1563,21 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
.get_hw_state = skl_ddi_dpll0_get_hw_state,
};
+static const struct dpll_info skl_plls[] = {
+ { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
+ { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
+ { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
+ { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr skl_pll_mgr = {
+ .dpll_info = skl_plls,
+ .get_dplls = skl_get_dpll,
+ .put_dplls = intel_put_dpll,
+ .dump_hw_state = skl_dump_hw_state,
+};
+
static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -1964,66 +2024,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
.get_hw_state = bxt_ddi_pll_get_hw_state,
};
-struct intel_dpll_mgr {
- const struct dpll_info *dpll_info;
-
- bool (*get_dplls)(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
- void (*put_dplls)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*update_active_dpll)(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
- void (*dump_hw_state)(struct drm_i915_private *dev_priv,
- const struct intel_dpll_hw_state *hw_state);
-};
-
-static const struct dpll_info pch_plls[] = {
- { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
- { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
- { },
-};
-
-static const struct intel_dpll_mgr pch_pll_mgr = {
- .dpll_info = pch_plls,
- .get_dplls = ibx_get_dpll,
- .put_dplls = intel_put_dpll,
- .dump_hw_state = ibx_dump_hw_state,
-};
-
-static const struct dpll_info hsw_plls[] = {
- { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
- { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
- { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
- { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
- { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
- { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
- { },
-};
-
-static const struct intel_dpll_mgr hsw_pll_mgr = {
- .dpll_info = hsw_plls,
- .get_dplls = hsw_get_dpll,
- .put_dplls = intel_put_dpll,
- .dump_hw_state = hsw_dump_hw_state,
-};
-
-static const struct dpll_info skl_plls[] = {
- { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
- { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
- { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
- { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
- { },
-};
-
-static const struct intel_dpll_mgr skl_pll_mgr = {
- .dpll_info = skl_plls,
- .get_dplls = skl_get_dpll,
- .put_dplls = intel_put_dpll,
- .dump_hw_state = skl_dump_hw_state,
-};
-
static const struct dpll_info bxt_plls[] = {
{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (3 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c Imre Deak
` (16 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Instead of converting DPLL ID to CLK_SEL to identify the DPLL use the
DPLL ID directly for this.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e09ab0d44afa..3375d63d543f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1729,26 +1729,25 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int link_clock = 0;
- u32 val, pll;
+ u32 pll;
- val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
- switch (val & PORT_CLK_SEL_MASK) {
- case PORT_CLK_SEL_LCPLL_810:
+ switch (pipe_config->shared_dpll->info->id) {
+ case DPLL_ID_LCPLL_810:
link_clock = 81000;
break;
- case PORT_CLK_SEL_LCPLL_1350:
+ case DPLL_ID_LCPLL_1350:
link_clock = 135000;
break;
- case PORT_CLK_SEL_LCPLL_2700:
+ case DPLL_ID_LCPLL_2700:
link_clock = 270000;
break;
- case PORT_CLK_SEL_WRPLL1:
+ case DPLL_ID_WRPLL1:
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
break;
- case PORT_CLK_SEL_WRPLL2:
+ case DPLL_ID_WRPLL2:
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
break;
- case PORT_CLK_SEL_SPLL:
+ case DPLL_ID_SPLL:
pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK;
if (pll == SPLL_FREQ_810MHz)
link_clock = 81000;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (4 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it Imre Deak
` (15 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Move all the DPLL params->DPLL frequency conversion functions to
intel_dpll_mgr.c where the corresponding inverse conversions are.
The GEN11+ TBT PLL outputs multiple frequencies and for selecting the
one in use we need to check the DDI CLK mux. As part of the DDI clock
logic this selection is kept in intel_ddi.c.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 442 +-----------------
drivers/gpu/drm/i915/display/intel_ddi.h | 2 -
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 418 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +
5 files changed, 431 insertions(+), 437 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c7214ace963a..c38addd07e42 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1350,15 +1350,13 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
intel_dsc_get_config(encoder, pipe_config);
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
- pipe_config->port_clock =
- cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
+ pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3375d63d543f..5e6f81b140d4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1325,164 +1325,6 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
return ret;
}
-static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
-{
- int refclk;
- int n, p, r;
- u32 wrpll;
-
- wrpll = intel_de_read(dev_priv, reg);
- switch (wrpll & WRPLL_REF_MASK) {
- case WRPLL_REF_SPECIAL_HSW:
- /*
- * muxed-SSC for BDW.
- * non-SSC for non-ULT HSW. Check FUSE_STRAP3
- * for the non-SSC reference frequency.
- */
- if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
- if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- refclk = 24;
- else
- refclk = 135;
- break;
- }
- /* fall through */
- case WRPLL_REF_PCH_SSC:
- /*
- * We could calculate spread here, but our checking
- * code only cares about 5% accuracy, and spread is a max of
- * 0.5% downspread.
- */
- refclk = 135;
- break;
- case WRPLL_REF_LCPLL:
- refclk = 2700;
- break;
- default:
- MISSING_CASE(wrpll);
- return 0;
- }
-
- r = wrpll & WRPLL_DIVIDER_REF_MASK;
- p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
- n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
-
- /* Convert to KHz, p & r have a fixed point portion */
- return (refclk * n * 100) / (p * r);
-}
-
-static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
-{
- u32 p0, p1, p2, dco_freq;
-
- p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
- p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
-
- if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
- p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
- else
- p1 = 1;
-
-
- switch (p0) {
- case DPLL_CFGCR2_PDIV_1:
- p0 = 1;
- break;
- case DPLL_CFGCR2_PDIV_2:
- p0 = 2;
- break;
- case DPLL_CFGCR2_PDIV_3:
- p0 = 3;
- break;
- case DPLL_CFGCR2_PDIV_7:
- p0 = 7;
- break;
- }
-
- switch (p2) {
- case DPLL_CFGCR2_KDIV_5:
- p2 = 5;
- break;
- case DPLL_CFGCR2_KDIV_2:
- p2 = 2;
- break;
- case DPLL_CFGCR2_KDIV_3:
- p2 = 3;
- break;
- case DPLL_CFGCR2_KDIV_1:
- p2 = 1;
- break;
- }
-
- dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
- * 24 * 1000;
-
- dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
- * 24 * 1000) / 0x8000;
-
- if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
- return 0;
-
- return dco_freq / (p0 * p1 * p2 * 5);
-}
-
-int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
- struct intel_dpll_hw_state *pll_state)
-{
- u32 p0, p1, p2, dco_freq, ref_clock;
-
- p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
- p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
-
- if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
- p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
- DPLL_CFGCR1_QDIV_RATIO_SHIFT;
- else
- p1 = 1;
-
-
- switch (p0) {
- case DPLL_CFGCR1_PDIV_2:
- p0 = 2;
- break;
- case DPLL_CFGCR1_PDIV_3:
- p0 = 3;
- break;
- case DPLL_CFGCR1_PDIV_5:
- p0 = 5;
- break;
- case DPLL_CFGCR1_PDIV_7:
- p0 = 7;
- break;
- }
-
- switch (p2) {
- case DPLL_CFGCR1_KDIV_1:
- p2 = 1;
- break;
- case DPLL_CFGCR1_KDIV_2:
- p2 = 2;
- break;
- case DPLL_CFGCR1_KDIV_3:
- p2 = 3;
- break;
- }
-
- ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
-
- dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
- * ref_clock;
-
- dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
- DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
-
- if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
- return 0;
-
- return dco_freq / (p0 * p1 * p2 * 5);
-}
-
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -1505,77 +1347,6 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
}
}
-static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
- const struct intel_dpll_hw_state *pll_state)
-{
- u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
- u64 tmp;
-
- ref_clock = dev_priv->cdclk.hw.ref;
-
- if (INTEL_GEN(dev_priv) >= 12) {
- m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
- m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
- m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
-
- if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
- m2_frac = pll_state->mg_pll_bias &
- DKL_PLL_BIAS_FBDIV_FRAC_MASK;
- m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
- } else {
- m2_frac = 0;
- }
- } else {
- m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
- m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
-
- if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
- m2_frac = pll_state->mg_pll_div0 &
- MG_PLL_DIV0_FBDIV_FRAC_MASK;
- m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
- } else {
- m2_frac = 0;
- }
- }
-
- switch (pll_state->mg_clktop2_hsclkctl &
- MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
- case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
- div1 = 2;
- break;
- case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
- div1 = 3;
- break;
- case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
- div1 = 5;
- break;
- case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
- div1 = 7;
- break;
- default:
- MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
- return 0;
- }
-
- div2 = (pll_state->mg_clktop2_hsclkctl &
- MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
- MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
-
- /* div2 value of 0 is same as 1 means no div */
- if (div2 == 0)
- div2 = 1;
-
- /*
- * Adjust the original formula to delay the division by 2^22 in order to
- * minimize possible rounding errors.
- */
- tmp = (u64)m1 * m2_int * ref_clock +
- (((u64)m1 * m2_frac * ref_clock) >> 22);
- tmp = div_u64(tmp, 5 * div1 * div2);
-
- return tmp;
-}
-
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
{
int dotclock;
@@ -1601,214 +1372,21 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
}
-static void icl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
- enum port port = encoder->port;
- enum phy phy = intel_port_to_phy(dev_priv, port);
- int link_clock;
-
- if (intel_phy_is_combo(dev_priv, phy)) {
- link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
- } else {
- enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
- pipe_config->shared_dpll);
-
- if (pll_id == DPLL_ID_ICL_TBTPLL)
- link_clock = icl_calc_tbt_pll_link(dev_priv, port);
- else
- link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
- }
-
- pipe_config->port_clock = link_clock;
-
- ddi_dotclock_get(pipe_config);
-}
-
-static void cnl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
- int link_clock;
-
- if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
- link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
- } else {
- link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
-
- switch (link_clock) {
- case DPLL_CFGCR0_LINK_RATE_810:
- link_clock = 81000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1080:
- link_clock = 108000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1350:
- link_clock = 135000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1620:
- link_clock = 162000;
- break;
- case DPLL_CFGCR0_LINK_RATE_2160:
- link_clock = 216000;
- break;
- case DPLL_CFGCR0_LINK_RATE_2700:
- link_clock = 270000;
- break;
- case DPLL_CFGCR0_LINK_RATE_3240:
- link_clock = 324000;
- break;
- case DPLL_CFGCR0_LINK_RATE_4050:
- link_clock = 405000;
- break;
- default:
- drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
- break;
- }
- link_clock *= 2;
- }
-
- pipe_config->port_clock = link_clock;
-
- ddi_dotclock_get(pipe_config);
-}
-
-static void skl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
- int link_clock;
-
- /*
- * ctrl1 register is already shifted for each pll, just use 0 to get
- * the internal shift for each field
- */
- if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
- link_clock = skl_calc_wrpll_link(pll_state);
- } else {
- link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
- link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
-
- switch (link_clock) {
- case DPLL_CTRL1_LINK_RATE_810:
- link_clock = 81000;
- break;
- case DPLL_CTRL1_LINK_RATE_1080:
- link_clock = 108000;
- break;
- case DPLL_CTRL1_LINK_RATE_1350:
- link_clock = 135000;
- break;
- case DPLL_CTRL1_LINK_RATE_1620:
- link_clock = 162000;
- break;
- case DPLL_CTRL1_LINK_RATE_2160:
- link_clock = 216000;
- break;
- case DPLL_CTRL1_LINK_RATE_2700:
- link_clock = 270000;
- break;
- default:
- drm_WARN(encoder->base.dev, 1,
- "Unsupported link rate\n");
- break;
- }
- link_clock *= 2;
- }
-
- pipe_config->port_clock = link_clock;
-
- ddi_dotclock_get(pipe_config);
-}
-
-static void hsw_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- int link_clock = 0;
- u32 pll;
-
- switch (pipe_config->shared_dpll->info->id) {
- case DPLL_ID_LCPLL_810:
- link_clock = 81000;
- break;
- case DPLL_ID_LCPLL_1350:
- link_clock = 135000;
- break;
- case DPLL_ID_LCPLL_2700:
- link_clock = 270000;
- break;
- case DPLL_ID_WRPLL1:
- link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
- break;
- case DPLL_ID_WRPLL2:
- link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
- break;
- case DPLL_ID_SPLL:
- pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK;
- if (pll == SPLL_FREQ_810MHz)
- link_clock = 81000;
- else if (pll == SPLL_FREQ_1350MHz)
- link_clock = 135000;
- else if (pll == SPLL_FREQ_2700MHz)
- link_clock = 270000;
- else {
- drm_WARN(&dev_priv->drm, 1, "bad spll freq\n");
- return;
- }
- break;
- default:
- drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n");
- return;
- }
-
- pipe_config->port_clock = link_clock * 2;
-
- ddi_dotclock_get(pipe_config);
-}
-
-static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
-{
- struct dpll clock;
-
- clock.m1 = 2;
- clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
- if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
- clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
- clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
- clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
- clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
-
- return chv_calc_dpll_params(100000, &clock);
-}
-
-static void bxt_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- pipe_config->port_clock =
- bxt_calc_pll_link(&pipe_config->dpll_hw_state);
-
- ddi_dotclock_get(pipe_config);
-}
-
static void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (INTEL_GEN(dev_priv) >= 11)
- icl_ddi_clock_get(encoder, pipe_config);
- else if (IS_CANNONLAKE(dev_priv))
- cnl_ddi_clock_get(encoder, pipe_config);
- else if (IS_GEN9_LP(dev_priv))
- bxt_ddi_clock_get(encoder, pipe_config);
- else if (IS_GEN9_BC(dev_priv))
- skl_ddi_clock_get(encoder, pipe_config);
- else if (INTEL_GEN(dev_priv) <= 8)
- hsw_ddi_clock_get(encoder, pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
+ DPLL_ID_ICL_TBTPLL)
+ pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
+ encoder->port);
+ else
+ pipe_config->port_clock = intel_dpll_get_freq(encoder,
+ pipe_config);
+
+ ddi_dotclock_get(pipe_config);
}
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 167c6579d972..82184750efae 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -47,7 +47,5 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
bool enable);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
-int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
- struct intel_dpll_hw_state *state);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 724ab356ea77..5057f7636534 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -877,6 +877,53 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
return pll;
}
+static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
+ i915_reg_t reg)
+{
+ int refclk;
+ int n, p, r;
+ u32 wrpll;
+
+ wrpll = intel_de_read(dev_priv, reg);
+ switch (wrpll & WRPLL_REF_MASK) {
+ case WRPLL_REF_SPECIAL_HSW:
+ /*
+ * muxed-SSC for BDW.
+ * non-SSC for non-ULT HSW. Check FUSE_STRAP3
+ * for the non-SSC reference frequency.
+ */
+ if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
+ if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
+ refclk = 24;
+ else
+ refclk = 135;
+ break;
+ }
+ /* fall through */
+ case WRPLL_REF_PCH_SSC:
+ /*
+ * We could calculate spread here, but our checking
+ * code only cares about 5% accuracy, and spread is a max of
+ * 0.5% downspread.
+ */
+ refclk = 135;
+ break;
+ case WRPLL_REF_LCPLL:
+ refclk = 2700;
+ break;
+ default:
+ MISSING_CASE(wrpll);
+ return 0;
+ }
+
+ r = wrpll & WRPLL_DIVIDER_REF_MASK;
+ p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
+ n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
+
+ /* Convert to KHz, p & r have a fixed point portion */
+ return (refclk * n * 100) / (p * r);
+}
+
static struct intel_shared_dpll *
hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
{
@@ -949,6 +996,50 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
return true;
}
+static int hsw_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ int link_clock = 0;
+ u32 pll;
+
+ switch (pipe_config->shared_dpll->info->id) {
+ case DPLL_ID_LCPLL_810:
+ link_clock = 81000;
+ break;
+ case DPLL_ID_LCPLL_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_ID_LCPLL_2700:
+ link_clock = 270000;
+ break;
+ case DPLL_ID_WRPLL1:
+ link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
+ break;
+ case DPLL_ID_WRPLL2:
+ link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
+ break;
+ case DPLL_ID_SPLL:
+ pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK;
+ if (pll == SPLL_FREQ_810MHz)
+ link_clock = 81000;
+ else if (pll == SPLL_FREQ_1350MHz)
+ link_clock = 135000;
+ else if (pll == SPLL_FREQ_2700MHz)
+ link_clock = 270000;
+ else {
+ drm_WARN(&dev_priv->drm, 1, "bad spll freq\n");
+ break;
+ }
+ break;
+ default:
+ drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n");
+ break;
+ }
+
+ return link_clock * 2;
+}
+
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1452,6 +1543,61 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
+static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
+{
+ u32 p0, p1, p2, dco_freq;
+
+ p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
+ p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
+
+ if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
+ p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
+ else
+ p1 = 1;
+
+
+ switch (p0) {
+ case DPLL_CFGCR2_PDIV_1:
+ p0 = 1;
+ break;
+ case DPLL_CFGCR2_PDIV_2:
+ p0 = 2;
+ break;
+ case DPLL_CFGCR2_PDIV_3:
+ p0 = 3;
+ break;
+ case DPLL_CFGCR2_PDIV_7:
+ p0 = 7;
+ break;
+ }
+
+ switch (p2) {
+ case DPLL_CFGCR2_KDIV_5:
+ p2 = 5;
+ break;
+ case DPLL_CFGCR2_KDIV_2:
+ p2 = 2;
+ break;
+ case DPLL_CFGCR2_KDIV_3:
+ p2 = 3;
+ break;
+ case DPLL_CFGCR2_KDIV_1:
+ p2 = 1;
+ break;
+ }
+
+ dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
+ * 24 * 1000;
+
+ dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
+ * 24 * 1000) / 0x8000;
+
+ if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
+ return 0;
+
+ return dco_freq / (p0 * p1 * p2 * 5);
+}
+
static bool
skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
@@ -1541,6 +1687,52 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
return true;
}
+static int skl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
+ int link_clock;
+
+ /*
+ * ctrl1 register is already shifted for each pll, just use 0 to get
+ * the internal shift for each field
+ */
+ if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
+ link_clock = skl_calc_wrpll_link(pll_state);
+ } else {
+ link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
+ link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
+
+ switch (link_clock) {
+ case DPLL_CTRL1_LINK_RATE_810:
+ link_clock = 81000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_2700:
+ link_clock = 270000;
+ break;
+ default:
+ drm_WARN(encoder->base.dev, 1,
+ "Unsupported link rate\n");
+ break;
+ }
+ link_clock *= 2;
+ }
+
+ return link_clock;
+}
+
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1966,6 +2158,24 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
}
+static int bxt_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dpll_hw_state *pll_state =
+ &crtc_state->shared_dpll->state.hw_state;
+ struct dpll clock;
+
+ clock.m1 = 2;
+ clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
+ if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
+ clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
+ clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
+ clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
+ clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
+
+ return chv_calc_dpll_params(100000, &clock);
+}
+
static bool bxt_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -2366,6 +2576,62 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
+static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
+ struct intel_dpll_hw_state *pll_state)
+{
+ u32 p0, p1, p2, dco_freq, ref_clock;
+
+ p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+ p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+
+ if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+ p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+ DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+ else
+ p1 = 1;
+
+
+ switch (p0) {
+ case DPLL_CFGCR1_PDIV_2:
+ p0 = 2;
+ break;
+ case DPLL_CFGCR1_PDIV_3:
+ p0 = 3;
+ break;
+ case DPLL_CFGCR1_PDIV_5:
+ p0 = 5;
+ break;
+ case DPLL_CFGCR1_PDIV_7:
+ p0 = 7;
+ break;
+ }
+
+ switch (p2) {
+ case DPLL_CFGCR1_KDIV_1:
+ p2 = 1;
+ break;
+ case DPLL_CFGCR1_KDIV_2:
+ p2 = 2;
+ break;
+ case DPLL_CFGCR1_KDIV_3:
+ p2 = 3;
+ break;
+ }
+
+ ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
+
+ dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
+ ref_clock;
+
+ dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
+
+ if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
+ return 0;
+
+ return dco_freq / (p0 * p1 * p2 * 5);
+}
+
static bool
cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
@@ -2460,6 +2726,53 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
return true;
}
+static int cnl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
+ int link_clock;
+
+ if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
+ link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
+ } else {
+ link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
+
+ switch (link_clock) {
+ case DPLL_CFGCR0_LINK_RATE_810:
+ link_clock = 81000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_2700:
+ link_clock = 270000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_3240:
+ link_clock = 324000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_4050:
+ link_clock = 405000;
+ break;
+ default:
+ drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
+ break;
+ }
+ link_clock *= 2;
+ }
+
+ return link_clock;
+}
+
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -2972,6 +3285,90 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return true;
}
+static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
+ const struct intel_dpll_hw_state *pll_state)
+{
+ u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
+ u64 tmp;
+
+ ref_clock = dev_priv->cdclk.hw.ref;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
+ m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
+ m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
+
+ if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
+ m2_frac = pll_state->mg_pll_bias &
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK;
+ m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
+ } else {
+ m2_frac = 0;
+ }
+ } else {
+ m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
+ m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
+
+ if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
+ m2_frac = pll_state->mg_pll_div0 &
+ MG_PLL_DIV0_FBDIV_FRAC_MASK;
+ m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
+ } else {
+ m2_frac = 0;
+ }
+ }
+
+ switch (pll_state->mg_clktop2_hsclkctl &
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
+ div1 = 2;
+ break;
+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
+ div1 = 3;
+ break;
+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
+ div1 = 5;
+ break;
+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
+ div1 = 7;
+ break;
+ default:
+ MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
+ return 0;
+ }
+
+ div2 = (pll_state->mg_clktop2_hsclkctl &
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
+
+ /* div2 value of 0 is same as 1 means no div */
+ if (div2 == 0)
+ div2 = 1;
+
+ /*
+ * Adjust the original formula to delay the division by 2^22 in order to
+ * minimize possible rounding errors.
+ */
+ tmp = (u64)m1 * m2_int * ref_clock +
+ (((u64)m1 * m2_frac * ref_clock) >> 22);
+ tmp = div_u64(tmp, 5 * div1 * div2);
+
+ return tmp;
+}
+
+static int icl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (intel_phy_is_combo(dev_priv, phy))
+ return cnl_calc_wrpll_link(dev_priv, pll_state);
+ else
+ return icl_calc_mg_pll_link(dev_priv, pll_state);
+}
+
/**
* icl_set_active_port_dpll - select the active port DPLL for a given CRTC
* @crtc_state: state for the CRTC to select the DPLL for
@@ -3919,6 +4316,27 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
dpll_mgr->update_active_dpll(state, crtc, encoder);
}
+int intel_dpll_get_freq(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ if (INTEL_GEN(i915) >= 11)
+ return icl_ddi_clock_get(encoder, crtc_state);
+ else if (IS_CANNONLAKE(i915))
+ return cnl_ddi_clock_get(encoder, crtc_state);
+ else if (IS_GEN9_LP(i915))
+ return bxt_ddi_clock_get(encoder, crtc_state);
+ else if (IS_GEN9_BC(i915))
+ return skl_ddi_clock_get(encoder, crtc_state);
+ else if (INTEL_GEN(i915) <= 8)
+ hsw_ddi_clock_get(encoder, crtc_state);
+
+ drm_WARN_ON(&i915->drm, 1);
+ return 0;
+}
+
+
static void readout_dpll_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index fe27a5dfc51e..fadc240eccf6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -372,6 +372,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
+int intel_dpll_get_freq(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (5 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL Imre Deak
` (14 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
For clarity keep the SKL DPLL ref clock in a variable instead of
open-coding it. Store the value in kHZ units as done on other platforms.
This allows us in a later patch to keep track of the DPLL ref clock in a
more unified way across all platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++--------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5057f7636534..a4d27dfaec9a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1369,6 +1369,7 @@ struct skl_wrpll_params {
static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
u64 afe_clock,
+ int ref_clock,
u64 central_freq,
u32 p0, u32 p1, u32 p2)
{
@@ -1428,14 +1429,15 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
* Intermediate values are in Hz.
* Divide by MHz to match bsepc
*/
- params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
+ params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
params->dco_fraction =
- div_u64((div_u64(dco_freq, 24) -
+ div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
params->dco_integer * MHz(1)) * 0x8000, MHz(1));
}
static bool
skl_ddi_calculate_wrpll(int clock /* in Hz */,
+ int ref_clock,
struct skl_wrpll_params *wrpll_params)
{
u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
@@ -1501,8 +1503,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
*/
p0 = p1 = p2 = 0;
skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
- skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
- p0, p1, p2);
+ skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
+ ctx.central_freq, p0, p1, p2);
return true;
}
@@ -1520,7 +1522,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
+ if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
&wrpll_params))
return false;
@@ -1545,6 +1547,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
{
+ int ref_clock = 24000;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1586,11 +1589,11 @@ static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
break;
}
- dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
- * 24 * 1000;
+ dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
+ ref_clock;
- dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
- * 24 * 1000) / 0x8000;
+ dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
+ ref_clock / 0x8000;
if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
return 0;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (6 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation Imre Deak
` (13 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
The types of PLLs used for HDMI/DP on HSW are WRPLL/LCPLL accordingly,
so use these names to align better with the rest of WRPLL/LCPLL function
names elsewhere.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index a4d27dfaec9a..1891aa268fb8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -849,8 +849,8 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
}
static struct intel_shared_dpll *
-hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -925,7 +925,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
}
static struct intel_shared_dpll *
-hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
+hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_shared_dpll *pll;
@@ -968,9 +968,9 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
sizeof(crtc_state->dpll_hw_state));
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
- pll = hsw_ddi_hdmi_get_dpll(state, crtc);
+ pll = hsw_ddi_wrpll_get_dpll(state, crtc);
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
- pll = hsw_ddi_dp_get_dpll(crtc_state);
+ pll = hsw_ddi_lcpll_get_dpll(crtc_state);
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
if (WARN_ON(crtc_state->port_clock / 2 != 135000))
return false;
--
2.23.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (7 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation Imre Deak
` (12 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
For consistency with the WRPLL/LCPLL parameter calculation functions,
split out the SPLL specific logic to its own function.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 36 +++++++++++--------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1891aa268fb8..87661f797a02 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -956,6 +956,23 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
+static struct intel_shared_dpll *
+hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (WARN_ON(crtc_state->port_clock / 2 != 135000))
+ return NULL;
+
+ crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
+ SPLL_REF_MUXED_SSC;
+
+ return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_SPLL));
+}
+
static bool hsw_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -967,23 +984,14 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
- } else if (intel_crtc_has_dp_encoder(crtc_state)) {
+ else if (intel_crtc_has_dp_encoder(crtc_state))
pll = hsw_ddi_lcpll_get_dpll(crtc_state);
- } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
- if (WARN_ON(crtc_state->port_clock / 2 != 135000))
- return false;
-
- crtc_state->dpll_hw_state.spll =
- SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
-
- pll = intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_SPLL));
- } else {
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
+ pll = hsw_ddi_spll_get_dpll(state, crtc);
+ else
return false;
- }
if (!pll)
return false;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (8 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
` (11 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Split out the PLL parameter->frequency conversion logic for each type of
PLL for symmetry with their corresponding inverse conversion functions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 91 ++++++++++++-------
1 file changed, 56 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 87661f797a02..ebd55fdaf4cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -877,9 +877,11 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
return pll;
}
-static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
+static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+ const struct intel_shared_dpll *pll)
{
+ i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
+ WRPLL_CTL(0) : WRPLL_CTL(1);
int refclk;
int n, p, r;
u32 wrpll;
@@ -921,7 +923,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
/* Convert to KHz, p & r have a fixed point portion */
- return (refclk * n * 100) / (p * r);
+ return (refclk * n * 100) / (p * r) * 2;
}
static struct intel_shared_dpll *
@@ -956,6 +958,29 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
+static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ int link_clock = 0;
+
+ switch (pll->info->id) {
+ case DPLL_ID_LCPLL_810:
+ link_clock = 81000;
+ break;
+ case DPLL_ID_LCPLL_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_ID_LCPLL_2700:
+ link_clock = 270000;
+ break;
+ default:
+ drm_WARN(&i915->drm, 1, "bad port clock sel\n");
+ break;
+ }
+
+ return link_clock * 2;
+}
+
static struct intel_shared_dpll *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -973,6 +998,29 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
+static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ int link_clock = 0;
+
+ switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
+ case SPLL_FREQ_810MHz:
+ link_clock = 81000;
+ break;
+ case SPLL_FREQ_1350MHz:
+ link_clock = 135000;
+ break;
+ case SPLL_FREQ_2700MHz:
+ link_clock = 270000;
+ break;
+ default:
+ drm_WARN(&i915->drm, 1, "bad spll freq\n");
+ break;
+ }
+
+ return link_clock * 2;
+}
+
static bool hsw_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -1008,44 +1056,17 @@ static int hsw_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- int link_clock = 0;
- u32 pll;
+ struct intel_shared_dpll *pll = pipe_config->shared_dpll;
- switch (pipe_config->shared_dpll->info->id) {
- case DPLL_ID_LCPLL_810:
- link_clock = 81000;
- break;
- case DPLL_ID_LCPLL_1350:
- link_clock = 135000;
- break;
- case DPLL_ID_LCPLL_2700:
- link_clock = 270000;
- break;
+ switch (pll->info->id) {
case DPLL_ID_WRPLL1:
- link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
- break;
case DPLL_ID_WRPLL2:
- link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
- break;
+ return hsw_ddi_wrpll_get_freq(dev_priv, pll);
case DPLL_ID_SPLL:
- pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK;
- if (pll == SPLL_FREQ_810MHz)
- link_clock = 81000;
- else if (pll == SPLL_FREQ_1350MHz)
- link_clock = 135000;
- else if (pll == SPLL_FREQ_2700MHz)
- link_clock = 270000;
- else {
- drm_WARN(&dev_priv->drm, 1, "bad spll freq\n");
- break;
- }
- break;
+ return hsw_ddi_spll_get_freq(dev_priv, pll);
default:
- drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n");
- break;
+ return hsw_ddi_lcpll_get_freq(dev_priv, pll);
}
-
- return link_clock * 2;
}
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (9 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-27 17:57 ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
` (10 subsequent siblings)
21 siblings, 1 reply; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Split out the PLL parameter->frequency conversion logic for each type of
PLL for symmetry with their corresponding inverse conversion functions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 269 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
4 files changed, 140 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c38addd07e42..17cee6f80d8b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
intel_dsc_get_config(encoder, pipe_config);
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
- pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
+ pipe_config->port_clock = intel_dpll_get_freq(i915,
+ pipe_config->shared_dpll);
pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5e6f81b140d4..284219da7df8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
encoder->port);
else
- pipe_config->port_clock = intel_dpll_get_freq(encoder,
- pipe_config);
+ pipe_config->port_clock =
+ intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
ddi_dotclock_get(pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ebd55fdaf4cd..b87b4ff5de52 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
return true;
}
-static int hsw_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_shared_dpll *pll = pipe_config->shared_dpll;
-
- switch (pll->info->id) {
- case DPLL_ID_WRPLL1:
- case DPLL_ID_WRPLL2:
- return hsw_ddi_wrpll_get_freq(dev_priv, pll);
- case DPLL_ID_SPLL:
- return hsw_ddi_spll_get_freq(dev_priv, pll);
- default:
- return hsw_ddi_lcpll_get_freq(dev_priv, pll);
- }
-}
-
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
+ .get_freq = hsw_ddi_wrpll_get_freq,
};
static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
.disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
+ .get_freq = hsw_ddi_spll_get_freq,
};
static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
@@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
.disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
+ .get_freq = hsw_ddi_lcpll_get_freq,
};
static const struct dpll_info hsw_plls[] = {
@@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
-static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
+static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
int ref_clock = 24000;
u32 p0, p1, p2, dco_freq;
@@ -1670,6 +1658,40 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return true;
}
+static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ int link_clock = 0;
+
+ switch ((pll->state.hw_state.ctrl1 &
+ DPLL_CTRL1_LINK_RATE_MASK(0)) >>
+ DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
+ case DPLL_CTRL1_LINK_RATE_810:
+ link_clock = 81000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
+ case DPLL_CTRL1_LINK_RATE_2700:
+ link_clock = 270000;
+ break;
+ default:
+ drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+ break;
+ }
+
+ return link_clock * 2;
+}
+
static bool skl_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -1719,50 +1741,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
return true;
}
-static int skl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
+static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
{
- struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
- int link_clock;
-
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
- if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
- link_clock = skl_calc_wrpll_link(pll_state);
- } else {
- link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
- link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
-
- switch (link_clock) {
- case DPLL_CTRL1_LINK_RATE_810:
- link_clock = 81000;
- break;
- case DPLL_CTRL1_LINK_RATE_1080:
- link_clock = 108000;
- break;
- case DPLL_CTRL1_LINK_RATE_1350:
- link_clock = 135000;
- break;
- case DPLL_CTRL1_LINK_RATE_1620:
- link_clock = 162000;
- break;
- case DPLL_CTRL1_LINK_RATE_2160:
- link_clock = 216000;
- break;
- case DPLL_CTRL1_LINK_RATE_2700:
- link_clock = 270000;
- break;
- default:
- drm_WARN(encoder->base.dev, 1,
- "Unsupported link rate\n");
- break;
- }
- link_clock *= 2;
- }
-
- return link_clock;
+ if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
+ return skl_ddi_wrpll_get_freq(i915, pll);
+ else
+ return skl_ddi_lcpll_get_freq(i915, pll);
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1779,12 +1768,14 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
+ .get_freq = skl_ddi_pll_get_freq,
};
static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
.disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
+ .get_freq = skl_ddi_pll_get_freq,
};
static const struct dpll_info skl_plls[] = {
@@ -2190,11 +2181,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
}
-static int bxt_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
+static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
{
- struct intel_dpll_hw_state *pll_state =
- &crtc_state->shared_dpll->state.hw_state;
+ const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
struct dpll clock;
clock.m1 = 2;
@@ -2264,6 +2254,7 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
+ .get_freq = bxt_ddi_pll_get_freq,
};
static const struct dpll_info bxt_plls[] = {
@@ -2608,9 +2599,10 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
-static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
- struct intel_dpll_hw_state *pll_state)
+static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+ const struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
u32 p0, p1, p2, dco_freq, ref_clock;
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
@@ -2709,6 +2701,44 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return true;
}
+static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ int link_clock = 0;
+
+ switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
+ case DPLL_CFGCR0_LINK_RATE_810:
+ link_clock = 81000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1350:
+ link_clock = 135000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_2700:
+ link_clock = 270000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_3240:
+ link_clock = 324000;
+ break;
+ case DPLL_CFGCR0_LINK_RATE_4050:
+ link_clock = 405000;
+ break;
+ default:
+ drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+ break;
+ }
+
+ return link_clock * 2;
+}
+
static bool cnl_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -2758,51 +2788,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
return true;
}
-static int cnl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
- int link_clock;
-
- if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
- link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
- } else {
- link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
-
- switch (link_clock) {
- case DPLL_CFGCR0_LINK_RATE_810:
- link_clock = 81000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1080:
- link_clock = 108000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1350:
- link_clock = 135000;
- break;
- case DPLL_CFGCR0_LINK_RATE_1620:
- link_clock = 162000;
- break;
- case DPLL_CFGCR0_LINK_RATE_2160:
- link_clock = 216000;
- break;
- case DPLL_CFGCR0_LINK_RATE_2700:
- link_clock = 270000;
- break;
- case DPLL_CFGCR0_LINK_RATE_3240:
- link_clock = 324000;
- break;
- case DPLL_CFGCR0_LINK_RATE_4050:
- link_clock = 405000;
- break;
- default:
- drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
- break;
- }
- link_clock *= 2;
- }
-
- return link_clock;
+ if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
+ return cnl_ddi_wrpll_get_freq(i915, pll);
+ else
+ return cnl_ddi_lcpll_get_freq(i915, pll);
}
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -2818,6 +2810,7 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
.enable = cnl_ddi_pll_enable,
.disable = cnl_ddi_pll_disable,
.get_hw_state = cnl_ddi_pll_get_hw_state,
+ .get_freq = cnl_ddi_pll_get_freq,
};
static const struct dpll_info cnl_plls[] = {
@@ -2979,6 +2972,18 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return true;
}
+static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ /*
+ * The PLL outputs multiple frequencies at the same time, selection is
+ * made at DDI clock mux level.
+ */
+ drm_WARN_ON(&i915->drm, 1);
+
+ return 0;
+}
+
static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder,
struct intel_dpll_hw_state *pll_state)
@@ -3317,9 +3322,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return true;
}
-static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
- const struct intel_dpll_hw_state *pll_state)
+static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
+ const struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3388,19 +3394,6 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
return tmp;
}
-static int icl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
- if (intel_phy_is_combo(dev_priv, phy))
- return cnl_calc_wrpll_link(dev_priv, pll_state);
- else
- return icl_calc_mg_pll_link(dev_priv, pll_state);
-}
-
/**
* icl_set_active_port_dpll - select the active port DPLL for a given CRTC
* @crtc_state: state for the CRTC to select the DPLL for
@@ -3485,6 +3478,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return true;
}
+static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ return cnl_ddi_wrpll_get_freq(i915, pll);
+}
+
static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -4141,18 +4140,21 @@ static const struct intel_shared_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
+ .get_freq = icl_ddi_combo_pll_get_freq,
};
static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
.disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
+ .get_freq = icl_ddi_tbt_pll_get_freq,
};
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
+ .get_freq = icl_ddi_mg_pll_get_freq,
};
static const struct dpll_info icl_plls[] = {
@@ -4192,6 +4194,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
+ .get_freq = icl_ddi_mg_pll_get_freq,
};
static const struct dpll_info tgl_plls[] = {
@@ -4348,27 +4351,15 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
dpll_mgr->update_active_dpll(state, crtc, encoder);
}
-int intel_dpll_get_freq(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
+int intel_dpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-
- if (INTEL_GEN(i915) >= 11)
- return icl_ddi_clock_get(encoder, crtc_state);
- else if (IS_CANNONLAKE(i915))
- return cnl_ddi_clock_get(encoder, crtc_state);
- else if (IS_GEN9_LP(i915))
- return bxt_ddi_clock_get(encoder, crtc_state);
- else if (IS_GEN9_BC(i915))
- return skl_ddi_clock_get(encoder, crtc_state);
- else if (INTEL_GEN(i915) <= 8)
- hsw_ddi_clock_get(encoder, crtc_state);
+ if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
+ return 0;
- drm_WARN_ON(&i915->drm, 1);
- return 0;
+ return pll->info->funcs->get_freq(i915, pll);
}
-
static void readout_dpll_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index fadc240eccf6..c155935874d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -278,6 +278,9 @@ struct intel_shared_dpll_funcs {
bool (*get_hw_state)(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state);
+
+ int (*get_freq)(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll);
};
/**
@@ -372,8 +375,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state);
+int intel_dpll_get_freq(struct drm_i915_private *,
+ const struct intel_shared_dpll *);
void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
@@ -384,7 +387,6 @@ void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state);
-int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (10 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-27 17:58 ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
` (9 subsequent siblings)
21 siblings, 1 reply; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
Instead of reading out the WRPLL/SPLL control values from HW, we can use
the DPLL state that was already read out, or swapped-to.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b87b4ff5de52..7e6da58a47c9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
const struct intel_shared_dpll *pll)
{
- i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
- WRPLL_CTL(0) : WRPLL_CTL(1);
int refclk;
int n, p, r;
- u32 wrpll;
+ u32 wrpll = pll->state.hw_state.wrpll;
- wrpll = intel_de_read(dev_priv, reg);
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/*
@@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
{
int link_clock = 0;
- switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
+ switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
case SPLL_FREQ_810MHz:
link_clock = 81000;
break;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (11 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
@ 2020-02-26 20:34 ` Imre Deak
2020-02-27 18:13 ` Ville Syrjälä
2020-02-28 15:33 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-02-27 4:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking Patchwork
` (8 subsequent siblings)
21 siblings, 2 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-26 20:34 UTC (permalink / raw)
To: intel-gfx
All platforms using the shared DPLL framework use 3 reference clocks for
their DPLLs: SSC, non-SSC and DSI. For a more unified way across
platforms store the frequency of these ref clocks as part of the DPLL
global state. This also allows us to keep the HW access reading out the
ref clock value separate from the DPLL frequency calculation that
depends on the ref clock.
For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
has its own logic for calculating DPLL parameters instead of the shared
DPLL framework.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 5 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 132 +++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 5 +
3 files changed, 95 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d2461d7946bf..6675b7e34f0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -920,6 +920,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
int i;
drm_modeset_lock_all(dev);
+
+ seq_printf(m, "PLL refclks: non-SSC: %d kHZ, SSC: %d kHZ\n",
+ dev_priv->dpll.ref_clks.nssc,
+ dev_priv->dpll.ref_clks.ssc);
+
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7e6da58a47c9..44db46782770 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -56,6 +56,7 @@ struct intel_dpll_mgr {
void (*update_active_dpll)(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
+ void (*update_ref_clks)(struct drm_i915_private *i915);
void (*dump_hw_state)(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state);
};
@@ -886,16 +887,9 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
- /*
- * muxed-SSC for BDW.
- * non-SSC for non-ULT HSW. Check FUSE_STRAP3
- * for the non-SSC reference frequency.
- */
+ /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
- if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- refclk = 24;
- else
- refclk = 135;
+ refclk = dev_priv->dpll.ref_clks.nssc;
break;
}
/* fall through */
@@ -905,10 +899,10 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = 135;
+ refclk = dev_priv->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
- refclk = 2700;
+ refclk = 2700000;
break;
default:
MISSING_CASE(wrpll);
@@ -920,7 +914,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
/* Convert to KHz, p & r have a fixed point portion */
- return (refclk * n * 100) / (p * r) * 2;
+ return (refclk * n / 10) / (p * r) * 2;
}
static struct intel_shared_dpll *
@@ -1049,6 +1043,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
return true;
}
+static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ i915->dpll.ref_clks.ssc = 135000;
+ /* Non-SSC is only used on non-ULT HSW. */
+ if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
+ i915->dpll.ref_clks.nssc = 24000;
+ else
+ i915->dpll.ref_clks.nssc = 135000;
+}
+
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1108,6 +1112,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
.dpll_info = hsw_plls,
.get_dplls = hsw_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = hsw_update_dpll_ref_clks,
.dump_hw_state = hsw_dump_hw_state,
};
@@ -1523,6 +1528,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
u32 ctrl1, cfgcr1, cfgcr2;
struct skl_wrpll_params wrpll_params = { 0, };
@@ -1534,7 +1540,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
+ if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
+ i915->dpll.ref_clks.nssc,
&wrpll_params))
return false;
@@ -1561,7 +1568,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll)
{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
- int ref_clock = 24000;
+ int ref_clock = i915->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1751,6 +1758,12 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
return skl_ddi_lcpll_get_freq(i915, pll);
}
+static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC ref */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1787,6 +1800,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.dpll_info = skl_plls,
.get_dplls = skl_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = skl_update_dpll_ref_clks,
.dump_hw_state = skl_dump_hw_state,
};
@@ -2192,7 +2206,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
- return chv_calc_dpll_params(100000, &clock);
+ return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
}
static bool bxt_get_dpll(struct intel_atomic_state *state,
@@ -2228,6 +2242,13 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
return true;
}
+static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ i915->dpll.ref_clks.ssc = 100000;
+ i915->dpll.ref_clks.nssc = 100000;
+ /* DSI non-SSC ref 19.2MHz */
+}
+
static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -2265,6 +2286,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
.dpll_info = bxt_plls,
.get_dplls = bxt_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = bxt_update_dpll_ref_clks,
.dump_hw_state = bxt_dump_hw_state,
};
@@ -2508,27 +2530,13 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
params->dco_fraction = dco & 0x7fff;
}
-int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
-{
- int ref_clock = dev_priv->cdclk.hw.ref;
-
- /*
- * For ICL+, the spec states: if reference frequency is 38.4,
- * use 19.2 because the DPLL automatically divides that by 2.
- */
- if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
- ref_clock = 19200;
-
- return ref_clock;
-}
-
static bool
cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *wrpll_params)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 afe_clock = crtc_state->port_clock * 5;
- u32 ref_clock;
+ int ref_clock = dev_priv->dpll.ref_clks.nssc;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
@@ -2560,9 +2568,6 @@ cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
return false;
cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
-
- ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
-
cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
pdiv, qdiv, kdiv);
@@ -2596,11 +2601,12 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
-static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
- const struct intel_shared_dpll *pll)
+static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+ const struct intel_shared_dpll *pll,
+ int ref_clock)
{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
- u32 p0, p1, p2, dco_freq, ref_clock;
+ u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
@@ -2639,8 +2645,6 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
break;
}
- ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
-
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
ref_clock;
@@ -2653,6 +2657,12 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
return dco_freq / (p0 * p1 * p2 * 5);
}
+static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
+}
+
static bool
cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
@@ -2794,6 +2804,12 @@ static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
return cnl_ddi_lcpll_get_freq(i915, pll);
}
+static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC reference */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -2821,6 +2837,7 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
.dpll_info = cnl_plls,
.get_dplls = cnl_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = cnl_update_dpll_ref_clks,
.dump_hw_state = cnl_dump_hw_state,
};
@@ -2916,7 +2933,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
- dev_priv->cdclk.hw.ref == 24000 ?
+ dev_priv->dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
@@ -2939,9 +2956,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (INTEL_GEN(dev_priv) >= 12) {
- switch (dev_priv->cdclk.hw.ref) {
+ switch (dev_priv->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->cdclk.hw.ref);
+ MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
/* fall-through */
case 19200:
case 38400:
@@ -2952,9 +2969,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
break;
}
} else {
- switch (dev_priv->cdclk.hw.ref) {
+ switch (dev_priv->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->cdclk.hw.ref);
+ MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
/* fall-through */
case 19200:
case 38400:
@@ -3118,7 +3135,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int refclk_khz = dev_priv->cdclk.hw.ref;
+ int refclk_khz = dev_priv->dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3326,7 +3343,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = dev_priv->cdclk.hw.ref;
+ ref_clock = dev_priv->dpll.ref_clks.nssc;
if (INTEL_GEN(dev_priv) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
@@ -3478,7 +3495,16 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll)
{
- return cnl_ddi_wrpll_get_freq(i915, pll);
+ int ref_clock = i915->dpll.ref_clks.nssc;
+
+ /*
+ * For ICL+, the spec states: if reference frequency is 38.4,
+ * use 19.2 because the DPLL automatically divides that by 2.
+ */
+ if (ref_clock == 38400)
+ ref_clock = 19200;
+
+ return __cnl_ddi_wrpll_get_freq(i915, pll, ref_clock);
}
static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
@@ -3629,7 +3655,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
- if (dev_priv->cdclk.hw.ref == 38400) {
+ if (dev_priv->dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
hw_state->mg_pll_bias_mask = 0;
} else {
@@ -4110,6 +4136,12 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
icl_pll_disable(dev_priv, pll, enable_reg);
}
+static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC ref */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -4170,6 +4202,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4184,6 +4217,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dpll_info = ehl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4212,6 +4246,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4390,6 +4425,9 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
int i;
+ if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
+ i915->dpll.mgr->update_ref_clks(i915);
+
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe4eefc5e7e6..49ee3bde08f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1059,6 +1059,11 @@ struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
+
+ struct {
+ int nssc;
+ int ssc;
+ } ref_clks;
} dpll;
struct list_head global_obj_list;
--
2.23.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (12 preceding siblings ...)
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
@ 2020-02-27 4:08 ` Patchwork
2020-02-27 4:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 4:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ad933d04ce1 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
649c52ce9987 drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
0d005a5d024f drm/i915: Keep the global DPLL state in a DPLL specific struct
-:311: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#311: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:3835:
+ BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
-:400: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#400: FILE: drivers/gpu/drm/i915/i915_drv.h:1057:
+ struct mutex lock;
total: 0 errors, 1 warnings, 1 checks, 339 lines checked
75d78cadd4ca drm/i915: Move the DPLL vfunc inits after the func defines
c6344edea0b3 drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
60a8609aa55a drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
-:607: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_810MHz>
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+ if (pll == SPLL_FREQ_810MHz)
-:607: CHECK:BRACES: braces {} should be used on all arms of this statement
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+ if (pll == SPLL_FREQ_810MHz)
[...]
+ else if (pll == SPLL_FREQ_1350MHz)
[...]
+ else if (pll == SPLL_FREQ_2700MHz)
[...]
+ else {
[...]
-:609: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#609: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1026:
+ else if (pll == SPLL_FREQ_1350MHz)
-:611: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_2700MHz>
#611: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1028:
+ else if (pll == SPLL_FREQ_2700MHz)
-:613: CHECK:BRACES: Unbalanced braces around else statement
#613: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1030:
+ else {
-:645: CHECK:LINE_SPACING: Please don't use multiple blank lines
#645: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1558:
+
+
-:787: CHECK:LINE_SPACING: Please don't use multiple blank lines
#787: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2593:
+
+
-:1001: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1001: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4339:
+
+
total: 0 errors, 0 warnings, 8 checks, 968 lines checked
fcb70a2a2063 drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
b20cdae29985 drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
08a1ec87a9d9 drm/i915/hsw: Split out the SPLL parameter calculation
-:29: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#29: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:969:
+ crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
total: 0 errors, 0 warnings, 1 checks, 51 lines checked
713fb8dc5a64 drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
cd28115faa3a drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
-:519: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_i915_private *' should also have an identifier name
#519: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,
-:519: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct intel_shared_dpll *' should also have an identifier name
#519: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,
total: 0 errors, 2 warnings, 0 checks, 479 lines checked
fcda3e44c96b drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
a5e019011c6b drm/i915: Unify the DPLL ref clock frequency tracking
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up DPLL output/refclock tracking
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (13 preceding siblings ...)
2020-02-27 4:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking Patchwork
@ 2020-02-27 4:14 ` Patchwork
2020-02-27 4:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 4:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Fix bounds check in intel_get_shared_dpll_id()
Okay!
Commit: drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
Okay!
Commit: drm/i915: Keep the global DPLL state in a DPLL specific struct
Okay!
Commit: drm/i915: Move the DPLL vfunc inits after the func defines
Okay!
Commit: drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
Okay!
Commit: drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
Okay!
Commit: drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
Okay!
Commit: drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
Okay!
Commit: drm/i915/hsw: Split out the SPLL parameter calculation
Okay!
Commit: drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
Okay!
Commit: drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2514:5: warning: symbol 'cnl_hdmi_pll_ref_clock' was not declared. Should it be static?
Commit: drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
Okay!
Commit: drm/i915: Unify the DPLL ref clock frequency tracking
-O:drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2511:5: warning: symbol 'cnl_hdmi_pll_ref_clock' was not declared. Should it be static?
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up DPLL output/refclock tracking
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (14 preceding siblings ...)
2020-02-27 4:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-02-27 4:33 ` Patchwork
2020-02-28 0:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-27 4:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16725
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16725:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/fi-tgl-dsi/igt@runner@aborted.html
- {fi-ehl-1}: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/fi-ehl-1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_16725 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/fi-tgl-y/igt@gem_flink_basic@double-flink.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][5] ([CI#94] / [i915#402]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (51 -> 41)
------------------------------
Missing (10): fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-ivb-3770 fi-cfl-8109u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8010 -> Patchwork_16725
CI-20190529: 20190529
CI_DRM_8010: 97bbec4d80df1c6573fc7063ad830e8beefe07c8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5471: 668afe52887a164ee6a12fd1c898bc1c9086cf3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16725: a5e019011c6b18582d2c4722209a2d8fd5b0ed38 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a5e019011c6b drm/i915: Unify the DPLL ref clock frequency tracking
fcda3e44c96b drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
cd28115faa3a drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
713fb8dc5a64 drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
08a1ec87a9d9 drm/i915/hsw: Split out the SPLL parameter calculation
b20cdae29985 drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
fcb70a2a2063 drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
60a8609aa55a drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
c6344edea0b3 drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
75d78cadd4ca drm/i915: Move the DPLL vfunc inits after the func defines
0d005a5d024f drm/i915: Keep the global DPLL state in a DPLL specific struct
649c52ce9987 drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
3ad933d04ce1 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
@ 2020-02-27 17:57 ` Ville Syrjälä
2020-02-27 18:34 ` Imre Deak
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 17:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Feb 26, 2020 at 10:34:53PM +0200, Imre Deak wrote:
> Split out the PLL parameter->frequency conversion logic for each type of
> PLL for symmetry with their corresponding inverse conversion functions.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 269 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
> 4 files changed, 140 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c38addd07e42..17cee6f80d8b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> static void gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>
> intel_dsc_get_config(encoder, pipe_config);
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> - pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
> + pipe_config->port_clock = intel_dpll_get_freq(i915,
> + pipe_config->shared_dpll);
For this one I'm thinking it might be better to pass the pll state
instead. That way we could use this function already before we've
actually committed the state.
We can think about that later though.
Patches 1-11 look OK to me:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5e6f81b140d4..284219da7df8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> encoder->port);
> else
> - pipe_config->port_clock = intel_dpll_get_freq(encoder,
> - pipe_config);
> + pipe_config->port_clock =
> + intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
>
> ddi_dotclock_get(pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ebd55fdaf4cd..b87b4ff5de52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> -static int hsw_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> -
> - switch (pll->info->id) {
> - case DPLL_ID_WRPLL1:
> - case DPLL_ID_WRPLL2:
> - return hsw_ddi_wrpll_get_freq(dev_priv, pll);
> - case DPLL_ID_SPLL:
> - return hsw_ddi_spll_get_freq(dev_priv, pll);
> - default:
> - return hsw_ddi_lcpll_get_freq(dev_priv, pll);
> - }
> -}
> -
> static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> .enable = hsw_ddi_wrpll_enable,
> .disable = hsw_ddi_wrpll_disable,
> .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> + .get_freq = hsw_ddi_wrpll_get_freq,
> };
>
> static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> .enable = hsw_ddi_spll_enable,
> .disable = hsw_ddi_spll_disable,
> .get_hw_state = hsw_ddi_spll_get_hw_state,
> + .get_freq = hsw_ddi_spll_get_freq,
> };
>
> static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
> @@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> .enable = hsw_ddi_lcpll_enable,
> .disable = hsw_ddi_lcpll_disable,
> .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> + .get_freq = hsw_ddi_lcpll_get_freq,
> };
>
> static const struct dpll_info hsw_plls[] = {
> @@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> -static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
> +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> {
> + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> int ref_clock = 24000;
> u32 p0, p1, p2, dco_freq;
>
> @@ -1670,6 +1658,40 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> +static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + int link_clock = 0;
> +
> + switch ((pll->state.hw_state.ctrl1 &
> + DPLL_CTRL1_LINK_RATE_MASK(0)) >>
> + DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
> + case DPLL_CTRL1_LINK_RATE_810:
> + link_clock = 81000;
> + break;
> + case DPLL_CTRL1_LINK_RATE_1080:
> + link_clock = 108000;
> + break;
> + case DPLL_CTRL1_LINK_RATE_1350:
> + link_clock = 135000;
> + break;
> + case DPLL_CTRL1_LINK_RATE_1620:
> + link_clock = 162000;
> + break;
> + case DPLL_CTRL1_LINK_RATE_2160:
> + link_clock = 216000;
> + break;
> + case DPLL_CTRL1_LINK_RATE_2700:
> + link_clock = 270000;
> + break;
> + default:
> + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> + break;
> + }
> +
> + return link_clock * 2;
> +}
> +
> static bool skl_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -1719,50 +1741,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> -static int skl_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> +static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> {
> - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> - int link_clock;
> -
> /*
> * ctrl1 register is already shifted for each pll, just use 0 to get
> * the internal shift for each field
> */
> - if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
> - link_clock = skl_calc_wrpll_link(pll_state);
> - } else {
> - link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
> - link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
> -
> - switch (link_clock) {
> - case DPLL_CTRL1_LINK_RATE_810:
> - link_clock = 81000;
> - break;
> - case DPLL_CTRL1_LINK_RATE_1080:
> - link_clock = 108000;
> - break;
> - case DPLL_CTRL1_LINK_RATE_1350:
> - link_clock = 135000;
> - break;
> - case DPLL_CTRL1_LINK_RATE_1620:
> - link_clock = 162000;
> - break;
> - case DPLL_CTRL1_LINK_RATE_2160:
> - link_clock = 216000;
> - break;
> - case DPLL_CTRL1_LINK_RATE_2700:
> - link_clock = 270000;
> - break;
> - default:
> - drm_WARN(encoder->base.dev, 1,
> - "Unsupported link rate\n");
> - break;
> - }
> - link_clock *= 2;
> - }
> -
> - return link_clock;
> + if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> + return skl_ddi_wrpll_get_freq(i915, pll);
> + else
> + return skl_ddi_lcpll_get_freq(i915, pll);
> }
>
> static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
> @@ -1779,12 +1768,14 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> .enable = skl_ddi_pll_enable,
> .disable = skl_ddi_pll_disable,
> .get_hw_state = skl_ddi_pll_get_hw_state,
> + .get_freq = skl_ddi_pll_get_freq,
> };
>
> static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> .enable = skl_ddi_dpll0_enable,
> .disable = skl_ddi_dpll0_disable,
> .get_hw_state = skl_ddi_dpll0_get_hw_state,
> + .get_freq = skl_ddi_pll_get_freq,
> };
>
> static const struct dpll_info skl_plls[] = {
> @@ -2190,11 +2181,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> }
>
> -static int bxt_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> {
> - struct intel_dpll_hw_state *pll_state =
> - &crtc_state->shared_dpll->state.hw_state;
> + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> struct dpll clock;
>
> clock.m1 = 2;
> @@ -2264,6 +2254,7 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> .enable = bxt_ddi_pll_enable,
> .disable = bxt_ddi_pll_disable,
> .get_hw_state = bxt_ddi_pll_get_hw_state,
> + .get_freq = bxt_ddi_pll_get_freq,
> };
>
> static const struct dpll_info bxt_plls[] = {
> @@ -2608,9 +2599,10 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> -static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> - struct intel_dpll_hw_state *pll_state)
> +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> + const struct intel_shared_dpll *pll)
> {
> + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> u32 p0, p1, p2, dco_freq, ref_clock;
>
> p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> @@ -2709,6 +2701,44 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> +static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + int link_clock = 0;
> +
> + switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
> + case DPLL_CFGCR0_LINK_RATE_810:
> + link_clock = 81000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_1080:
> + link_clock = 108000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_1350:
> + link_clock = 135000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_1620:
> + link_clock = 162000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_2160:
> + link_clock = 216000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_2700:
> + link_clock = 270000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_3240:
> + link_clock = 324000;
> + break;
> + case DPLL_CFGCR0_LINK_RATE_4050:
> + link_clock = 405000;
> + break;
> + default:
> + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> + break;
> + }
> +
> + return link_clock * 2;
> +}
> +
> static bool cnl_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -2758,51 +2788,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> -static int cnl_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> +static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
> - int link_clock;
> -
> - if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> - link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> - } else {
> - link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
> -
> - switch (link_clock) {
> - case DPLL_CFGCR0_LINK_RATE_810:
> - link_clock = 81000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_1080:
> - link_clock = 108000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_1350:
> - link_clock = 135000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_1620:
> - link_clock = 162000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_2160:
> - link_clock = 216000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_2700:
> - link_clock = 270000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_3240:
> - link_clock = 324000;
> - break;
> - case DPLL_CFGCR0_LINK_RATE_4050:
> - link_clock = 405000;
> - break;
> - default:
> - drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
> - break;
> - }
> - link_clock *= 2;
> - }
> -
> - return link_clock;
> + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> + return cnl_ddi_wrpll_get_freq(i915, pll);
> + else
> + return cnl_ddi_lcpll_get_freq(i915, pll);
> }
>
> static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> @@ -2818,6 +2810,7 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
> .enable = cnl_ddi_pll_enable,
> .disable = cnl_ddi_pll_disable,
> .get_hw_state = cnl_ddi_pll_get_hw_state,
> + .get_freq = cnl_ddi_pll_get_freq,
> };
>
> static const struct dpll_info cnl_plls[] = {
> @@ -2979,6 +2972,18 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> return true;
> }
>
> +static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + /*
> + * The PLL outputs multiple frequencies at the same time, selection is
> + * made at DDI clock mux level.
> + */
> + drm_WARN_ON(&i915->drm, 1);
> +
> + return 0;
> +}
> +
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder,
> struct intel_dpll_hw_state *pll_state)
> @@ -3317,9 +3322,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> return true;
> }
>
> -static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> - const struct intel_dpll_hw_state *pll_state)
> +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> + const struct intel_shared_dpll *pll)
> {
> + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> u64 tmp;
>
> @@ -3388,19 +3394,6 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> return tmp;
> }
>
> -static int icl_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> - if (intel_phy_is_combo(dev_priv, phy))
> - return cnl_calc_wrpll_link(dev_priv, pll_state);
> - else
> - return icl_calc_mg_pll_link(dev_priv, pll_state);
> -}
> -
> /**
> * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
> * @crtc_state: state for the CRTC to select the DPLL for
> @@ -3485,6 +3478,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> +static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + return cnl_ddi_wrpll_get_freq(i915, pll);
> +}
> +
> static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -4141,18 +4140,21 @@ static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> .enable = combo_pll_enable,
> .disable = combo_pll_disable,
> .get_hw_state = combo_pll_get_hw_state,
> + .get_freq = icl_ddi_combo_pll_get_freq,
> };
>
> static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> .enable = tbt_pll_enable,
> .disable = tbt_pll_disable,
> .get_hw_state = tbt_pll_get_hw_state,
> + .get_freq = icl_ddi_tbt_pll_get_freq,
> };
>
> static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = mg_pll_get_hw_state,
> + .get_freq = icl_ddi_mg_pll_get_freq,
> };
>
> static const struct dpll_info icl_plls[] = {
> @@ -4192,6 +4194,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = dkl_pll_get_hw_state,
> + .get_freq = icl_ddi_mg_pll_get_freq,
> };
>
> static const struct dpll_info tgl_plls[] = {
> @@ -4348,27 +4351,15 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> dpll_mgr->update_active_dpll(state, crtc, encoder);
> }
>
> -int intel_dpll_get_freq(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> +int intel_dpll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -
> - if (INTEL_GEN(i915) >= 11)
> - return icl_ddi_clock_get(encoder, crtc_state);
> - else if (IS_CANNONLAKE(i915))
> - return cnl_ddi_clock_get(encoder, crtc_state);
> - else if (IS_GEN9_LP(i915))
> - return bxt_ddi_clock_get(encoder, crtc_state);
> - else if (IS_GEN9_BC(i915))
> - return skl_ddi_clock_get(encoder, crtc_state);
> - else if (INTEL_GEN(i915) <= 8)
> - hsw_ddi_clock_get(encoder, crtc_state);
> + if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
> + return 0;
>
> - drm_WARN_ON(&i915->drm, 1);
> - return 0;
> + return pll->info->funcs->get_freq(i915, pll);
> }
>
> -
> static void readout_dpll_hw_state(struct drm_i915_private *i915,
> struct intel_shared_dpll *pll)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index fadc240eccf6..c155935874d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -278,6 +278,9 @@ struct intel_shared_dpll_funcs {
> bool (*get_hw_state)(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state *hw_state);
> +
> + int (*get_freq)(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll);
> };
>
> /**
> @@ -372,8 +375,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> void intel_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -int intel_dpll_get_freq(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state);
> +int intel_dpll_get_freq(struct drm_i915_private *,
> + const struct intel_shared_dpll *);
> void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> @@ -384,7 +387,6 @@ void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
>
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state);
> -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> --
> 2.23.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
@ 2020-02-27 17:58 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 17:58 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Feb 26, 2020 at 10:34:54PM +0200, Imre Deak wrote:
> Instead of reading out the WRPLL/SPLL control values from HW, we can use
> the DPLL state that was already read out, or swapped-to.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b87b4ff5de52..7e6da58a47c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> const struct intel_shared_dpll *pll)
> {
> - i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
> - WRPLL_CTL(0) : WRPLL_CTL(1);
> int refclk;
> int n, p, r;
> - u32 wrpll;
> + u32 wrpll = pll->state.hw_state.wrpll;
>
> - wrpll = intel_de_read(dev_priv, reg);
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> /*
> @@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
> {
> int link_clock = 0;
>
> - switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
> + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
> case SPLL_FREQ_810MHz:
> link_clock = 81000;
> break;
> --
> 2.23.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
@ 2020-02-27 18:13 ` Ville Syrjälä
2020-02-27 19:01 ` Imre Deak
2020-02-28 15:33 ` [Intel-gfx] [PATCH v2 " Imre Deak
1 sibling, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 18:13 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Feb 26, 2020 at 10:34:55PM +0200, Imre Deak wrote:
> All platforms using the shared DPLL framework use 3 reference clocks for
> their DPLLs: SSC, non-SSC and DSI. For a more unified way across
> platforms store the frequency of these ref clocks as part of the DPLL
> global state. This also allows us to keep the HW access reading out the
> ref clock value separate from the DPLL frequency calculation that
> depends on the ref clock.
>
> For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
> has its own logic for calculating DPLL parameters instead of the shared
> DPLL framework.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 5 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 132 +++++++++++-------
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> 3 files changed, 95 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d2461d7946bf..6675b7e34f0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -920,6 +920,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> int i;
>
> drm_modeset_lock_all(dev);
> +
> + seq_printf(m, "PLL refclks: non-SSC: %d kHZ, SSC: %d kHZ\n",
nit: "kHz"
> + dev_priv->dpll.ref_clks.nssc,
> + dev_priv->dpll.ref_clks.ssc);
> +
> for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
> struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 7e6da58a47c9..44db46782770 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -56,6 +56,7 @@ struct intel_dpll_mgr {
> void (*update_active_dpll)(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> + void (*update_ref_clks)(struct drm_i915_private *i915);
> void (*dump_hw_state)(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state);
> };
> @@ -886,16 +887,9 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
>
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> - /*
> - * muxed-SSC for BDW.
> - * non-SSC for non-ULT HSW. Check FUSE_STRAP3
> - * for the non-SSC reference frequency.
> - */
> + /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
> if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
> - if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> - refclk = 24;
> - else
> - refclk = 135;
> + refclk = dev_priv->dpll.ref_clks.nssc;
> break;
> }
> /* fall through */
> @@ -905,10 +899,10 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> * code only cares about 5% accuracy, and spread is a max of
> * 0.5% downspread.
> */
> - refclk = 135;
> + refclk = dev_priv->dpll.ref_clks.ssc;
> break;
> case WRPLL_REF_LCPLL:
> - refclk = 2700;
> + refclk = 2700000;
> break;
> default:
> MISSING_CASE(wrpll);
> @@ -920,7 +914,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
>
> /* Convert to KHz, p & r have a fixed point portion */
> - return (refclk * n * 100) / (p * r) * 2;
> + return (refclk * n / 10) / (p * r) * 2;
> }
>
> static struct intel_shared_dpll *
> @@ -1049,6 +1043,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> +static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + i915->dpll.ref_clks.ssc = 135000;
> + /* Non-SSC is only used on non-ULT HSW. */
> + if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> + i915->dpll.ref_clks.nssc = 24000;
> + else
> + i915->dpll.ref_clks.nssc = 135000;
I couldn't remember whether the PCH and CPU SSC references have the same
frquency. But looks like they do.
> +}
> +
> static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -1108,6 +1112,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
> .dpll_info = hsw_plls,
> .get_dplls = hsw_get_dpll,
> .put_dplls = intel_put_dpll,
> + .update_ref_clks = hsw_update_dpll_ref_clks,
> .dump_hw_state = hsw_dump_hw_state,
> };
>
> @@ -1523,6 +1528,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>
> static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> u32 ctrl1, cfgcr1, cfgcr2;
> struct skl_wrpll_params wrpll_params = { 0, };
>
> @@ -1534,7 +1540,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>
> ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
>
> - if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
> + if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
> + i915->dpll.ref_clks.nssc,
> &wrpll_params))
> return false;
>
> @@ -1561,7 +1568,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> const struct intel_shared_dpll *pll)
> {
> const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> - int ref_clock = 24000;
> + int ref_clock = i915->dpll.ref_clks.nssc;
> u32 p0, p1, p2, dco_freq;
>
> p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
> @@ -1751,6 +1758,12 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> return skl_ddi_lcpll_get_freq(i915, pll);
> }
>
> +static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + /* No SSC ref */
> + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> +}
> +
> static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -1787,6 +1800,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> .dpll_info = skl_plls,
> .get_dplls = skl_get_dpll,
> .put_dplls = intel_put_dpll,
> + .update_ref_clks = skl_update_dpll_ref_clks,
> .dump_hw_state = skl_dump_hw_state,
> };
>
> @@ -2192,7 +2206,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
> clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
>
> - return chv_calc_dpll_params(100000, &clock);
> + return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
> }
>
> static bool bxt_get_dpll(struct intel_atomic_state *state,
> @@ -2228,6 +2242,13 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
> return true;
> }
>
> +static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + i915->dpll.ref_clks.ssc = 100000;
> + i915->dpll.ref_clks.nssc = 100000;
> + /* DSI non-SSC ref 19.2MHz */
> +}
> +
> static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -2265,6 +2286,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
> .dpll_info = bxt_plls,
> .get_dplls = bxt_get_dpll,
> .put_dplls = intel_put_dpll,
> + .update_ref_clks = bxt_update_dpll_ref_clks,
> .dump_hw_state = bxt_dump_hw_state,
> };
>
> @@ -2508,27 +2530,13 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> params->dco_fraction = dco & 0x7fff;
> }
>
> -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
> -{
> - int ref_clock = dev_priv->cdclk.hw.ref;
> -
> - /*
> - * For ICL+, the spec states: if reference frequency is 38.4,
> - * use 19.2 because the DPLL automatically divides that by 2.
> - */
> - if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
> - ref_clock = 19200;
> -
> - return ref_clock;
> -}
> -
> static bool
> cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *wrpll_params)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 afe_clock = crtc_state->port_clock * 5;
> - u32 ref_clock;
> + int ref_clock = dev_priv->dpll.ref_clks.nssc;
> u32 dco_min = 7998000;
> u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> @@ -2560,9 +2568,6 @@ cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> return false;
>
> cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> -
> - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> -
> cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
> pdiv, qdiv, kdiv);
>
> @@ -2596,11 +2601,12 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> -static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> - const struct intel_shared_dpll *pll)
> +static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> + const struct intel_shared_dpll *pll,
> + int ref_clock)
> {
> const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> - u32 p0, p1, p2, dco_freq, ref_clock;
> + u32 p0, p1, p2, dco_freq;
>
> p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
> @@ -2639,8 +2645,6 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> break;
> }
>
> - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> -
> dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
> ref_clock;
>
> @@ -2653,6 +2657,12 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> return dco_freq / (p0 * p1 * p2 * 5);
> }
>
> +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
> +}
> +
> static bool
> cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> @@ -2794,6 +2804,12 @@ static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> return cnl_ddi_lcpll_get_freq(i915, pll);
> }
>
> +static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + /* No SSC reference */
> + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> +}
> +
> static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -2821,6 +2837,7 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
> .dpll_info = cnl_plls,
> .get_dplls = cnl_get_dpll,
> .put_dplls = intel_put_dpll,
> + .update_ref_clks = cnl_update_dpll_ref_clks,
> .dump_hw_state = cnl_dump_hw_state,
> };
>
> @@ -2916,7 +2933,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> const struct icl_combo_pll_params *params =
> - dev_priv->cdclk.hw.ref == 24000 ?
> + dev_priv->dpll.ref_clks.nssc == 24000 ?
> icl_dp_combo_pll_24MHz_values :
> icl_dp_combo_pll_19_2MHz_values;
> int clock = crtc_state->port_clock;
> @@ -2939,9 +2956,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> - switch (dev_priv->cdclk.hw.ref) {
> + switch (dev_priv->dpll.ref_clks.nssc) {
> default:
> - MISSING_CASE(dev_priv->cdclk.hw.ref);
> + MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
> /* fall-through */
> case 19200:
> case 38400:
> @@ -2952,9 +2969,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> break;
> }
> } else {
> - switch (dev_priv->cdclk.hw.ref) {
> + switch (dev_priv->dpll.ref_clks.nssc) {
> default:
> - MISSING_CASE(dev_priv->cdclk.hw.ref);
> + MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
> /* fall-through */
> case 19200:
> case 38400:
> @@ -3118,7 +3135,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> struct intel_dpll_hw_state *pll_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - int refclk_khz = dev_priv->cdclk.hw.ref;
> + int refclk_khz = dev_priv->dpll.ref_clks.nssc;
> int clock = crtc_state->port_clock;
> u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> u32 iref_ndiv, iref_trim, iref_pulse_w;
> @@ -3326,7 +3343,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> u64 tmp;
>
> - ref_clock = dev_priv->cdclk.hw.ref;
> + ref_clock = dev_priv->dpll.ref_clks.nssc;
>
> if (INTEL_GEN(dev_priv) >= 12) {
> m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
> @@ -3478,7 +3495,16 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> const struct intel_shared_dpll *pll)
> {
> - return cnl_ddi_wrpll_get_freq(i915, pll);
> + int ref_clock = i915->dpll.ref_clks.nssc;
> +
> + /*
> + * For ICL+, the spec states: if reference frequency is 38.4,
> + * use 19.2 because the DPLL automatically divides that by 2.
> + */
> + if (ref_clock == 38400)
> + ref_clock = 19200;
I was pondering whether it would be better to store the divided ref,
but I guess we need the original value for some other things, and it's
really the DPLL in HDMI mode that does the extra /2 for us.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + return __cnl_ddi_wrpll_get_freq(i915, pll, ref_clock);
> }
>
> static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> @@ -3629,7 +3655,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->mg_pll_tdc_coldst_bias =
> intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
>
> - if (dev_priv->cdclk.hw.ref == 38400) {
> + if (dev_priv->dpll.ref_clks.nssc == 38400) {
> hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
> hw_state->mg_pll_bias_mask = 0;
> } else {
> @@ -4110,6 +4136,12 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
> icl_pll_disable(dev_priv, pll, enable_reg);
> }
>
> +static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + /* No SSC ref */
> + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> +}
> +
> static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -4170,6 +4202,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_active_dpll = icl_update_active_dpll,
> + .update_ref_clks = icl_update_dpll_ref_clks,
> .dump_hw_state = icl_dump_hw_state,
> };
>
> @@ -4184,6 +4217,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
> .dpll_info = ehl_plls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> + .update_ref_clks = icl_update_dpll_ref_clks,
> .dump_hw_state = icl_dump_hw_state,
> };
>
> @@ -4212,6 +4246,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_active_dpll = icl_update_active_dpll,
> + .update_ref_clks = icl_update_dpll_ref_clks,
> .dump_hw_state = icl_dump_hw_state,
> };
>
> @@ -4390,6 +4425,9 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
> {
> int i;
>
> + if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
> + i915->dpll.mgr->update_ref_clks(i915);
> +
> for (i = 0; i < i915->dpll.num_shared_dpll; i++)
> readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe4eefc5e7e6..49ee3bde08f5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1059,6 +1059,11 @@ struct drm_i915_private {
> int num_shared_dpll;
> struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> const struct intel_dpll_mgr *mgr;
> +
> + struct {
> + int nssc;
> + int ssc;
> + } ref_clks;
> } dpll;
>
> struct list_head global_obj_list;
> --
> 2.23.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
2020-02-27 17:57 ` Ville Syrjälä
@ 2020-02-27 18:34 ` Imre Deak
2020-02-27 18:49 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Imre Deak @ 2020-02-27 18:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Feb 27, 2020 at 07:57:41PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 26, 2020 at 10:34:53PM +0200, Imre Deak wrote:
> > Split out the PLL parameter->frequency conversion logic for each type of
> > PLL for symmetry with their corresponding inverse conversion functions.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 269 +++++++++---------
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
> > 4 files changed, 140 insertions(+), 145 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index c38addd07e42..17cee6f80d8b 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> > static void gen11_dsi_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config)
> > {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> >
> > intel_dsc_get_config(encoder, pipe_config);
> >
> > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> > - pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
> > + pipe_config->port_clock = intel_dpll_get_freq(i915,
> > + pipe_config->shared_dpll);
>
> For this one I'm thinking it might be better to pass the pll state
> instead. That way we could use this function already before we've
> actually committed the state.
Right, forgot about using this before swapping the new state into
pll->state. Since pll can't be deducted from the state how about:
int (*get_freq)(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *hw_state);
?
I can resend with that also making the change adding get_freq a separate
patch as I originally intended.
> We can think about that later though.
>
> Patches 1-11 look OK to me:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks.
>
> >
> > pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> > if (intel_dsi->dual_link)
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 5e6f81b140d4..284219da7df8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> > pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> > encoder->port);
> > else
> > - pipe_config->port_clock = intel_dpll_get_freq(encoder,
> > - pipe_config);
> > + pipe_config->port_clock =
> > + intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
> >
> > ddi_dotclock_get(pipe_config);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index ebd55fdaf4cd..b87b4ff5de52 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > -static int hsw_ddi_clock_get(struct intel_encoder *encoder,
> > - struct intel_crtc_state *pipe_config)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > - struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> > -
> > - switch (pll->info->id) {
> > - case DPLL_ID_WRPLL1:
> > - case DPLL_ID_WRPLL2:
> > - return hsw_ddi_wrpll_get_freq(dev_priv, pll);
> > - case DPLL_ID_SPLL:
> > - return hsw_ddi_spll_get_freq(dev_priv, pll);
> > - default:
> > - return hsw_ddi_lcpll_get_freq(dev_priv, pll);
> > - }
> > -}
> > -
> > static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> > .enable = hsw_ddi_wrpll_enable,
> > .disable = hsw_ddi_wrpll_disable,
> > .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> > + .get_freq = hsw_ddi_wrpll_get_freq,
> > };
> >
> > static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> > .enable = hsw_ddi_spll_enable,
> > .disable = hsw_ddi_spll_disable,
> > .get_hw_state = hsw_ddi_spll_get_hw_state,
> > + .get_freq = hsw_ddi_spll_get_freq,
> > };
> >
> > static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
> > @@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> > .enable = hsw_ddi_lcpll_enable,
> > .disable = hsw_ddi_lcpll_disable,
> > .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> > + .get_freq = hsw_ddi_lcpll_get_freq,
> > };
> >
> > static const struct dpll_info hsw_plls[] = {
> > @@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > -static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
> > +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > {
> > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > int ref_clock = 24000;
> > u32 p0, p1, p2, dco_freq;
> >
> > @@ -1670,6 +1658,40 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > +static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + int link_clock = 0;
> > +
> > + switch ((pll->state.hw_state.ctrl1 &
> > + DPLL_CTRL1_LINK_RATE_MASK(0)) >>
> > + DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
> > + case DPLL_CTRL1_LINK_RATE_810:
> > + link_clock = 81000;
> > + break;
> > + case DPLL_CTRL1_LINK_RATE_1080:
> > + link_clock = 108000;
> > + break;
> > + case DPLL_CTRL1_LINK_RATE_1350:
> > + link_clock = 135000;
> > + break;
> > + case DPLL_CTRL1_LINK_RATE_1620:
> > + link_clock = 162000;
> > + break;
> > + case DPLL_CTRL1_LINK_RATE_2160:
> > + link_clock = 216000;
> > + break;
> > + case DPLL_CTRL1_LINK_RATE_2700:
> > + link_clock = 270000;
> > + break;
> > + default:
> > + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> > + break;
> > + }
> > +
> > + return link_clock * 2;
> > +}
> > +
> > static bool skl_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder)
> > @@ -1719,50 +1741,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > -static int skl_ddi_clock_get(struct intel_encoder *encoder,
> > - struct intel_crtc_state *crtc_state)
> > +static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > {
> > - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> > - int link_clock;
> > -
> > /*
> > * ctrl1 register is already shifted for each pll, just use 0 to get
> > * the internal shift for each field
> > */
> > - if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
> > - link_clock = skl_calc_wrpll_link(pll_state);
> > - } else {
> > - link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
> > - link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
> > -
> > - switch (link_clock) {
> > - case DPLL_CTRL1_LINK_RATE_810:
> > - link_clock = 81000;
> > - break;
> > - case DPLL_CTRL1_LINK_RATE_1080:
> > - link_clock = 108000;
> > - break;
> > - case DPLL_CTRL1_LINK_RATE_1350:
> > - link_clock = 135000;
> > - break;
> > - case DPLL_CTRL1_LINK_RATE_1620:
> > - link_clock = 162000;
> > - break;
> > - case DPLL_CTRL1_LINK_RATE_2160:
> > - link_clock = 216000;
> > - break;
> > - case DPLL_CTRL1_LINK_RATE_2700:
> > - link_clock = 270000;
> > - break;
> > - default:
> > - drm_WARN(encoder->base.dev, 1,
> > - "Unsupported link rate\n");
> > - break;
> > - }
> > - link_clock *= 2;
> > - }
> > -
> > - return link_clock;
> > + if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> > + return skl_ddi_wrpll_get_freq(i915, pll);
> > + else
> > + return skl_ddi_lcpll_get_freq(i915, pll);
> > }
> >
> > static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
> > @@ -1779,12 +1768,14 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> > .enable = skl_ddi_pll_enable,
> > .disable = skl_ddi_pll_disable,
> > .get_hw_state = skl_ddi_pll_get_hw_state,
> > + .get_freq = skl_ddi_pll_get_freq,
> > };
> >
> > static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> > .enable = skl_ddi_dpll0_enable,
> > .disable = skl_ddi_dpll0_disable,
> > .get_hw_state = skl_ddi_dpll0_get_hw_state,
> > + .get_freq = skl_ddi_pll_get_freq,
> > };
> >
> > static const struct dpll_info skl_plls[] = {
> > @@ -2190,11 +2181,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> > }
> >
> > -static int bxt_ddi_clock_get(struct intel_encoder *encoder,
> > - struct intel_crtc_state *crtc_state)
> > +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > {
> > - struct intel_dpll_hw_state *pll_state =
> > - &crtc_state->shared_dpll->state.hw_state;
> > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > struct dpll clock;
> >
> > clock.m1 = 2;
> > @@ -2264,6 +2254,7 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> > .enable = bxt_ddi_pll_enable,
> > .disable = bxt_ddi_pll_disable,
> > .get_hw_state = bxt_ddi_pll_get_hw_state,
> > + .get_freq = bxt_ddi_pll_get_freq,
> > };
> >
> > static const struct dpll_info bxt_plls[] = {
> > @@ -2608,9 +2599,10 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > -static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> > - struct intel_dpll_hw_state *pll_state)
> > +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > + const struct intel_shared_dpll *pll)
> > {
> > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > u32 p0, p1, p2, dco_freq, ref_clock;
> >
> > p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> > @@ -2709,6 +2701,44 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > +static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + int link_clock = 0;
> > +
> > + switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
> > + case DPLL_CFGCR0_LINK_RATE_810:
> > + link_clock = 81000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_1080:
> > + link_clock = 108000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_1350:
> > + link_clock = 135000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_1620:
> > + link_clock = 162000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_2160:
> > + link_clock = 216000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_2700:
> > + link_clock = 270000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_3240:
> > + link_clock = 324000;
> > + break;
> > + case DPLL_CFGCR0_LINK_RATE_4050:
> > + link_clock = 405000;
> > + break;
> > + default:
> > + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> > + break;
> > + }
> > +
> > + return link_clock * 2;
> > +}
> > +
> > static bool cnl_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder)
> > @@ -2758,51 +2788,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > -static int cnl_ddi_clock_get(struct intel_encoder *encoder,
> > - struct intel_crtc_state *pipe_config)
> > +static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
> > - int link_clock;
> > -
> > - if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> > - link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> > - } else {
> > - link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
> > -
> > - switch (link_clock) {
> > - case DPLL_CFGCR0_LINK_RATE_810:
> > - link_clock = 81000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_1080:
> > - link_clock = 108000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_1350:
> > - link_clock = 135000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_1620:
> > - link_clock = 162000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_2160:
> > - link_clock = 216000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_2700:
> > - link_clock = 270000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_3240:
> > - link_clock = 324000;
> > - break;
> > - case DPLL_CFGCR0_LINK_RATE_4050:
> > - link_clock = 405000;
> > - break;
> > - default:
> > - drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
> > - break;
> > - }
> > - link_clock *= 2;
> > - }
> > -
> > - return link_clock;
> > + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> > + return cnl_ddi_wrpll_get_freq(i915, pll);
> > + else
> > + return cnl_ddi_lcpll_get_freq(i915, pll);
> > }
> >
> > static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> > @@ -2818,6 +2810,7 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
> > .enable = cnl_ddi_pll_enable,
> > .disable = cnl_ddi_pll_disable,
> > .get_hw_state = cnl_ddi_pll_get_hw_state,
> > + .get_freq = cnl_ddi_pll_get_freq,
> > };
> >
> > static const struct dpll_info cnl_plls[] = {
> > @@ -2979,6 +2972,18 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> > return true;
> > }
> >
> > +static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + /*
> > + * The PLL outputs multiple frequencies at the same time, selection is
> > + * made at DDI clock mux level.
> > + */
> > + drm_WARN_ON(&i915->drm, 1);
> > +
> > + return 0;
> > +}
> > +
> > static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> > struct intel_encoder *encoder,
> > struct intel_dpll_hw_state *pll_state)
> > @@ -3317,9 +3322,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> > return true;
> > }
> >
> > -static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> > - const struct intel_dpll_hw_state *pll_state)
> > +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> > + const struct intel_shared_dpll *pll)
> > {
> > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> > u64 tmp;
> >
> > @@ -3388,19 +3394,6 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> > return tmp;
> > }
> >
> > -static int icl_ddi_clock_get(struct intel_encoder *encoder,
> > - struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > -
> > - if (intel_phy_is_combo(dev_priv, phy))
> > - return cnl_calc_wrpll_link(dev_priv, pll_state);
> > - else
> > - return icl_calc_mg_pll_link(dev_priv, pll_state);
> > -}
> > -
> > /**
> > * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
> > * @crtc_state: state for the CRTC to select the DPLL for
> > @@ -3485,6 +3478,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > +static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + return cnl_ddi_wrpll_get_freq(i915, pll);
> > +}
> > +
> > static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder)
> > @@ -4141,18 +4140,21 @@ static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> > .enable = combo_pll_enable,
> > .disable = combo_pll_disable,
> > .get_hw_state = combo_pll_get_hw_state,
> > + .get_freq = icl_ddi_combo_pll_get_freq,
> > };
> >
> > static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> > .enable = tbt_pll_enable,
> > .disable = tbt_pll_disable,
> > .get_hw_state = tbt_pll_get_hw_state,
> > + .get_freq = icl_ddi_tbt_pll_get_freq,
> > };
> >
> > static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > .enable = mg_pll_enable,
> > .disable = mg_pll_disable,
> > .get_hw_state = mg_pll_get_hw_state,
> > + .get_freq = icl_ddi_mg_pll_get_freq,
> > };
> >
> > static const struct dpll_info icl_plls[] = {
> > @@ -4192,6 +4194,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > .enable = mg_pll_enable,
> > .disable = mg_pll_disable,
> > .get_hw_state = dkl_pll_get_hw_state,
> > + .get_freq = icl_ddi_mg_pll_get_freq,
> > };
> >
> > static const struct dpll_info tgl_plls[] = {
> > @@ -4348,27 +4351,15 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> > dpll_mgr->update_active_dpll(state, crtc, encoder);
> > }
> >
> > -int intel_dpll_get_freq(struct intel_encoder *encoder,
> > - struct intel_crtc_state *crtc_state)
> > +int intel_dpll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > {
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > -
> > - if (INTEL_GEN(i915) >= 11)
> > - return icl_ddi_clock_get(encoder, crtc_state);
> > - else if (IS_CANNONLAKE(i915))
> > - return cnl_ddi_clock_get(encoder, crtc_state);
> > - else if (IS_GEN9_LP(i915))
> > - return bxt_ddi_clock_get(encoder, crtc_state);
> > - else if (IS_GEN9_BC(i915))
> > - return skl_ddi_clock_get(encoder, crtc_state);
> > - else if (INTEL_GEN(i915) <= 8)
> > - hsw_ddi_clock_get(encoder, crtc_state);
> > + if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
> > + return 0;
> >
> > - drm_WARN_ON(&i915->drm, 1);
> > - return 0;
> > + return pll->info->funcs->get_freq(i915, pll);
> > }
> >
> > -
> > static void readout_dpll_hw_state(struct drm_i915_private *i915,
> > struct intel_shared_dpll *pll)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index fadc240eccf6..c155935874d4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -278,6 +278,9 @@ struct intel_shared_dpll_funcs {
> > bool (*get_hw_state)(struct drm_i915_private *dev_priv,
> > struct intel_shared_dpll *pll,
> > struct intel_dpll_hw_state *hw_state);
> > +
> > + int (*get_freq)(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll);
> > };
> >
> > /**
> > @@ -372,8 +375,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > void intel_update_active_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder);
> > -int intel_dpll_get_freq(struct intel_encoder *encoder,
> > - struct intel_crtc_state *crtc_state);
> > +int intel_dpll_get_freq(struct drm_i915_private *,
> > + const struct intel_shared_dpll *);
> > void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
> > void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > @@ -384,7 +387,6 @@ void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
> >
> > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state);
> > -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> > enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> > bool intel_dpll_is_combophy(enum intel_dpll_id id);
> >
> > --
> > 2.23.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
2020-02-27 18:34 ` Imre Deak
@ 2020-02-27 18:49 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2020-02-27 18:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Feb 27, 2020 at 08:34:53PM +0200, Imre Deak wrote:
> On Thu, Feb 27, 2020 at 07:57:41PM +0200, Ville Syrjälä wrote:
> > On Wed, Feb 26, 2020 at 10:34:53PM +0200, Imre Deak wrote:
> > > Split out the PLL parameter->frequency conversion logic for each type of
> > > PLL for symmetry with their corresponding inverse conversion functions.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 269 +++++++++---------
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
> > > 4 files changed, 140 insertions(+), 145 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > index c38addd07e42..17cee6f80d8b 100644
> > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > @@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> > > static void gen11_dsi_get_config(struct intel_encoder *encoder,
> > > struct intel_crtc_state *pipe_config)
> > > {
> > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> > >
> > > intel_dsc_get_config(encoder, pipe_config);
> > >
> > > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> > > - pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
> > > + pipe_config->port_clock = intel_dpll_get_freq(i915,
> > > + pipe_config->shared_dpll);
> >
> > For this one I'm thinking it might be better to pass the pll state
> > instead. That way we could use this function already before we've
> > actually committed the state.
>
> Right, forgot about using this before swapping the new state into
> pll->state. Since pll can't be deducted from the state how about:
>
> int (*get_freq)(struct drm_i915_private *i915,
> const struct intel_shared_dpll *pll,
> const struct intel_dpll_hw_state *hw_state);
>
> ?
I guess we'd still have the slight problem of perhaps not having
selected the pll yet. So bit of a chicken vs. egg. But I guess
that's not something we have to worry about right now.
>
> I can resend with that also making the change adding get_freq a separate
> patch as I originally intended.
>
>
> > We can think about that later though.
> >
> > Patches 1-11 look OK to me:
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Thanks.
>
> >
> > >
> > > pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> > > if (intel_dsi->dual_link)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 5e6f81b140d4..284219da7df8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> > > pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> > > encoder->port);
> > > else
> > > - pipe_config->port_clock = intel_dpll_get_freq(encoder,
> > > - pipe_config);
> > > + pipe_config->port_clock =
> > > + intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
> > >
> > > ddi_dotclock_get(pipe_config);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index ebd55fdaf4cd..b87b4ff5de52 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> > > return true;
> > > }
> > >
> > > -static int hsw_ddi_clock_get(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *pipe_config)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> > > -
> > > - switch (pll->info->id) {
> > > - case DPLL_ID_WRPLL1:
> > > - case DPLL_ID_WRPLL2:
> > > - return hsw_ddi_wrpll_get_freq(dev_priv, pll);
> > > - case DPLL_ID_SPLL:
> > > - return hsw_ddi_spll_get_freq(dev_priv, pll);
> > > - default:
> > > - return hsw_ddi_lcpll_get_freq(dev_priv, pll);
> > > - }
> > > -}
> > > -
> > > static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> > > const struct intel_dpll_hw_state *hw_state)
> > > {
> > > @@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> > > .enable = hsw_ddi_wrpll_enable,
> > > .disable = hsw_ddi_wrpll_disable,
> > > .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> > > + .get_freq = hsw_ddi_wrpll_get_freq,
> > > };
> > >
> > > static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> > > .enable = hsw_ddi_spll_enable,
> > > .disable = hsw_ddi_spll_disable,
> > > .get_hw_state = hsw_ddi_spll_get_hw_state,
> > > + .get_freq = hsw_ddi_spll_get_freq,
> > > };
> > >
> > > static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
> > > @@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> > > .enable = hsw_ddi_lcpll_enable,
> > > .disable = hsw_ddi_lcpll_disable,
> > > .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> > > + .get_freq = hsw_ddi_lcpll_get_freq,
> > > };
> > >
> > > static const struct dpll_info hsw_plls[] = {
> > > @@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > > return true;
> > > }
> > >
> > > -static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
> > > +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > > int ref_clock = 24000;
> > > u32 p0, p1, p2, dco_freq;
> > >
> > > @@ -1670,6 +1658,40 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > > return true;
> > > }
> > >
> > > +static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > +{
> > > + int link_clock = 0;
> > > +
> > > + switch ((pll->state.hw_state.ctrl1 &
> > > + DPLL_CTRL1_LINK_RATE_MASK(0)) >>
> > > + DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
> > > + case DPLL_CTRL1_LINK_RATE_810:
> > > + link_clock = 81000;
> > > + break;
> > > + case DPLL_CTRL1_LINK_RATE_1080:
> > > + link_clock = 108000;
> > > + break;
> > > + case DPLL_CTRL1_LINK_RATE_1350:
> > > + link_clock = 135000;
> > > + break;
> > > + case DPLL_CTRL1_LINK_RATE_1620:
> > > + link_clock = 162000;
> > > + break;
> > > + case DPLL_CTRL1_LINK_RATE_2160:
> > > + link_clock = 216000;
> > > + break;
> > > + case DPLL_CTRL1_LINK_RATE_2700:
> > > + link_clock = 270000;
> > > + break;
> > > + default:
> > > + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> > > + break;
> > > + }
> > > +
> > > + return link_clock * 2;
> > > +}
> > > +
> > > static bool skl_get_dpll(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder)
> > > @@ -1719,50 +1741,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
> > > return true;
> > > }
> > >
> > > -static int skl_ddi_clock_get(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *crtc_state)
> > > +static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> > > - int link_clock;
> > > -
> > > /*
> > > * ctrl1 register is already shifted for each pll, just use 0 to get
> > > * the internal shift for each field
> > > */
> > > - if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
> > > - link_clock = skl_calc_wrpll_link(pll_state);
> > > - } else {
> > > - link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
> > > - link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
> > > -
> > > - switch (link_clock) {
> > > - case DPLL_CTRL1_LINK_RATE_810:
> > > - link_clock = 81000;
> > > - break;
> > > - case DPLL_CTRL1_LINK_RATE_1080:
> > > - link_clock = 108000;
> > > - break;
> > > - case DPLL_CTRL1_LINK_RATE_1350:
> > > - link_clock = 135000;
> > > - break;
> > > - case DPLL_CTRL1_LINK_RATE_1620:
> > > - link_clock = 162000;
> > > - break;
> > > - case DPLL_CTRL1_LINK_RATE_2160:
> > > - link_clock = 216000;
> > > - break;
> > > - case DPLL_CTRL1_LINK_RATE_2700:
> > > - link_clock = 270000;
> > > - break;
> > > - default:
> > > - drm_WARN(encoder->base.dev, 1,
> > > - "Unsupported link rate\n");
> > > - break;
> > > - }
> > > - link_clock *= 2;
> > > - }
> > > -
> > > - return link_clock;
> > > + if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> > > + return skl_ddi_wrpll_get_freq(i915, pll);
> > > + else
> > > + return skl_ddi_lcpll_get_freq(i915, pll);
> > > }
> > >
> > > static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
> > > @@ -1779,12 +1768,14 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> > > .enable = skl_ddi_pll_enable,
> > > .disable = skl_ddi_pll_disable,
> > > .get_hw_state = skl_ddi_pll_get_hw_state,
> > > + .get_freq = skl_ddi_pll_get_freq,
> > > };
> > >
> > > static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> > > .enable = skl_ddi_dpll0_enable,
> > > .disable = skl_ddi_dpll0_disable,
> > > .get_hw_state = skl_ddi_dpll0_get_hw_state,
> > > + .get_freq = skl_ddi_pll_get_freq,
> > > };
> > >
> > > static const struct dpll_info skl_plls[] = {
> > > @@ -2190,11 +2181,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > > return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> > > }
> > >
> > > -static int bxt_ddi_clock_get(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *crtc_state)
> > > +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > - struct intel_dpll_hw_state *pll_state =
> > > - &crtc_state->shared_dpll->state.hw_state;
> > > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > > struct dpll clock;
> > >
> > > clock.m1 = 2;
> > > @@ -2264,6 +2254,7 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> > > .enable = bxt_ddi_pll_enable,
> > > .disable = bxt_ddi_pll_disable,
> > > .get_hw_state = bxt_ddi_pll_get_hw_state,
> > > + .get_freq = bxt_ddi_pll_get_freq,
> > > };
> > >
> > > static const struct dpll_info bxt_plls[] = {
> > > @@ -2608,9 +2599,10 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > > return true;
> > > }
> > >
> > > -static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> > > - struct intel_dpll_hw_state *pll_state)
> > > +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > > u32 p0, p1, p2, dco_freq, ref_clock;
> > >
> > > p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> > > @@ -2709,6 +2701,44 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > > return true;
> > > }
> > >
> > > +static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > +{
> > > + int link_clock = 0;
> > > +
> > > + switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
> > > + case DPLL_CFGCR0_LINK_RATE_810:
> > > + link_clock = 81000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_1080:
> > > + link_clock = 108000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_1350:
> > > + link_clock = 135000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_1620:
> > > + link_clock = 162000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_2160:
> > > + link_clock = 216000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_2700:
> > > + link_clock = 270000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_3240:
> > > + link_clock = 324000;
> > > + break;
> > > + case DPLL_CFGCR0_LINK_RATE_4050:
> > > + link_clock = 405000;
> > > + break;
> > > + default:
> > > + drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> > > + break;
> > > + }
> > > +
> > > + return link_clock * 2;
> > > +}
> > > +
> > > static bool cnl_get_dpll(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder)
> > > @@ -2758,51 +2788,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
> > > return true;
> > > }
> > >
> > > -static int cnl_ddi_clock_get(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *pipe_config)
> > > +static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
> > > - int link_clock;
> > > -
> > > - if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> > > - link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> > > - } else {
> > > - link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
> > > -
> > > - switch (link_clock) {
> > > - case DPLL_CFGCR0_LINK_RATE_810:
> > > - link_clock = 81000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_1080:
> > > - link_clock = 108000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_1350:
> > > - link_clock = 135000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_1620:
> > > - link_clock = 162000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_2160:
> > > - link_clock = 216000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_2700:
> > > - link_clock = 270000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_3240:
> > > - link_clock = 324000;
> > > - break;
> > > - case DPLL_CFGCR0_LINK_RATE_4050:
> > > - link_clock = 405000;
> > > - break;
> > > - default:
> > > - drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
> > > - break;
> > > - }
> > > - link_clock *= 2;
> > > - }
> > > -
> > > - return link_clock;
> > > + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> > > + return cnl_ddi_wrpll_get_freq(i915, pll);
> > > + else
> > > + return cnl_ddi_lcpll_get_freq(i915, pll);
> > > }
> > >
> > > static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> > > @@ -2818,6 +2810,7 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
> > > .enable = cnl_ddi_pll_enable,
> > > .disable = cnl_ddi_pll_disable,
> > > .get_hw_state = cnl_ddi_pll_get_hw_state,
> > > + .get_freq = cnl_ddi_pll_get_freq,
> > > };
> > >
> > > static const struct dpll_info cnl_plls[] = {
> > > @@ -2979,6 +2972,18 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> > > return true;
> > > }
> > >
> > > +static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > +{
> > > + /*
> > > + * The PLL outputs multiple frequencies at the same time, selection is
> > > + * made at DDI clock mux level.
> > > + */
> > > + drm_WARN_ON(&i915->drm, 1);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> > > struct intel_encoder *encoder,
> > > struct intel_dpll_hw_state *pll_state)
> > > @@ -3317,9 +3322,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> > > return true;
> > > }
> > >
> > > -static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> > > - const struct intel_dpll_hw_state *pll_state)
> > > +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > > u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> > > u64 tmp;
> > >
> > > @@ -3388,19 +3394,6 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> > > return tmp;
> > > }
> > >
> > > -static int icl_ddi_clock_get(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *crtc_state)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> > > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > > -
> > > - if (intel_phy_is_combo(dev_priv, phy))
> > > - return cnl_calc_wrpll_link(dev_priv, pll_state);
> > > - else
> > > - return icl_calc_mg_pll_link(dev_priv, pll_state);
> > > -}
> > > -
> > > /**
> > > * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
> > > * @crtc_state: state for the CRTC to select the DPLL for
> > > @@ -3485,6 +3478,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> > > return true;
> > > }
> > >
> > > +static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > +{
> > > + return cnl_ddi_wrpll_get_freq(i915, pll);
> > > +}
> > > +
> > > static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder)
> > > @@ -4141,18 +4140,21 @@ static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> > > .enable = combo_pll_enable,
> > > .disable = combo_pll_disable,
> > > .get_hw_state = combo_pll_get_hw_state,
> > > + .get_freq = icl_ddi_combo_pll_get_freq,
> > > };
> > >
> > > static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> > > .enable = tbt_pll_enable,
> > > .disable = tbt_pll_disable,
> > > .get_hw_state = tbt_pll_get_hw_state,
> > > + .get_freq = icl_ddi_tbt_pll_get_freq,
> > > };
> > >
> > > static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > > .enable = mg_pll_enable,
> > > .disable = mg_pll_disable,
> > > .get_hw_state = mg_pll_get_hw_state,
> > > + .get_freq = icl_ddi_mg_pll_get_freq,
> > > };
> > >
> > > static const struct dpll_info icl_plls[] = {
> > > @@ -4192,6 +4194,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > > .enable = mg_pll_enable,
> > > .disable = mg_pll_disable,
> > > .get_hw_state = dkl_pll_get_hw_state,
> > > + .get_freq = icl_ddi_mg_pll_get_freq,
> > > };
> > >
> > > static const struct dpll_info tgl_plls[] = {
> > > @@ -4348,27 +4351,15 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> > > dpll_mgr->update_active_dpll(state, crtc, encoder);
> > > }
> > >
> > > -int intel_dpll_get_freq(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *crtc_state)
> > > +int intel_dpll_get_freq(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll)
> > > {
> > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > -
> > > - if (INTEL_GEN(i915) >= 11)
> > > - return icl_ddi_clock_get(encoder, crtc_state);
> > > - else if (IS_CANNONLAKE(i915))
> > > - return cnl_ddi_clock_get(encoder, crtc_state);
> > > - else if (IS_GEN9_LP(i915))
> > > - return bxt_ddi_clock_get(encoder, crtc_state);
> > > - else if (IS_GEN9_BC(i915))
> > > - return skl_ddi_clock_get(encoder, crtc_state);
> > > - else if (INTEL_GEN(i915) <= 8)
> > > - hsw_ddi_clock_get(encoder, crtc_state);
> > > + if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
> > > + return 0;
> > >
> > > - drm_WARN_ON(&i915->drm, 1);
> > > - return 0;
> > > + return pll->info->funcs->get_freq(i915, pll);
> > > }
> > >
> > > -
> > > static void readout_dpll_hw_state(struct drm_i915_private *i915,
> > > struct intel_shared_dpll *pll)
> > > {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > index fadc240eccf6..c155935874d4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > @@ -278,6 +278,9 @@ struct intel_shared_dpll_funcs {
> > > bool (*get_hw_state)(struct drm_i915_private *dev_priv,
> > > struct intel_shared_dpll *pll,
> > > struct intel_dpll_hw_state *hw_state);
> > > +
> > > + int (*get_freq)(struct drm_i915_private *i915,
> > > + const struct intel_shared_dpll *pll);
> > > };
> > >
> > > /**
> > > @@ -372,8 +375,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > > void intel_update_active_dpll(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder);
> > > -int intel_dpll_get_freq(struct intel_encoder *encoder,
> > > - struct intel_crtc_state *crtc_state);
> > > +int intel_dpll_get_freq(struct drm_i915_private *,
> > > + const struct intel_shared_dpll *);
> > > void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
> > > void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > > void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > > @@ -384,7 +387,6 @@ void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
> > >
> > > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> > > const struct intel_dpll_hw_state *hw_state);
> > > -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> > > enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> > > bool intel_dpll_is_combophy(enum intel_dpll_id id);
> > >
> > > --
> > > 2.23.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking
2020-02-27 18:13 ` Ville Syrjälä
@ 2020-02-27 19:01 ` Imre Deak
0 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-27 19:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Feb 27, 2020 at 08:13:29PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 26, 2020 at 10:34:55PM +0200, Imre Deak wrote:
> > All platforms using the shared DPLL framework use 3 reference clocks for
> > their DPLLs: SSC, non-SSC and DSI. For a more unified way across
> > platforms store the frequency of these ref clocks as part of the DPLL
> > global state. This also allows us to keep the HW access reading out the
> > ref clock value separate from the DPLL frequency calculation that
> > depends on the ref clock.
> >
> > For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
> > has its own logic for calculating DPLL parameters instead of the shared
> > DPLL framework.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 5 +
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 132 +++++++++++-------
> > drivers/gpu/drm/i915/i915_drv.h | 5 +
> > 3 files changed, 95 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index d2461d7946bf..6675b7e34f0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -920,6 +920,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> > int i;
> >
> > drm_modeset_lock_all(dev);
> > +
> > + seq_printf(m, "PLL refclks: non-SSC: %d kHZ, SSC: %d kHZ\n",
>
> nit: "kHz"
>
> > + dev_priv->dpll.ref_clks.nssc,
> > + dev_priv->dpll.ref_clks.ssc);
> > +
> > for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
> > struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 7e6da58a47c9..44db46782770 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -56,6 +56,7 @@ struct intel_dpll_mgr {
> > void (*update_active_dpll)(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder);
> > + void (*update_ref_clks)(struct drm_i915_private *i915);
> > void (*dump_hw_state)(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state);
> > };
> > @@ -886,16 +887,9 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> >
> > switch (wrpll & WRPLL_REF_MASK) {
> > case WRPLL_REF_SPECIAL_HSW:
> > - /*
> > - * muxed-SSC for BDW.
> > - * non-SSC for non-ULT HSW. Check FUSE_STRAP3
> > - * for the non-SSC reference frequency.
> > - */
> > + /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
> > if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
> > - if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> > - refclk = 24;
> > - else
> > - refclk = 135;
> > + refclk = dev_priv->dpll.ref_clks.nssc;
> > break;
> > }
> > /* fall through */
> > @@ -905,10 +899,10 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > * code only cares about 5% accuracy, and spread is a max of
> > * 0.5% downspread.
> > */
> > - refclk = 135;
> > + refclk = dev_priv->dpll.ref_clks.ssc;
> > break;
> > case WRPLL_REF_LCPLL:
> > - refclk = 2700;
> > + refclk = 2700000;
> > break;
> > default:
> > MISSING_CASE(wrpll);
> > @@ -920,7 +914,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> >
> > /* Convert to KHz, p & r have a fixed point portion */
> > - return (refclk * n * 100) / (p * r) * 2;
> > + return (refclk * n / 10) / (p * r) * 2;
> > }
> >
> > static struct intel_shared_dpll *
> > @@ -1049,6 +1043,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > +static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> > +{
> > + i915->dpll.ref_clks.ssc = 135000;
> > + /* Non-SSC is only used on non-ULT HSW. */
> > + if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> > + i915->dpll.ref_clks.nssc = 24000;
> > + else
> > + i915->dpll.ref_clks.nssc = 135000;
>
> I couldn't remember whether the PCH and CPU SSC references have the same
> frquency. But looks like they do.
Yes, according to bspec for both HSW and BDW.
>
> > +}
> > +
> > static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -1108,6 +1112,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
> > .dpll_info = hsw_plls,
> > .get_dplls = hsw_get_dpll,
> > .put_dplls = intel_put_dpll,
> > + .update_ref_clks = hsw_update_dpll_ref_clks,
> > .dump_hw_state = hsw_dump_hw_state,
> > };
> >
> > @@ -1523,6 +1528,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> >
> > static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > u32 ctrl1, cfgcr1, cfgcr2;
> > struct skl_wrpll_params wrpll_params = { 0, };
> >
> > @@ -1534,7 +1540,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> >
> > ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
> >
> > - if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
> > + if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
> > + i915->dpll.ref_clks.nssc,
> > &wrpll_params))
> > return false;
> >
> > @@ -1561,7 +1568,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > const struct intel_shared_dpll *pll)
> > {
> > const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > - int ref_clock = 24000;
> > + int ref_clock = i915->dpll.ref_clks.nssc;
> > u32 p0, p1, p2, dco_freq;
> >
> > p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
> > @@ -1751,6 +1758,12 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > return skl_ddi_lcpll_get_freq(i915, pll);
> > }
> >
> > +static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
> > +{
> > + /* No SSC ref */
> > + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> > +}
> > +
> > static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -1787,6 +1800,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> > .dpll_info = skl_plls,
> > .get_dplls = skl_get_dpll,
> > .put_dplls = intel_put_dpll,
> > + .update_ref_clks = skl_update_dpll_ref_clks,
> > .dump_hw_state = skl_dump_hw_state,
> > };
> >
> > @@ -2192,7 +2206,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> > clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
> > clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
> >
> > - return chv_calc_dpll_params(100000, &clock);
> > + return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
> > }
> >
> > static bool bxt_get_dpll(struct intel_atomic_state *state,
> > @@ -2228,6 +2242,13 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
> > return true;
> > }
> >
> > +static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
> > +{
> > + i915->dpll.ref_clks.ssc = 100000;
> > + i915->dpll.ref_clks.nssc = 100000;
> > + /* DSI non-SSC ref 19.2MHz */
> > +}
> > +
> > static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -2265,6 +2286,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
> > .dpll_info = bxt_plls,
> > .get_dplls = bxt_get_dpll,
> > .put_dplls = intel_put_dpll,
> > + .update_ref_clks = bxt_update_dpll_ref_clks,
> > .dump_hw_state = bxt_dump_hw_state,
> > };
> >
> > @@ -2508,27 +2530,13 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> > params->dco_fraction = dco & 0x7fff;
> > }
> >
> > -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
> > -{
> > - int ref_clock = dev_priv->cdclk.hw.ref;
> > -
> > - /*
> > - * For ICL+, the spec states: if reference frequency is 38.4,
> > - * use 19.2 because the DPLL automatically divides that by 2.
> > - */
> > - if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
> > - ref_clock = 19200;
> > -
> > - return ref_clock;
> > -}
> > -
> > static bool
> > cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> > struct skl_wrpll_params *wrpll_params)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > u32 afe_clock = crtc_state->port_clock * 5;
> > - u32 ref_clock;
> > + int ref_clock = dev_priv->dpll.ref_clks.nssc;
> > u32 dco_min = 7998000;
> > u32 dco_max = 10000000;
> > u32 dco_mid = (dco_min + dco_max) / 2;
> > @@ -2560,9 +2568,6 @@ cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> > return false;
> >
> > cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> > -
> > - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> > -
> > cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
> > pdiv, qdiv, kdiv);
> >
> > @@ -2596,11 +2601,12 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > -static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > - const struct intel_shared_dpll *pll)
> > +static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > + const struct intel_shared_dpll *pll,
> > + int ref_clock)
> > {
> > const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
> > - u32 p0, p1, p2, dco_freq, ref_clock;
> > + u32 p0, p1, p2, dco_freq;
> >
> > p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> > p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
> > @@ -2639,8 +2645,6 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > break;
> > }
> >
> > - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> > -
> > dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
> > ref_clock;
> >
> > @@ -2653,6 +2657,12 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > return dco_freq / (p0 * p1 * p2 * 5);
> > }
> >
> > +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
> > +}
> > +
> > static bool
> > cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> > {
> > @@ -2794,6 +2804,12 @@ static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> > return cnl_ddi_lcpll_get_freq(i915, pll);
> > }
> >
> > +static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
> > +{
> > + /* No SSC reference */
> > + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> > +}
> > +
> > static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -2821,6 +2837,7 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
> > .dpll_info = cnl_plls,
> > .get_dplls = cnl_get_dpll,
> > .put_dplls = intel_put_dpll,
> > + .update_ref_clks = cnl_update_dpll_ref_clks,
> > .dump_hw_state = cnl_dump_hw_state,
> > };
> >
> > @@ -2916,7 +2933,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > const struct icl_combo_pll_params *params =
> > - dev_priv->cdclk.hw.ref == 24000 ?
> > + dev_priv->dpll.ref_clks.nssc == 24000 ?
> > icl_dp_combo_pll_24MHz_values :
> > icl_dp_combo_pll_19_2MHz_values;
> > int clock = crtc_state->port_clock;
> > @@ -2939,9 +2956,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > - switch (dev_priv->cdclk.hw.ref) {
> > + switch (dev_priv->dpll.ref_clks.nssc) {
> > default:
> > - MISSING_CASE(dev_priv->cdclk.hw.ref);
> > + MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
> > /* fall-through */
> > case 19200:
> > case 38400:
> > @@ -2952,9 +2969,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> > break;
> > }
> > } else {
> > - switch (dev_priv->cdclk.hw.ref) {
> > + switch (dev_priv->dpll.ref_clks.nssc) {
> > default:
> > - MISSING_CASE(dev_priv->cdclk.hw.ref);
> > + MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
> > /* fall-through */
> > case 19200:
> > case 38400:
> > @@ -3118,7 +3135,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> > struct intel_dpll_hw_state *pll_state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - int refclk_khz = dev_priv->cdclk.hw.ref;
> > + int refclk_khz = dev_priv->dpll.ref_clks.nssc;
> > int clock = crtc_state->port_clock;
> > u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> > u32 iref_ndiv, iref_trim, iref_pulse_w;
> > @@ -3326,7 +3343,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> > u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> > u64 tmp;
> >
> > - ref_clock = dev_priv->cdclk.hw.ref;
> > + ref_clock = dev_priv->dpll.ref_clks.nssc;
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
> > @@ -3478,7 +3495,16 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> > static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> > const struct intel_shared_dpll *pll)
> > {
> > - return cnl_ddi_wrpll_get_freq(i915, pll);
> > + int ref_clock = i915->dpll.ref_clks.nssc;
> > +
> > + /*
> > + * For ICL+, the spec states: if reference frequency is 38.4,
> > + * use 19.2 because the DPLL automatically divides that by 2.
> > + */
> > + if (ref_clock == 38400)
> > + ref_clock = 19200;
>
> I was pondering whether it would be better to store the divided ref,
> but I guess we need the original value for some other things, and it's
> really the DPLL in HDMI mode that does the extra /2 for us.
Yes in case the original ref is 38.4MHz, DPLL uses 19.2MHz as reference
both for DP and HDMI, while MG-PLLs use 38.4MHz as reference in that
case. And we store the ref globally not per-PLL.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > +
> > + return __cnl_ddi_wrpll_get_freq(i915, pll, ref_clock);
> > }
> >
> > static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> > @@ -3629,7 +3655,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
> > hw_state->mg_pll_tdc_coldst_bias =
> > intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
> >
> > - if (dev_priv->cdclk.hw.ref == 38400) {
> > + if (dev_priv->dpll.ref_clks.nssc == 38400) {
> > hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
> > hw_state->mg_pll_bias_mask = 0;
> > } else {
> > @@ -4110,6 +4136,12 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
> > icl_pll_disable(dev_priv, pll, enable_reg);
> > }
> >
> > +static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
> > +{
> > + /* No SSC ref */
> > + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> > +}
> > +
> > static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > @@ -4170,6 +4202,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> > .get_dplls = icl_get_dplls,
> > .put_dplls = icl_put_dplls,
> > .update_active_dpll = icl_update_active_dpll,
> > + .update_ref_clks = icl_update_dpll_ref_clks,
> > .dump_hw_state = icl_dump_hw_state,
> > };
> >
> > @@ -4184,6 +4217,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
> > .dpll_info = ehl_plls,
> > .get_dplls = icl_get_dplls,
> > .put_dplls = icl_put_dplls,
> > + .update_ref_clks = icl_update_dpll_ref_clks,
> > .dump_hw_state = icl_dump_hw_state,
> > };
> >
> > @@ -4212,6 +4246,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
> > .get_dplls = icl_get_dplls,
> > .put_dplls = icl_put_dplls,
> > .update_active_dpll = icl_update_active_dpll,
> > + .update_ref_clks = icl_update_dpll_ref_clks,
> > .dump_hw_state = icl_dump_hw_state,
> > };
> >
> > @@ -4390,6 +4425,9 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
> > {
> > int i;
> >
> > + if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
> > + i915->dpll.mgr->update_ref_clks(i915);
> > +
> > for (i = 0; i < i915->dpll.num_shared_dpll; i++)
> > readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index fe4eefc5e7e6..49ee3bde08f5 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1059,6 +1059,11 @@ struct drm_i915_private {
> > int num_shared_dpll;
> > struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> > const struct intel_dpll_mgr *mgr;
> > +
> > + struct {
> > + int nssc;
> > + int ssc;
> > + } ref_clks;
> > } dpll;
> >
> > struct list_head global_obj_list;
> > --
> > 2.23.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL output/refclock tracking
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (15 preceding siblings ...)
2020-02-27 4:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-28 0:22 ` Patchwork
2020-02-28 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2) Patchwork
` (4 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-28 0:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking
URL : https://patchwork.freedesktop.org/series/73977/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8010_full -> Patchwork_16725_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16725_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16725_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16725_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_3d:
- shard-iclb: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb3/igt@kms_3d.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@kms_3d.html
* igt@kms_hdmi_inject@inject-4k:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@kms_hdmi_inject@inject-4k.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb7/igt@kms_hdmi_inject@inject-4k.html
* igt@runner@aborted:
- shard-tglb: NOTRUN -> ([FAIL][5], [FAIL][6], [FAIL][7])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-tglb1/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-tglb5/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-tglb2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_16725_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#679])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb2/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb5/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
- shard-iclb: [PASS][10] -> [INCOMPLETE][11] ([i915#1239])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb2/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb5/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
* igt@gem_exec_schedule@implicit-both-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([i915#677])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb7/igt@gem_exec_schedule@implicit-both-bsd.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd.html
* igt@gem_exec_schedule@implicit-both-bsd2:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276] / [i915#677]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd2.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#112146]) +6 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#118] / [i915#95])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk3/igt@gem_exec_whisper@basic-fds-all.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk7/igt@gem_exec_whisper@basic-fds-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#716])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#413])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb4/igt@i915_pm_rps@waitboost.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb4/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#407])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk7/igt@kms_flip@2x-modeset-vs-vblank-race.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-glk: [PASS][28] -> [FAIL][29] ([i915#49])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][30] -> [DMESG-WARN][31] ([i915#180]) +5 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdmi_inject@inject-4k:
- shard-tglb: [PASS][32] -> [INCOMPLETE][33] ([i915#449]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-tglb8/igt@kms_hdmi_inject@inject-4k.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-tglb1/igt@kms_hdmi_inject@inject-4k.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#1188]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][36] -> [FAIL][37] ([fdo#108145])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#899])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-y.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][40] -> [SKIP][41] ([fdo#109441]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf_pmu@busy-double-start-vcs1:
- shard-iclb: [PASS][42] -> [SKIP][43] ([fdo#112080]) +9 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@perf_pmu@busy-double-start-vcs1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@perf_pmu@busy-double-start-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][44] -> [SKIP][45] ([fdo#109276]) +18 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb4/igt@prime_busy@hang-bsd2.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb3/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][46] ([fdo#112080]) -> [PASS][47] +11 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb7/igt@gem_busy@busy-vcs1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb1/igt@gem_busy@busy-vcs1.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][48] ([fdo#110854]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb6/igt@gem_exec_balancer@smoke.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb1/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][50] ([fdo#109276] / [i915#677]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb7/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][52] ([i915#677]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][54] ([fdo#112146]) -> [PASS][55] +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-iclb: [INCOMPLETE][56] ([i915#1120]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb4/igt@gem_exec_whisper@basic-queues-forked.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb3/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][58] ([i915#644]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-skl: [FAIL][60] ([i915#644]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-iclb: [FAIL][62] ([i915#644]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb4/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [DMESG-WARN][64] ([i915#180]) -> [PASS][65] +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-kbl6/igt@i915_suspend@sysfs-reader.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-kbl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][66] ([i915#79]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: [FAIL][68] ([i915#79]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
- shard-glk: [FAIL][70] ([i915#79]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][72] ([i915#1188]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][74] ([fdo#108145]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][76] ([fdo#108145] / [i915#265]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][78] ([fdo#109441]) -> [PASS][79] +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][80] ([fdo#109276]) -> [PASS][81] +19 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][82] ([IGT#28]) -> [SKIP][83] ([fdo#112080])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@kms_content_protection@atomic:
- shard-kbl: [TIMEOUT][84] ([i915#1319] / [i915#727]) -> [TIMEOUT][85] ([i915#1319]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-kbl2/igt@kms_content_protection@atomic.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-kbl4/igt@kms_content_protection@atomic.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][86] ([i915#1226]) -> [SKIP][87] ([fdo#109349])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1333]: https://gitlab.freedesktop.org/drm/intel/issues/1333
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#449]: https://gitlab.freedesktop.org/drm/intel/issues/449
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#727]: https://gitlab.freedesktop.org/drm/intel/issues/727
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8010 -> Patchwork_16725
CI-20190529: 20190529
CI_DRM_8010: 97bbec4d80df1c6573fc7063ad830e8beefe07c8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5471: 668afe52887a164ee6a12fd1c898bc1c9086cf3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16725: a5e019011c6b18582d2c4722209a2d8fd5b0ed38 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16725/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [PATCH v2 13/13] drm/i915: Unify the DPLL ref clock frequency tracking
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
2020-02-27 18:13 ` Ville Syrjälä
@ 2020-02-28 15:33 ` Imre Deak
1 sibling, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-02-28 15:33 UTC (permalink / raw)
To: intel-gfx
All platforms using the shared DPLL framework use 3 reference clocks for
their DPLLs: SSC, non-SSC and DSI. For a more unified way across
platforms store the frequency of these ref clocks as part of the DPLL
global state. This also allows us to keep the HW access reading out the
ref clock value separate from the DPLL frequency calculation that
depends on the ref clock.
For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
has its own logic for calculating DPLL parameters instead of the shared
DPLL framework.
v2:
- Apply the ICL combo PHY PLL ref_clock/2 adjustment during the
frequency->PLL param conversion direction as well. (CI shards)
- s/kHZ/kHz/ (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 5 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 175 ++++++++++++------
drivers/gpu/drm/i915/i915_drv.h | 5 +
3 files changed, 129 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d2461d7946bf..1e6eb7f2f72d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -920,6 +920,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
int i;
drm_modeset_lock_all(dev);
+
+ seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
+ dev_priv->dpll.ref_clks.nssc,
+ dev_priv->dpll.ref_clks.ssc);
+
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7e6da58a47c9..76d14486b3a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -56,6 +56,7 @@ struct intel_dpll_mgr {
void (*update_active_dpll)(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
+ void (*update_ref_clks)(struct drm_i915_private *i915);
void (*dump_hw_state)(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state);
};
@@ -886,16 +887,9 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
- /*
- * muxed-SSC for BDW.
- * non-SSC for non-ULT HSW. Check FUSE_STRAP3
- * for the non-SSC reference frequency.
- */
+ /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
- if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- refclk = 24;
- else
- refclk = 135;
+ refclk = dev_priv->dpll.ref_clks.nssc;
break;
}
/* fall through */
@@ -905,10 +899,10 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = 135;
+ refclk = dev_priv->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
- refclk = 2700;
+ refclk = 2700000;
break;
default:
MISSING_CASE(wrpll);
@@ -920,7 +914,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
/* Convert to KHz, p & r have a fixed point portion */
- return (refclk * n * 100) / (p * r) * 2;
+ return (refclk * n / 10) / (p * r) * 2;
}
static struct intel_shared_dpll *
@@ -1049,6 +1043,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
return true;
}
+static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ i915->dpll.ref_clks.ssc = 135000;
+ /* Non-SSC is only used on non-ULT HSW. */
+ if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
+ i915->dpll.ref_clks.nssc = 24000;
+ else
+ i915->dpll.ref_clks.nssc = 135000;
+}
+
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1108,6 +1112,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
.dpll_info = hsw_plls,
.get_dplls = hsw_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = hsw_update_dpll_ref_clks,
.dump_hw_state = hsw_dump_hw_state,
};
@@ -1523,6 +1528,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
u32 ctrl1, cfgcr1, cfgcr2;
struct skl_wrpll_params wrpll_params = { 0, };
@@ -1534,7 +1540,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, 24000,
+ if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
+ i915->dpll.ref_clks.nssc,
&wrpll_params))
return false;
@@ -1561,7 +1568,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll)
{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
- int ref_clock = 24000;
+ int ref_clock = i915->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1751,6 +1758,12 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
return skl_ddi_lcpll_get_freq(i915, pll);
}
+static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC ref */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -1787,6 +1800,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.dpll_info = skl_plls,
.get_dplls = skl_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = skl_update_dpll_ref_clks,
.dump_hw_state = skl_dump_hw_state,
};
@@ -2192,7 +2206,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
- return chv_calc_dpll_params(100000, &clock);
+ return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
}
static bool bxt_get_dpll(struct intel_atomic_state *state,
@@ -2228,6 +2242,13 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
return true;
}
+static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ i915->dpll.ref_clks.ssc = 100000;
+ i915->dpll.ref_clks.nssc = 100000;
+ /* DSI non-SSC ref 19.2MHz */
+}
+
static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -2265,6 +2286,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
.dpll_info = bxt_plls,
.get_dplls = bxt_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = bxt_update_dpll_ref_clks,
.dump_hw_state = bxt_dump_hw_state,
};
@@ -2508,27 +2530,12 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
params->dco_fraction = dco & 0x7fff;
}
-int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
-{
- int ref_clock = dev_priv->cdclk.hw.ref;
-
- /*
- * For ICL+, the spec states: if reference frequency is 38.4,
- * use 19.2 because the DPLL automatically divides that by 2.
- */
- if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
- ref_clock = 19200;
-
- return ref_clock;
-}
-
static bool
-cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
- struct skl_wrpll_params *wrpll_params)
+__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
+ struct skl_wrpll_params *wrpll_params,
+ int ref_clock)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 afe_clock = crtc_state->port_clock * 5;
- u32 ref_clock;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
@@ -2560,15 +2567,22 @@ cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
return false;
cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
-
- ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
-
cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
pdiv, qdiv, kdiv);
return true;
}
+static bool
+cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
+ struct skl_wrpll_params *wrpll_params)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
+ i915->dpll.ref_clks.nssc);
+}
+
static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
u32 cfgcr0, cfgcr1;
@@ -2596,11 +2610,12 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
-static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
- const struct intel_shared_dpll *pll)
+static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+ const struct intel_shared_dpll *pll,
+ int ref_clock)
{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
- u32 p0, p1, p2, dco_freq, ref_clock;
+ u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
@@ -2639,8 +2654,6 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
break;
}
- ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
-
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
ref_clock;
@@ -2653,6 +2666,12 @@ static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
return dco_freq / (p0 * p1 * p2 * 5);
}
+static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
+}
+
static bool
cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
@@ -2794,6 +2813,12 @@ static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
return cnl_ddi_lcpll_get_freq(i915, pll);
}
+static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC reference */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -2821,6 +2846,7 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
.dpll_info = cnl_plls,
.get_dplls = cnl_get_dpll,
.put_dplls = intel_put_dpll,
+ .update_ref_clks = cnl_update_dpll_ref_clks,
.dump_hw_state = cnl_dump_hw_state,
};
@@ -2916,7 +2942,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
- dev_priv->cdclk.hw.ref == 24000 ?
+ dev_priv->dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
@@ -2939,9 +2965,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (INTEL_GEN(dev_priv) >= 12) {
- switch (dev_priv->cdclk.hw.ref) {
+ switch (dev_priv->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->cdclk.hw.ref);
+ MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
/* fall-through */
case 19200:
case 38400:
@@ -2952,9 +2978,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
break;
}
} else {
- switch (dev_priv->cdclk.hw.ref) {
+ switch (dev_priv->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->cdclk.hw.ref);
+ MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
/* fall-through */
case 19200:
case 38400:
@@ -2981,6 +3007,37 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
return 0;
}
+static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
+{
+ int ref_clock = i915->dpll.ref_clks.nssc;
+
+ /*
+ * For ICL+, the spec states: if reference frequency is 38.4,
+ * use 19.2 because the DPLL automatically divides that by 2.
+ */
+ if (ref_clock == 38400)
+ ref_clock = 19200;
+
+ return ref_clock;
+}
+
+static bool
+icl_calc_wrpll(struct intel_crtc_state *crtc_state,
+ struct skl_wrpll_params *wrpll_params)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
+ icl_wrpll_ref_clock(i915));
+}
+
+static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ return __cnl_ddi_wrpll_get_freq(i915, pll,
+ icl_wrpll_ref_clock(i915));
+}
+
static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder,
struct intel_dpll_hw_state *pll_state)
@@ -2995,7 +3052,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
- ret = cnl_ddi_calculate_wrpll(crtc_state, &pll_params);
+ ret = icl_calc_wrpll(crtc_state, &pll_params);
else
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
@@ -3118,7 +3175,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int refclk_khz = dev_priv->cdclk.hw.ref;
+ int refclk_khz = dev_priv->dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3326,7 +3383,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = dev_priv->cdclk.hw.ref;
+ ref_clock = dev_priv->dpll.ref_clks.nssc;
if (INTEL_GEN(dev_priv) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
@@ -3475,12 +3532,6 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return true;
}
-static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
- const struct intel_shared_dpll *pll)
-{
- return cnl_ddi_wrpll_get_freq(i915, pll);
-}
-
static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -3629,7 +3680,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
- if (dev_priv->cdclk.hw.ref == 38400) {
+ if (dev_priv->dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
hw_state->mg_pll_bias_mask = 0;
} else {
@@ -4110,6 +4161,12 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
icl_pll_disable(dev_priv, pll, enable_reg);
}
+static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
+{
+ /* No SSC ref */
+ i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+}
+
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
@@ -4170,6 +4227,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4184,6 +4242,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dpll_info = ehl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4212,6 +4271,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
+ .update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
};
@@ -4390,6 +4450,9 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
int i;
+ if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
+ i915->dpll.mgr->update_ref_clks(i915);
+
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe4eefc5e7e6..49ee3bde08f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1059,6 +1059,11 @@ struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
+
+ struct {
+ int nssc;
+ int ssc;
+ } ref_clks;
} dpll;
struct list_head global_obj_list;
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (16 preceding siblings ...)
2020-02-28 0:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-02-28 17:49 ` Patchwork
2020-02-28 17:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-28 17:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
19fd5dd4fc02 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
4a956a747f48 drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
a46550bb063a drm/i915: Keep the global DPLL state in a DPLL specific struct
-:311: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#311: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:3835:
+ BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
-:400: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#400: FILE: drivers/gpu/drm/i915/i915_drv.h:1057:
+ struct mutex lock;
total: 0 errors, 1 warnings, 1 checks, 339 lines checked
b87324c7e4d4 drm/i915: Move the DPLL vfunc inits after the func defines
e7b63db4be61 drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
16cbb5c45f38 drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
-:607: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_810MHz>
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+ if (pll == SPLL_FREQ_810MHz)
-:607: CHECK:BRACES: braces {} should be used on all arms of this statement
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+ if (pll == SPLL_FREQ_810MHz)
[...]
+ else if (pll == SPLL_FREQ_1350MHz)
[...]
+ else if (pll == SPLL_FREQ_2700MHz)
[...]
+ else {
[...]
-:609: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#609: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1026:
+ else if (pll == SPLL_FREQ_1350MHz)
-:611: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_2700MHz>
#611: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1028:
+ else if (pll == SPLL_FREQ_2700MHz)
-:613: CHECK:BRACES: Unbalanced braces around else statement
#613: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1030:
+ else {
-:645: CHECK:LINE_SPACING: Please don't use multiple blank lines
#645: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1558:
+
+
-:787: CHECK:LINE_SPACING: Please don't use multiple blank lines
#787: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2593:
+
+
-:1001: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1001: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4339:
+
+
total: 0 errors, 0 warnings, 8 checks, 968 lines checked
12c8e6996ea5 drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
d44f7bddc44c drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
9b1ae235617a drm/i915/hsw: Split out the SPLL parameter calculation
-:29: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#29: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:969:
+ crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
total: 0 errors, 0 warnings, 1 checks, 51 lines checked
7c9bf0760704 drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
dcf2a96e2ea6 drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
-:523: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_i915_private *' should also have an identifier name
#523: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,
-:523: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct intel_shared_dpll *' should also have an identifier name
#523: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,
total: 0 errors, 2 warnings, 0 checks, 479 lines checked
7766f980fe46 drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
8ab21b812217 drm/i915: Unify the DPLL ref clock frequency tracking
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (17 preceding siblings ...)
2020-02-28 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2) Patchwork
@ 2020-02-28 17:55 ` Patchwork
2020-02-28 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-28 17:55 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
URL : https://patchwork.freedesktop.org/series/73977/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Fix bounds check in intel_get_shared_dpll_id()
Okay!
Commit: drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
Okay!
Commit: drm/i915: Keep the global DPLL state in a DPLL specific struct
Okay!
Commit: drm/i915: Move the DPLL vfunc inits after the func defines
Okay!
Commit: drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
Okay!
Commit: drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
Okay!
Commit: drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
Okay!
Commit: drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
Okay!
Commit: drm/i915/hsw: Split out the SPLL parameter calculation
Okay!
Commit: drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
Okay!
Commit: drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2514:5: warning: symbol 'cnl_hdmi_pll_ref_clock' was not declared. Should it be static?
Commit: drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
Okay!
Commit: drm/i915: Unify the DPLL ref clock frequency tracking
-O:drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2511:5: warning: symbol 'cnl_hdmi_pll_ref_clock' was not declared. Should it be static?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (18 preceding siblings ...)
2020-02-28 17:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-02-28 18:40 ` Patchwork
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
21 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2020-02-28 18:40 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
URL : https://patchwork.freedesktop.org/series/73977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8032 -> Patchwork_16764
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
Known issues
------------
Here are the changes found in Patchwork_16764 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#151])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [PASS][3] -> [DMESG-FAIL][4] ([i915#877])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@prime_self_import@basic-llseek-bad:
- fi-tgl-y: [DMESG-WARN][7] ([CI#94] / [i915#402]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][9] ([i915#704]) -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [FAIL][12] ([fdo#111407])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
[i915#998]: https://gitlab.freedesktop.org/drm/intel/issues/998
Participating hosts (47 -> 44)
------------------------------
Additional (4): fi-byt-j1900 fi-bdw-5557u fi-bsw-kefka fi-kbl-r
Missing (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8032 -> Patchwork_16764
CI-20190529: 20190529
CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8ab21b812217 drm/i915: Unify the DPLL ref clock frequency tracking
7766f980fe46 drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
dcf2a96e2ea6 drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
7c9bf0760704 drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
9b1ae235617a drm/i915/hsw: Split out the SPLL parameter calculation
d44f7bddc44c drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
12c8e6996ea5 drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
16cbb5c45f38 drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
e7b63db4be61 drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
b87324c7e4d4 drm/i915: Move the DPLL vfunc inits after the func defines
a46550bb063a drm/i915: Keep the global DPLL state in a DPLL specific struct
4a956a747f48 drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
19fd5dd4fc02 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (19 preceding siblings ...)
2020-02-28 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-01 14:06 ` Patchwork
2020-03-02 13:31 ` Imre Deak
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
21 siblings, 1 reply; 33+ messages in thread
From: Patchwork @ 2020-03-01 14:06 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
URL : https://patchwork.freedesktop.org/series/73977/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8032_full -> Patchwork_16764_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16764_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16764_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16764_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: NOTRUN -> [TIMEOUT][1] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@perf@stress-open-close}:
- shard-hsw: [INCOMPLETE][2] ([i915#61]) -> [TIMEOUT][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw6/igt@perf@stress-open-close.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@perf@stress-open-close.html
Known issues
------------
Here are the changes found in Patchwork_16764_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#1340])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@gem_ctx_persistence@close-replace-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110841])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112146]) +5 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb4/igt@gem_exec_balancer@smoke.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276] / [i915#677]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276]) +15 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([i915#677]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#750])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-tglb2/igt@gem_exec_whisper@basic-queues-forked.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-tglb7/igt@gem_exec_whisper@basic-queues-forked.html
- shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([i915#1120])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_wait@busy-vcs1:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112080]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_wait@busy-vcs1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_wait@busy-vcs1.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#454])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][26] -> [FAIL][27] ([i915#413])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@i915_pm_rps@waitboost.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#72])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk8/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#69])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#79])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][36] -> [FAIL][37] ([i915#79])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#221])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-glk: [PASS][40] -> [FAIL][41] ([i915#34])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#34])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#1188])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [i915#265]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][48] -> [FAIL][49] ([i915#899])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-skl: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl3/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109642] / [fdo#111068])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][54] -> [FAIL][55] ([i915#173])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@no_drrs.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-iclb: [INCOMPLETE][60] ([i915#1291]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb7/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][62] ([fdo#112080]) -> [PASS][63] +17 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@implicit-write-read-bsd2:
- shard-iclb: [SKIP][64] ([fdo#109276] / [i915#677]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd2.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd2.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][66] ([i915#677]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][68] ([fdo#112146]) -> [PASS][69] +7 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-kbl: [FAIL][70] ([i915#644]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
- shard-hsw: [TIMEOUT][72] -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][74] ([IGT#5]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [INCOMPLETE][76] ([fdo#103665]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][78] ([i915#1188]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][80] ([i915#180]) -> [PASS][81] +5 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-top-left-pipe-a-planes:
- shard-skl: [FAIL][84] -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][86] ([fdo#108145]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [FAIL][88] ([i915#899]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-skl: [DMESG-WARN][90] ([IGT#6]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][92] ([fdo#109441]) -> [PASS][93] +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][94] ([fdo#109276]) -> [PASS][95] +21 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@prime_busy@hang-bsd2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][96] ([fdo#112080]) -> [FAIL][97] ([IGT#28])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-snb: [SKIP][98] ([fdo#109271]) -> [INCOMPLETE][99] ([i915#82])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-snb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-snb6/igt@i915_pm_rpm@debugfs-forcewake-user.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
[i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8032 -> Patchwork_16764
CI-20190529: 20190529
CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-03-02 13:31 ` Imre Deak
2020-03-02 14:30 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 33+ messages in thread
From: Imre Deak @ 2020-03-02 13:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Lakshminarayana Vudum
On Sun, Mar 01, 2020 at 02:06:00PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
> URL : https://patchwork.freedesktop.org/series/73977/
> State : failure
>
> [...]
> #### Possible regressions ####
>
> * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
> - shard-hsw: NOTRUN -> [TIMEOUT][1] +3 similar issues
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
Here perf/stress-open-close failed already, before kms_cursor_legacy and
tests afterwards fail. It looks like
https://gitlab.freedesktop.org/drm/intel/issues/1356
<6>[ 306.955929] perf S12616 2283 1117 0x00000000
<4>[ 306.955932] Call Trace:
<4>[ 306.955935] ? __schedule+0x2e5/0x800
<4>[ 306.955940] schedule+0x37/0xe0
<4>[ 306.955942] schedule_timeout+0x225/0x3f0
<4>[ 306.955945] ? find_held_lock+0x2d/0x90
<4>[ 306.955983] ? i915_request_wait+0x175/0x880 [i915]
<4>[ 306.955988] io_schedule_timeout+0x14/0x40
<4>[ 306.956026] i915_request_wait+0x1ce/0x880 [i915]
<4>[ 306.956066] ? irq_execute_cb+0x20/0x20 [i915]
<4>[ 306.956109] wait_for_space+0x114/0x290 [i915]
<4>[ 306.956142] intel_ring_begin+0x229/0x490 [i915]
<4>[ 306.956175] gen7_render_ring_flush+0xe4/0x300 [i915]
<4>[ 306.956207] ring_request_alloc+0x75/0xca0 [i915]
<4>[ 306.956246] __i915_request_create+0x253/0x600 [i915]
<4>[ 306.956284] i915_request_create+0x8c/0x1d0 [i915]
<4>[ 306.956320] emit_oa_config+0x46c/0x9c0 [i915]
<4>[ 306.956357] i915_oa_stream_init.isra.41+0x794/0x11f0 [i915]
<4>[ 306.956361] ? kmem_cache_alloc_trace+0x2a6/0x2d0
<4>[ 306.956398] i915_perf_open_ioctl+0x30a/0x760 [i915]
<4>[ 306.956457] ? i915_oa_init_reg_state+0x160/0x160 [i915]
<4>[ 306.956462] drm_ioctl_kernel+0xad/0xf0
<4>[ 306.956466] drm_ioctl+0x2e1/0x390
<4>[ 306.956503] ? i915_oa_init_reg_state+0x160/0x160 [i915]
<4>[ 306.956506] ? find_held_lock+0x2d/0x90
<4>[ 306.956510] ? task_work_run+0x6e/0xb0
<4>[ 306.956514] ? _raw_spin_unlock_irq+0x1f/0x40
<4>[ 306.956518] ksys_ioctl+0x7b/0x90
<4>[ 306.956521] __x64_sys_ioctl+0x11/0x20
<4>[ 306.956524] do_syscall_64+0x4f/0x220
<4>[ 306.956526] entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 306.956528] RIP: 0033:0x7f6a68ecf5d7
<4>[ 306.956531] Code: Bad RIP value.
<4>[ 306.956533] RSP: 002b:00007ffcdb611258 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
<4>[ 306.956535] RAX: ffffffffffffffda RBX: 0000000000000005 RCX: 00007f6a68ecf5d7
<4>[ 306.956537] RDX: 00007ffcdb611540 RSI: 0000000040106476 RDI: 0000000000000005
<4>[ 306.956538] RBP: 00007ffcdb611540 R08: 000000000004bdd6 R09: 00000000000000bb
<4>[ 306.956540] R10: 00000000de3f2d42 R11: 0000000000000246 R12: 0000000040106476
<4>[ 306.956541] R13: 0000000000000005 R14: 0000000000000000 R15: 0000000000000000
<6>[ 306.956548] perf S13288 2284 2283 0x00000000
<4>[ 306.956552] Call Trace:
<4>[ 306.956556] ? __schedule+0x2e5/0x800
<4>[ 306.956572] schedule+0x37/0xe0
<4>[ 306.956574] schedule_timeout+0x225/0x3f0
<4>[ 306.956577] ? find_held_lock+0x2d/0x90
<4>[ 306.956616] ? i915_request_wait+0x175/0x880 [i915]
<4>[ 306.956621] io_schedule_timeout+0x14/0x40
<4>[ 306.956669] i915_request_wait+0x1ce/0x880 [i915]
<4>[ 306.956708] ? irq_execute_cb+0x20/0x20 [i915]
<4>[ 306.956746] i915_gem_object_wait+0x27c/0x540 [i915]
<4>[ 306.956792] ? i915_gem_object_set_to_cpu_domain+0xd1/0x150 [i915]
<4>[ 306.956825] i915_gem_set_domain_ioctl+0x143/0x500 [i915]
<4>[ 306.956859] ? i915_gem_object_set_to_cpu_domain+0x150/0x150 [i915]
<4>[ 306.956862] drm_ioctl_kernel+0xad/0xf0
<4>[ 306.956866] drm_ioctl+0x2e1/0x390
<4>[ 306.956901] ? i915_gem_object_set_to_cpu_domain+0x150/0x150 [i915]
<4>[ 306.956909] ksys_ioctl+0x7b/0x90
<4>[ 306.956912] __x64_sys_ioctl+0x11/0x20
<4>[ 306.956914] do_syscall_64+0x4f/0x220
<4>[ 306.956916] entry_SYSCALL_64_after_hwframe+0x49/0xbe
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@perf@stress-open-close}:
> - shard-hsw: [INCOMPLETE][2] ([i915#61]) -> [TIMEOUT][3]
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw6/igt@perf@stress-open-close.html
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@perf@stress-open-close.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_16764_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#1340])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@gem_ctx_persistence@close-replace-race.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_ctx_shared@exec-single-timeline-bsd:
> - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110841])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
>
> * igt@gem_exec_async@concurrent-writes-bsd:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112146]) +5 similar issues
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@implicit-both-bsd1:
> - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276] / [i915#677]) +1 similar issue
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html
>
> * igt@gem_exec_schedule@independent-bsd2:
> - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276]) +15 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
>
> * igt@gem_exec_schedule@pi-distinct-iova-bsd:
> - shard-iclb: [PASS][16] -> [SKIP][17] ([i915#677]) +2 similar issues
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
>
> * igt@gem_exec_whisper@basic-queues-forked:
> - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#750])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-tglb2/igt@gem_exec_whisper@basic-queues-forked.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-tglb7/igt@gem_exec_whisper@basic-queues-forked.html
> - shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([i915#1120])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_whisper@basic-queues-forked.html
>
> * igt@gem_wait@busy-vcs1:
> - shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112080]) +3 similar issues
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_wait@busy-vcs1.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_wait@busy-vcs1.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-iclb: [PASS][24] -> [FAIL][25] ([i915#454])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_pm_rps@waitboost:
> - shard-iclb: [PASS][26] -> [FAIL][27] ([i915#413])
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@i915_pm_rps@waitboost.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@i915_pm_rps@waitboost.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +5 similar issues
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
> - shard-glk: [PASS][30] -> [FAIL][31] ([i915#72])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk8/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
>
> * igt@kms_fbcon_fbt@psr-suspend:
> - shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#69])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [PASS][34] -> [FAIL][35] ([i915#79])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-glk: [PASS][36] -> [FAIL][37] ([i915#79])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#221])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible:
> - shard-glk: [PASS][40] -> [FAIL][41] ([i915#34])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> - shard-skl: [PASS][42] -> [FAIL][43] ([i915#34])
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [PASS][44] -> [FAIL][45] ([i915#1188])
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [i915#265]) +1 similar issue
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-glk: [PASS][48] -> [FAIL][49] ([i915#899])
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
> - shard-skl: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl3/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
>
> * igt@kms_psr2_su@frontbuffer:
> - shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109642] / [fdo#111068])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
>
> * igt@kms_psr@no_drrs:
> - shard-iclb: [PASS][54] -> [FAIL][55] ([i915#173])
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@no_drrs.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr@no_drrs.html
>
> * igt@kms_psr@psr2_primary_mmap_cpu:
> - shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441]) +2 similar issues
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +5 similar issues
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-iclb: [INCOMPLETE][60] ([i915#1291]) -> [PASS][61]
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb7/igt@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_exec_parallel@vcs1-fds:
> - shard-iclb: [SKIP][62] ([fdo#112080]) -> [PASS][63] +17 similar issues
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
>
> * igt@gem_exec_schedule@implicit-write-read-bsd2:
> - shard-iclb: [SKIP][64] ([fdo#109276] / [i915#677]) -> [PASS][65]
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd2.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd2.html
>
> * igt@gem_exec_schedule@pi-common-bsd:
> - shard-iclb: [SKIP][66] ([i915#677]) -> [PASS][67] +1 similar issue
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [SKIP][68] ([fdo#112146]) -> [PASS][69] +7 similar issues
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_ppgtt@flink-and-close-vma-leak:
> - shard-kbl: [FAIL][70] ([i915#644]) -> [PASS][71]
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
>
> * igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
> - shard-hsw: [TIMEOUT][72] -> [PASS][73]
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
> - shard-skl: [FAIL][74] ([IGT#5]) -> [PASS][75]
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-kbl: [INCOMPLETE][76] ([fdo#103665]) -> [PASS][77]
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_hdr@bpc-switch-suspend:
> - shard-skl: [FAIL][78] ([i915#1188]) -> [PASS][79]
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
> - shard-kbl: [DMESG-WARN][80] ([i915#180]) -> [PASS][81] +5 similar issues
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-apl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83]
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
> - shard-skl: [FAIL][84] -> [PASS][85]
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
> - shard-skl: [FAIL][86] ([fdo#108145]) -> [PASS][87] +1 similar issue
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-glk: [FAIL][88] ([i915#899]) -> [PASS][89]
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-y.html
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> - shard-skl: [DMESG-WARN][90] ([IGT#6]) -> [PASS][91]
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: [SKIP][92] ([fdo#109441]) -> [PASS][93] +4 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@prime_busy@hang-bsd2:
> - shard-iclb: [SKIP][94] ([fdo#109276]) -> [PASS][95] +21 similar issues
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@prime_busy@hang-bsd2.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@prime_busy@hang-bsd2.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [SKIP][96] ([fdo#112080]) -> [FAIL][97] ([IGT#28])
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@i915_pm_rpm@debugfs-forcewake-user:
> - shard-snb: [SKIP][98] ([fdo#109271]) -> [INCOMPLETE][99] ([i915#82])
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-snb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-snb6/igt@i915_pm_rpm@debugfs-forcewake-user.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
> [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
> [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
> [i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
> [i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
> [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
> [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
> [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_8032 -> Patchwork_16764
>
> CI-20190529: 20190529
> CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
` (20 preceding siblings ...)
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-03-02 13:56 ` Patchwork
2020-03-02 17:39 ` Imre Deak
21 siblings, 1 reply; 33+ messages in thread
From: Patchwork @ 2020-03-02 13:56 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
URL : https://patchwork.freedesktop.org/series/73977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8032_full -> Patchwork_16764_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16764_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-skl: [PASS][1] -> [TIMEOUT][2] ([i915#1340])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@gem_ctx_persistence@close-replace-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb4/igt@gem_exec_balancer@smoke.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([i915#677]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#750])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-tglb2/igt@gem_exec_whisper@basic-queues-forked.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-tglb7/igt@gem_exec_whisper@basic-queues-forked.html
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#1120])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_wait@busy-vcs1:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112080]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_wait@busy-vcs1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_wait@busy-vcs1.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#454])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#413])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@i915_pm_rps@waitboost.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#72])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk8/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#69])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#79])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#79])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][35] -> [INCOMPLETE][36] ([i915#221])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#34])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#34])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#1188])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145] / [i915#265]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][45] -> [FAIL][46] ([i915#899])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-skl: [PASS][47] -> [DMESG-WARN][48] ([IGT#6])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl3/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109642] / [fdo#111068])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][51] -> [FAIL][52] ([i915#173])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@no_drrs.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109441]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-iclb: [INCOMPLETE][57] ([i915#1291]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb7/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][59] ([fdo#112080]) -> [PASS][60] +17 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@implicit-write-read-bsd2:
- shard-iclb: [SKIP][61] ([fdo#109276] / [i915#677]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd2.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd2.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][63] ([i915#677]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][65] ([fdo#112146]) -> [PASS][66] +7 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-kbl: [FAIL][67] ([i915#644]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
- shard-hsw: [TIMEOUT][69] -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][71] ([IGT#5]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [INCOMPLETE][73] ([fdo#103665]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][75] ([i915#1188]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +5 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-top-left-pipe-a-planes:
- shard-skl: [FAIL][81] ([i915#1036]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][83] ([fdo#108145]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [FAIL][85] ([i915#899]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-skl: [DMESG-WARN][87] ([IGT#6]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +4 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][91] ([fdo#109276]) -> [PASS][92] +21 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@prime_busy@hang-bsd2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][93] ([fdo#112080]) -> [FAIL][94] ([IGT#28])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-snb: [SKIP][95] ([fdo#109271]) -> [INCOMPLETE][96] ([i915#82])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-snb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-snb6/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@runner@aborted:
- shard-hsw: ([FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106]) ([fdo#111870] / [i915#1356] / [i915#478]) -> ([FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115]) ([fdo#111870] / [i915#478])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw6/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw5/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw1/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw5/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw4/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw5/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw7/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
[i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
[i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
[i915#1356]: https://gitlab.freedesktop.org/drm/intel/issues/1356
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8032 -> Patchwork_16764
CI-20190529: 20190529
CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-03-02 13:31 ` Imre Deak
@ 2020-03-02 14:30 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 33+ messages in thread
From: Vudum, Lakshminarayana @ 2020-03-02 14:30 UTC (permalink / raw)
To: Deak, Imre, intel-gfx
@Deak, Imre Re-reported the results. All good now.
Lakshmi.
-----Original Message-----
From: Imre Deak <imre.deak@intel.com>
Sent: Monday, March 2, 2020 3:31 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL output/refclock tracking (rev2)
On Sun, Mar 01, 2020 at 02:06:00PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
> URL : https://patchwork.freedesktop.org/series/73977/
> State : failure
>
> [...]
> #### Possible regressions ####
>
> * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
> - shard-hsw: NOTRUN -> [TIMEOUT][1] +3 similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/ig
> t@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
Here perf/stress-open-close failed already, before kms_cursor_legacy and tests afterwards fail. It looks like
https://gitlab.freedesktop.org/drm/intel/issues/1356
<6>[ 306.955929] perf S12616 2283 1117 0x00000000
<4>[ 306.955932] Call Trace:
<4>[ 306.955935] ? __schedule+0x2e5/0x800 <4>[ 306.955940] schedule+0x37/0xe0 <4>[ 306.955942] schedule_timeout+0x225/0x3f0 <4>[ 306.955945] ? find_held_lock+0x2d/0x90 <4>[ 306.955983] ? i915_request_wait+0x175/0x880 [i915] <4>[ 306.955988] io_schedule_timeout+0x14/0x40 <4>[ 306.956026] i915_request_wait+0x1ce/0x880 [i915] <4>[ 306.956066] ? irq_execute_cb+0x20/0x20 [i915] <4>[ 306.956109] wait_for_space+0x114/0x290 [i915] <4>[ 306.956142] intel_ring_begin+0x229/0x490 [i915] <4>[ 306.956175] gen7_render_ring_flush+0xe4/0x300 [i915] <4>[ 306.956207] ring_request_alloc+0x75/0xca0 [i915] <4>[ 306.956246] __i915_request_create+0x253/0x600 [i915] <4>[ 306.956284] i915_request_create+0x8c/0x1d0 [i915] <4>[ 306.956320] emit_oa_config+0x46c/0x9c0 [i915] <4>[ 306.956357] i915_oa_stream_init.isra.41+0x794/0x11f0 [i915] <4>[ 306.956361] ? kmem_cache_alloc_trace+0x2a6/0x2d0
<4>[ 306.956398] i915_perf_open_ioctl+0x30a/0x760 [i915] <4>[ 306.956457] ? i915_oa_init_reg_state+0x160/0x160 [i915] <4>[ 306.956462] drm_ioctl_kernel+0xad/0xf0 <4>[ 306.956466] drm_ioctl+0x2e1/0x390 <4>[ 306.956503] ? i915_oa_init_reg_state+0x160/0x160 [i915] <4>[ 306.956506] ? find_held_lock+0x2d/0x90 <4>[ 306.956510] ? task_work_run+0x6e/0xb0 <4>[ 306.956514] ? _raw_spin_unlock_irq+0x1f/0x40 <4>[ 306.956518] ksys_ioctl+0x7b/0x90 <4>[ 306.956521] __x64_sys_ioctl+0x11/0x20 <4>[ 306.956524] do_syscall_64+0x4f/0x220 <4>[ 306.956526] entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 306.956528] RIP: 0033:0x7f6a68ecf5d7 <4>[ 306.956531] Code: Bad RIP value.
<4>[ 306.956533] RSP: 002b:00007ffcdb611258 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 <4>[ 306.956535] RAX: ffffffffffffffda RBX: 0000000000000005 RCX: 00007f6a68ecf5d7 <4>[ 306.956537] RDX: 00007ffcdb611540 RSI: 0000000040106476 RDI: 0000000000000005 <4>[ 306.956538] RBP: 00007ffcdb611540 R08: 000000000004bdd6 R09: 00000000000000bb <4>[ 306.956540] R10: 00000000de3f2d42 R11: 0000000000000246 R12: 0000000040106476 <4>[ 306.956541] R13: 0000000000000005 R14: 0000000000000000 R15: 0000000000000000
<6>[ 306.956548] perf S13288 2284 2283 0x00000000
<4>[ 306.956552] Call Trace:
<4>[ 306.956556] ? __schedule+0x2e5/0x800 <4>[ 306.956572] schedule+0x37/0xe0 <4>[ 306.956574] schedule_timeout+0x225/0x3f0 <4>[ 306.956577] ? find_held_lock+0x2d/0x90 <4>[ 306.956616] ? i915_request_wait+0x175/0x880 [i915] <4>[ 306.956621] io_schedule_timeout+0x14/0x40 <4>[ 306.956669] i915_request_wait+0x1ce/0x880 [i915] <4>[ 306.956708] ? irq_execute_cb+0x20/0x20 [i915] <4>[ 306.956746] i915_gem_object_wait+0x27c/0x540 [i915] <4>[ 306.956792] ? i915_gem_object_set_to_cpu_domain+0xd1/0x150 [i915] <4>[ 306.956825] i915_gem_set_domain_ioctl+0x143/0x500 [i915] <4>[ 306.956859] ? i915_gem_object_set_to_cpu_domain+0x150/0x150 [i915] <4>[ 306.956862] drm_ioctl_kernel+0xad/0xf0 <4>[ 306.956866] drm_ioctl+0x2e1/0x390 <4>[ 306.956901] ? i915_gem_object_set_to_cpu_domain+0x150/0x150 [i915] <4>[ 306.956909] ksys_ioctl+0x7b/0x90 <4>[ 306.956912] __x64_sys_ioctl+0x11/0x20 <4>[ 306.956914] do_syscall_64+0x4f/0x220 <4>[ 306.956916] entry_SYSCALL_64_after_hwframe+0x49/0xbe
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@perf@stress-open-close}:
> - shard-hsw: [INCOMPLETE][2] ([i915#61]) -> [TIMEOUT][3]
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw6/igt@perf@stress-open-close.html
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/ig
> t@perf@stress-open-close.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_16764_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#1340])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@gem_ctx_persistence@close-replace-race.html
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/ig
> t@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_ctx_shared@exec-single-timeline-bsd:
> - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110841])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/i
> gt@gem_ctx_shared@exec-single-timeline-bsd.html
>
> * igt@gem_exec_async@concurrent-writes-bsd:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112146]) +5 similar issues
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/i
> gt@gem_exec_async@concurrent-writes-bsd.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/i
> gt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@implicit-both-bsd1:
> - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276] / [i915#677]) +1 similar issue
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/i
> gt@gem_exec_schedule@implicit-both-bsd1.html
>
> * igt@gem_exec_schedule@independent-bsd2:
> - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276]) +15 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/i
> gt@gem_exec_schedule@independent-bsd2.html
>
> * igt@gem_exec_schedule@pi-distinct-iova-bsd:
> - shard-iclb: [PASS][16] -> [SKIP][17] ([i915#677]) +2 similar issues
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/i
> gt@gem_exec_schedule@pi-distinct-iova-bsd.html
>
> * igt@gem_exec_whisper@basic-queues-forked:
> - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#750])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-tglb2/igt@gem_exec_whisper@basic-queues-forked.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-tglb7/igt@gem_exec_whisper@basic-queues-forked.html
> - shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([i915#1120])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/i
> gt@gem_exec_whisper@basic-queues-forked.html
>
> * igt@gem_wait@busy-vcs1:
> - shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112080]) +3 similar issues
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_wait@busy-vcs1.html
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/i
> gt@gem_wait@busy-vcs1.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-iclb: [PASS][24] -> [FAIL][25] ([i915#454])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/i
> gt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_pm_rps@waitboost:
> - shard-iclb: [PASS][26] -> [FAIL][27] ([i915#413])
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@i915_pm_rps@waitboost.html
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/i
> gt@i915_pm_rps@waitboost.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +5 similar issues
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl6/ig
> t@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
> - shard-glk: [PASS][30] -> [FAIL][31] ([i915#72])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk8/ig
> t@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
>
> * igt@kms_fbcon_fbt@psr-suspend:
> - shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#69])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/ig
> t@kms_fbcon_fbt@psr-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [PASS][34] -> [FAIL][35] ([i915#79])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/ig
> t@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-glk: [PASS][36] -> [FAIL][37] ([i915#79])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/ig
> t@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#221])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/ig
> t@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible:
> - shard-glk: [PASS][40] -> [FAIL][41] ([i915#34])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> - shard-skl: [PASS][42] -> [FAIL][43] ([i915#34])
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/ig
> t@kms_flip@plain-flip-fb-recreate-interruptible.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [PASS][44] -> [FAIL][45] ([i915#1188])
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/ig
> t@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [i915#265]) +1 similar issue
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/ig
> t@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-glk: [PASS][48] -> [FAIL][49] ([i915#899])
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk7/ig
> t@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
> - shard-skl: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl3/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/ig
> t@kms_plane_multiple@atomic-pipe-a-tiling-y.html
>
> * igt@kms_psr2_su@frontbuffer:
> - shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109642] / [fdo#111068])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/i
> gt@kms_psr2_su@frontbuffer.html
>
> * igt@kms_psr@no_drrs:
> - shard-iclb: [PASS][54] -> [FAIL][55] ([i915#173])
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@no_drrs.html
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/i
> gt@kms_psr@no_drrs.html
>
> * igt@kms_psr@psr2_primary_mmap_cpu:
> - shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441]) +2 similar issues
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/i
> gt@kms_psr@psr2_primary_mmap_cpu.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +5 similar issues
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl6/ig
> t@kms_vblank@pipe-a-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-iclb: [INCOMPLETE][60] ([i915#1291]) -> [PASS][61]
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html
> [61]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb7/i
> gt@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_exec_parallel@vcs1-fds:
> - shard-iclb: [SKIP][62] ([fdo#112080]) -> [PASS][63] +17 similar issues
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/i
> gt@gem_exec_parallel@vcs1-fds.html
>
> * igt@gem_exec_schedule@implicit-write-read-bsd2:
> - shard-iclb: [SKIP][64] ([fdo#109276] / [i915#677]) -> [PASS][65]
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd2.html
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/i
> gt@gem_exec_schedule@implicit-write-read-bsd2.html
>
> * igt@gem_exec_schedule@pi-common-bsd:
> - shard-iclb: [SKIP][66] ([i915#677]) -> [PASS][67] +1 similar issue
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/i
> gt@gem_exec_schedule@pi-common-bsd.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [SKIP][68] ([fdo#112146]) -> [PASS][69] +7 similar issues
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/i
> gt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_ppgtt@flink-and-close-vma-leak:
> - shard-kbl: [FAIL][70] ([i915#644]) -> [PASS][71]
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
> [71]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl2/ig
> t@gem_ppgtt@flink-and-close-vma-leak.html
>
> * igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
> - shard-hsw: [TIMEOUT][72] -> [PASS][73]
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
> [73]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/ig
> t@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
> - shard-skl: [FAIL][74] ([IGT#5]) -> [PASS][75]
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
> [75]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/ig
> t@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-kbl: [INCOMPLETE][76] ([fdo#103665]) -> [PASS][77]
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [77]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl1/ig
> t@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_hdr@bpc-switch-suspend:
> - shard-skl: [FAIL][78] ([i915#1188]) -> [PASS][79]
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
> [79]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/ig
> t@kms_hdr@bpc-switch-suspend.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
> - shard-kbl: [DMESG-WARN][80] ([i915#180]) -> [PASS][81] +5 similar issues
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
> [81]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl4/ig
> t@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-apl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83]
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [83]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl3/ig
> t@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
> - shard-skl: [FAIL][84] -> [PASS][85]
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
> [85]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/ig
> t@kms_plane@plane-panning-top-left-pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
> - shard-skl: [FAIL][86] ([fdo#108145]) -> [PASS][87] +1 similar issue
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> [87]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl7/ig
> t@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-glk: [FAIL][88] ([i915#899]) -> [PASS][89]
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
> [89]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk1/ig
> t@kms_plane_lowres@pipe-a-tiling-y.html
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> - shard-skl: [DMESG-WARN][90] ([IGT#6]) -> [PASS][91]
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
> [91]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/ig
> t@kms_plane_multiple@atomic-pipe-b-tiling-y.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: [SKIP][92] ([fdo#109441]) -> [PASS][93] +4 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
> [93]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/i
> gt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@prime_busy@hang-bsd2:
> - shard-iclb: [SKIP][94] ([fdo#109276]) -> [PASS][95] +21 similar issues
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@prime_busy@hang-bsd2.html
> [95]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/i
> gt@prime_busy@hang-bsd2.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [SKIP][96] ([fdo#112080]) -> [FAIL][97] ([IGT#28])
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [97]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/i
> gt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@i915_pm_rpm@debugfs-forcewake-user:
> - shard-snb: [SKIP][98] ([fdo#109271]) -> [INCOMPLETE][99] ([i915#82])
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-snb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
> [99]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-snb6/ig
> t@i915_pm_rpm@debugfs-forcewake-user.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
> [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
> [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
> [i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
> [i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
> [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
> [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
> [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_8032 -> Patchwork_16764
>
> CI-20190529: 20190529
> CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clean up DPLL output/refclock tracking (rev2)
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
@ 2020-03-02 17:39 ` Imre Deak
0 siblings, 0 replies; 33+ messages in thread
From: Imre Deak @ 2020-03-02 17:39 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä
On Mon, Mar 02, 2020 at 01:56:03PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Clean up DPLL output/refclock tracking (rev2)
> URL : https://patchwork.freedesktop.org/series/73977/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8032_full -> Patchwork_16764_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_16764_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-skl: [PASS][1] -> [TIMEOUT][2] ([i915#1340])
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@gem_ctx_persistence@close-replace-race.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_ctx_shared@exec-single-timeline-bsd:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
>
> * igt@gem_exec_async@concurrent-writes-bsd:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +5 similar issues
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@implicit-both-bsd1:
> - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677]) +1 similar issue
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html
>
> * igt@gem_exec_schedule@independent-bsd2:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15 similar issues
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
>
> * igt@gem_exec_schedule@pi-distinct-iova-bsd:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([i915#677]) +2 similar issues
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
>
> * igt@gem_exec_whisper@basic-queues-forked:
> - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#750])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-tglb2/igt@gem_exec_whisper@basic-queues-forked.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-tglb7/igt@gem_exec_whisper@basic-queues-forked.html
> - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#1120])
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb5/igt@gem_exec_whisper@basic-queues-forked.html
>
> * igt@gem_wait@busy-vcs1:
> - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112080]) +3 similar issues
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_wait@busy-vcs1.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_wait@busy-vcs1.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#454])
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_pm_rps@waitboost:
> - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#413])
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@i915_pm_rps@waitboost.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@i915_pm_rps@waitboost.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +5 similar issues
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
> - shard-glk: [PASS][27] -> [FAIL][28] ([i915#72])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk8/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
>
> * igt@kms_fbcon_fbt@psr-suspend:
> - shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#69])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [PASS][31] -> [FAIL][32] ([i915#79])
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-glk: [PASS][33] -> [FAIL][34] ([i915#79])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-skl: [PASS][35] -> [INCOMPLETE][36] ([i915#221])
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible:
> - shard-glk: [PASS][37] -> [FAIL][38] ([i915#34])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> - shard-skl: [PASS][39] -> [FAIL][40] ([i915#34])
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [PASS][41] -> [FAIL][42] ([i915#1188])
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145] / [i915#265]) +1 similar issue
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-glk: [PASS][45] -> [FAIL][46] ([i915#899])
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
> - shard-skl: [PASS][47] -> [DMESG-WARN][48] ([IGT#6])
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl3/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
>
> * igt@kms_psr2_su@frontbuffer:
> - shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109642] / [fdo#111068])
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
>
> * igt@kms_psr@no_drrs:
> - shard-iclb: [PASS][51] -> [FAIL][52] ([i915#173])
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@no_drrs.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@kms_psr@no_drrs.html
>
> * igt@kms_psr@psr2_primary_mmap_cpu:
> - shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109441]) +2 similar issues
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-apl: [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +5 similar issues
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_persistence@close-replace-race:
> - shard-iclb: [INCOMPLETE][57] ([i915#1291]) -> [PASS][58]
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb7/igt@gem_ctx_persistence@close-replace-race.html
>
> * igt@gem_exec_parallel@vcs1-fds:
> - shard-iclb: [SKIP][59] ([fdo#112080]) -> [PASS][60] +17 similar issues
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
>
> * igt@gem_exec_schedule@implicit-write-read-bsd2:
> - shard-iclb: [SKIP][61] ([fdo#109276] / [i915#677]) -> [PASS][62]
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd2.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd2.html
>
> * igt@gem_exec_schedule@pi-common-bsd:
> - shard-iclb: [SKIP][63] ([i915#677]) -> [PASS][64] +1 similar issue
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [SKIP][65] ([fdo#112146]) -> [PASS][66] +7 similar issues
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_ppgtt@flink-and-close-vma-leak:
> - shard-kbl: [FAIL][67] ([i915#644]) -> [PASS][68]
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
>
> * igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
> - shard-hsw: [TIMEOUT][69] -> [PASS][70]
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@kms_atomic_transition@2x-modeset-transitions-nonblocking.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
> - shard-skl: [FAIL][71] ([IGT#5]) -> [PASS][72]
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-kbl: [INCOMPLETE][73] ([fdo#103665]) -> [PASS][74]
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_hdr@bpc-switch-suspend:
> - shard-skl: [FAIL][75] ([i915#1188]) -> [PASS][76]
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
> - shard-kbl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +5 similar issues
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80]
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
> - shard-skl: [FAIL][81] ([i915#1036]) -> [PASS][82]
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
> - shard-skl: [FAIL][83] ([fdo#108145]) -> [PASS][84] +1 similar issue
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-glk: [FAIL][85] ([i915#899]) -> [PASS][86]
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-y.html
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> - shard-skl: [DMESG-WARN][87] ([IGT#6]) -> [PASS][88]
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-skl10/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-skl8/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +4 similar issues
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@prime_busy@hang-bsd2:
> - shard-iclb: [SKIP][91] ([fdo#109276]) -> [PASS][92] +21 similar issues
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@prime_busy@hang-bsd2.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb1/igt@prime_busy@hang-bsd2.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [SKIP][93] ([fdo#112080]) -> [FAIL][94] ([IGT#28])
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@i915_pm_rpm@debugfs-forcewake-user:
> - shard-snb: [SKIP][95] ([fdo#109271]) -> [INCOMPLETE][96] ([i915#82])
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-snb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-snb6/igt@i915_pm_rpm@debugfs-forcewake-user.html
>
> * igt@runner@aborted:
> - shard-hsw: ([FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106]) ([fdo#111870] / [i915#1356] / [i915#478]) -> ([FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115]) ([fdo#111870] / [i915#478])
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw6/igt@runner@aborted.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw4/igt@runner@aborted.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw7/igt@runner@aborted.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw5/igt@runner@aborted.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8032/shard-hsw1/igt@runner@aborted.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw5/igt@runner@aborted.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw4/igt@runner@aborted.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw5/igt@runner@aborted.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw7/igt@runner@aborted.html
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw7/igt@runner@aborted.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw1/igt@runner@aborted.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/shard-hsw6/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
> [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
> [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
> [i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
> [i915#1120]: https://gitlab.freedesktop.org/drm/intel/issues/1120
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
> [i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
> [i915#1356]: https://gitlab.freedesktop.org/drm/intel/issues/1356
> [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
> [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
> [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
> [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_8032 -> Patchwork_16764
>
> CI-20190529: 20190529
> CI_DRM_8032: e61f34133ad908d4b455344daa7b4edb9fcf680c @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_16764: 8ab21b812217008f9addcd71af53a833e04e76f4 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16764/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2020-03-02 17:40 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-26 20:34 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL output/refclock tracking Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix bounds check in intel_get_shared_dpll_id() Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 03/13] drm/i915: Keep the global DPLL state in a DPLL specific struct Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move the DPLL vfunc inits after the func defines Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 05/13] drm/i915/hsw: Use the DPLL ID when calculating DPLL clock Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 07/13] drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 08/13] drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 09/13] drm/i915/hsw: Split out the SPLL parameter calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 10/13] drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation Imre Deak
2020-02-26 20:34 ` [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL " Imre Deak
2020-02-27 17:57 ` Ville Syrjälä
2020-02-27 18:34 ` Imre Deak
2020-02-27 18:49 ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again Imre Deak
2020-02-27 17:58 ` Ville Syrjälä
2020-02-26 20:34 ` [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking Imre Deak
2020-02-27 18:13 ` Ville Syrjälä
2020-02-27 19:01 ` Imre Deak
2020-02-28 15:33 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-02-27 4:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking Patchwork
2020-02-27 4:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-27 4:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28 0:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-02-28 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking (rev2) Patchwork
2020-02-28 17:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-02-28 18:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-01 14:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 13:31 ` Imre Deak
2020-03-02 14:30 ` Vudum, Lakshminarayana
2020-03-02 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-03-02 17:39 ` Imre Deak
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