From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FFB8C3F2D1 for ; Tue, 3 Mar 2020 17:54:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3B9D220728 for ; Tue, 3 Mar 2020 17:54:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583258042; bh=DRIj/511LI9YCCerkUGQuQURMrZ2X0geKBW/bOYrSwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=uh7hADxdhnY5XWhcs+BX3RyNwUX17lyV0sWvSTnNzUPh0flrY24eGeVCpe+47YoC+ ykx4+Emt9pPgnb9jUIFR9UUp+E30qFSmDFoD4rF9Oq3D9uYzsJ6XAyjIt0xQxjkJdJ Iv30tjV8sullibC49ayqU8u95jDnNV2dhzmqDXpg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732457AbgCCRyA (ORCPT ); Tue, 3 Mar 2020 12:54:00 -0500 Received: from mail.kernel.org ([198.145.29.99]:34592 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732431AbgCCRxx (ORCPT ); Tue, 3 Mar 2020 12:53:53 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 243092146E; Tue, 3 Mar 2020 17:53:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583258033; bh=DRIj/511LI9YCCerkUGQuQURMrZ2X0geKBW/bOYrSwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nNSkFHdmnvFEd9dPcb/FDGvOw9gG/Qn034rPTs45n/FdtimMqc+zvXObEVyuiRzs0 3lV+vA3B8gBMFKbwxSMVs2x23FKUZzUzAb762G2bDCprWDlXwu3of4TMftx32FRljt U2UMzpoyCh1647JSwSmFYa0QO3AuYnZXejBD6kB8= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Yongqiang Sun , Eric Yang , Bhawanpreet Lakha , Alex Deucher , Sasha Levin Subject: [PATCH 5.4 044/152] drm/amd/display: Limit minimum DPPCLK to 100MHz. Date: Tue, 3 Mar 2020 18:42:22 +0100 Message-Id: <20200303174307.397662650@linuxfoundation.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200303174302.523080016@linuxfoundation.org> References: <20200303174302.523080016@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yongqiang Sun [ Upstream commit 6c81917a0485ee2a1be0dc23321ac10ecfd9578b ] [Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by: Yongqiang Sun Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 787f94d815f42..dd92f9c295b45 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -91,6 +91,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; + } + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; -- 2.20.1