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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t 4/4] tools/intel_reg: Add support for reading indexed VGA registers
Date: Fri,  6 Mar 2020 14:50:02 +0200	[thread overview]
Message-ID: <20200306125002.21316-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200306125002.21316-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add convenient "ports" for accessing the indexed VGA registers.
SAdly we still have to poke these at times.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 lib/intel_reg.h        |  15 ++-
 tools/intel_reg.c      | 201 +++++++++++++++++++++++++++++++++++++++++
 tools/intel_reg_spec.c |  40 ++++++++
 tools/intel_reg_spec.h |  10 ++
 4 files changed, 263 insertions(+), 3 deletions(-)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 0a9ee34cd90d..036dfec51e7d 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -46,9 +46,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 /* I/O register offsets
  */
-#define SRX 0x3C4		/* p208 */
-#define GRX 0x3CE		/* p213 */
-#define ARX 0x3C0		/* p224 */
+#define CRX_MDA		0x3B4
+#define CRD_MDA		0x3B5
+#define ST01_MDA	0x3BA
+#define ARX		0x3C0
+#define ARD_R		0x3C1
+#define SRX		0x3C4
+#define SRD		0x3C5
+#define GRX		0x3CE
+#define GRD		0x3CF
+#define CRX_CGA		0x3D4
+#define CRD_CGA		0x3D5
+#define ST01_CGA	0x3DA
 
 /* VGA Color Palette Registers */
 #define DACMASK  0x3C6		/* p232 */
diff --git a/tools/intel_reg.c b/tools/intel_reg.c
index 69af0f5a19ff..f46b4849ddd8 100644
--- a/tools/intel_reg.c
+++ b/tools/intel_reg.c
@@ -374,6 +374,119 @@ static uint32_t mcbar_offset(uint32_t devid)
 	return intel_gen(devid) >= 6 ? 0x140000 : 0x10000;
 }
 
+static bool vga_is_cga_mode(bool mmio)
+{
+	if (mmio)
+		return INREG8(MSR_R) & IO_ADDR_SELECT;
+	else
+		return inb(MSR_R) & IO_ADDR_SELECT;
+}
+
+static uint16_t vga_st01(bool mmio)
+{
+	if (vga_is_cga_mode(mmio))
+		return ST01_CGA;
+	else
+		return ST01_MDA;
+}
+
+static uint16_t vga_crx(bool mmio)
+{
+	if (vga_is_cga_mode(mmio))
+		return CRX_CGA;
+	else
+		return CRX_MDA;
+}
+
+static uint16_t vga_crd(bool mmio)
+{
+	if (vga_is_cga_mode(mmio))
+		return CRD_CGA;
+	else
+		return CRD_MDA;
+}
+
+static uint8_t vga_read(uint16_t index_reg, uint16_t data_reg,
+			uint8_t index, bool mmio)
+{
+	uint8_t val;
+
+	if (mmio) {
+		if (index_reg == ARX)
+			INREG(vga_st01(mmio)); /* reset flip-flop */
+		OUTREG8(index_reg, index);
+		val = INREG8(data_reg);
+	} else {
+		iopl(3);
+		if (index_reg == ARX)
+			inb(vga_st01(mmio)); /* reset flip-flop */
+		outb(index, index_reg);
+		val = inb(data_reg);
+		iopl(0);
+	}
+
+	return val;
+}
+
+static void vga_write(uint16_t index_reg, uint16_t data_reg,
+		      uint8_t index, uint8_t value, bool mmio)
+{
+	if (mmio) {
+		if (index_reg == ARX)
+			INREG(vga_st01(mmio)); /* reset flip-flop */
+		OUTREG8(index_reg, index);
+		OUTREG(data_reg, value);
+	} else {
+		iopl(3);
+		if (index_reg == ARX)
+			inb(vga_st01(mmio)); /* reset flip-flop */
+		outb(index, index_reg);
+		outb(value, data_reg);
+		iopl(0);
+	}
+}
+
+static uint8_t vga_ar_read(uint8_t index, bool mmio)
+{
+	return vga_read(ARX, ARD_R, index, mmio);
+}
+
+static void vga_ar_write(uint8_t index, uint8_t value, bool mmio)
+{
+	/* Yes, ARX is where you write the data! */
+	vga_write(ARX, ARX, index, value, mmio);
+}
+
+static uint8_t vga_sr_read(uint8_t index, bool mmio)
+{
+	return vga_read(SRX, SRD, index, mmio);
+}
+
+static void vga_sr_write(uint8_t index, uint8_t value, bool mmio)
+{
+	vga_write(SRX, SRD, index, value, mmio);
+}
+
+static uint8_t vga_gr_read(uint8_t index, bool mmio)
+{
+	return vga_read(GRX, GRD, index, mmio);
+}
+
+static void vga_gr_write(uint8_t index, uint8_t value, bool mmio)
+{
+	vga_write(GRX, GRD, index, value, mmio);
+}
+
+static uint8_t vga_cr_read(uint8_t index, bool mmio)
+{
+	return vga_read(vga_crx(mmio), vga_crd(mmio), index, mmio);
+}
+
+static void vga_cr_write(uint8_t index, uint8_t value, bool mmio)
+{
+	vga_write(vga_crx(mmio), vga_crd(mmio), index, value, mmio);
+}
+
 static int read_register(struct config *config, struct reg *reg, uint32_t *valp)
 {
 	uint32_t val = 0;
@@ -400,11 +513,35 @@ static int read_register(struct config *config, struct reg *reg, uint32_t *valp)
 	case PORT_MMIO_8:
 		val = INREG8(reg->mmio_offset + reg->addr);
 		break;
+	case PORT_MMIO_VGA_AR:
+		val = vga_ar_read(reg->addr, true);
+		break;
+	case PORT_MMIO_VGA_SR:
+		val = vga_sr_read(reg->addr, true);
+		break;
+	case PORT_MMIO_VGA_GR:
+		val = vga_gr_read(reg->addr, true);
+		break;
+	case PORT_MMIO_VGA_CR:
+		val = vga_cr_read(reg->addr, true);
+		break;
 	case PORT_PORTIO:
 		iopl(3);
 		val = inb(reg->addr);
 		iopl(0);
 		break;
+	case PORT_PORTIO_VGA_AR:
+		val = vga_ar_read(reg->addr, false);
+		break;
+	case PORT_PORTIO_VGA_SR:
+		val = vga_sr_read(reg->addr, false);
+		break;
+	case PORT_PORTIO_VGA_GR:
+		val = vga_gr_read(reg->addr, false);
+		break;
+	case PORT_PORTIO_VGA_CR:
+		val = vga_cr_read(reg->addr, false);
+		break;
 	case PORT_BUNIT:
 	case PORT_PUNIT:
 	case PORT_NC:
@@ -474,6 +611,38 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val)
 		}
 		OUTREG8(reg->mmio_offset + reg->addr, val);
 		break;
+	case PORT_MMIO_VGA_AR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_ar_write(reg->addr, val, true);
+		break;
+	case PORT_MMIO_VGA_SR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_sr_write(reg->addr, val, true);
+		break;
+	case PORT_MMIO_VGA_GR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_gr_write(reg->addr, val, true);
+		break;
+	case PORT_MMIO_VGA_CR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_cr_write(reg->addr, val, true);
+		break;
 	case PORT_PORTIO:
 		if (val > 0xff) {
 			fprintf(stderr, "value 0x%08x out of range for port %s\n",
@@ -484,6 +653,38 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val)
 		outb(val, reg->addr);
 		iopl(0);
 		break;
+	case PORT_PORTIO_VGA_AR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_ar_write(reg->addr, val, false);
+		break;
+	case PORT_PORTIO_VGA_SR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_sr_write(reg->addr, val, false);
+		break;
+	case PORT_PORTIO_VGA_GR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_gr_write(reg->addr, val, false);
+		break;
+	case PORT_PORTIO_VGA_CR:
+		if (val > 0xff) {
+			fprintf(stderr, "value 0x%08x out of range for port %s\n",
+				val, reg->port_desc.name);
+			return -1;
+		}
+		vga_cr_write(reg->addr, val, false);
+		break;
 	case PORT_BUNIT:
 	case PORT_PUNIT:
 	case PORT_NC:
diff --git a/tools/intel_reg_spec.c b/tools/intel_reg_spec.c
index dadd844730f0..632db6b9f045 100644
--- a/tools/intel_reg_spec.c
+++ b/tools/intel_reg_spec.c
@@ -63,11 +63,51 @@ static const struct port_desc port_descs[] = {
 		.port = PORT_MCHBAR_8,
 		.stride = 1,
 	},
+	{
+		.name = "mmio-ar",
+		.port = PORT_MMIO_VGA_AR,
+		.stride = 1,
+	},
+	{
+		.name = "mmio-sr",
+		.port = PORT_MMIO_VGA_SR,
+		.stride = 1,
+	},
+	{
+		.name = "mmio-gr",
+		.port = PORT_MMIO_VGA_GR,
+		.stride = 1,
+	},
+	{
+		.name = "mmio-cr",
+		.port = PORT_MMIO_VGA_CR,
+		.stride = 1,
+	},
 	{
 		.name = "portio",
 		.port = PORT_PORTIO,
 		.stride = 1,
 	},
+	{
+		.name = "portio-ar",
+		.port = PORT_PORTIO_VGA_AR,
+		.stride = 1,
+	},
+	{
+		.name = "portio-sr",
+		.port = PORT_PORTIO_VGA_SR,
+		.stride = 1,
+	},
+	{
+		.name = "portio-gr",
+		.port = PORT_PORTIO_VGA_GR,
+		.stride = 1,
+	},
+	{
+		.name = "portio-cr",
+		.port = PORT_PORTIO_VGA_CR,
+		.stride = 1,
+	},
 	{
 		.name = "bunit",
 		.port = PORT_BUNIT,
diff --git a/tools/intel_reg_spec.h b/tools/intel_reg_spec.h
index fc27a9a62f6f..06d9bc257558 100644
--- a/tools/intel_reg_spec.h
+++ b/tools/intel_reg_spec.h
@@ -33,8 +33,18 @@ enum port_addr {
 	PORT_MCHBAR_16,
 	PORT_MCHBAR_8,
 
+	PORT_MMIO_VGA_AR,
+	PORT_MMIO_VGA_SR,
+	PORT_MMIO_VGA_GR,
+	PORT_MMIO_VGA_CR,
+
 	PORT_PORTIO,
 
+	PORT_PORTIO_VGA_AR,
+	PORT_PORTIO_VGA_SR,
+	PORT_PORTIO_VGA_GR,
+	PORT_PORTIO_VGA_CR,
+
 	PORT_NONE = 0,
 
 	/* vlv */
-- 
2.24.1

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  parent reply	other threads:[~2020-03-06 12:50 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-06 12:49 [igt-dev] [PATCH i-g-t 1/4] tools/intel_reg: Simplify negative ports Ville Syrjala
2020-03-06 12:50 ` [igt-dev] [PATCH i-g-t 2/4] tools/intel_reg: Support 8 and 16 bit mmio registers Ville Syrjala
2020-03-09  8:03   ` Jani Nikula
2020-03-06 12:50 ` [igt-dev] [PATCH i-g-t 3/4] tools/intel_reg: Add support for register access via the MCHBAR mirror Ville Syrjala
2020-03-09  8:24   ` Jani Nikula
2020-03-06 12:50 ` Ville Syrjala [this message]
2020-03-06 13:38 ` [igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/4] tools/intel_reg: Simplify negative ports Patchwork
2020-03-09  7:52 ` [igt-dev] [PATCH i-g-t 1/4] " Jani Nikula
2023-01-25  5:42 Ville Syrjala
2023-01-25  5:42 ` [igt-dev] [PATCH i-g-t 4/4] tools/intel_reg: Add support for reading indexed VGA registers Ville Syrjala

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