From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52561C10F27 for ; Mon, 9 Mar 2020 16:09:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 01DDF20828 for ; Mon, 9 Mar 2020 16:09:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="so5+iHtV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727146AbgCIQJj (ORCPT ); Mon, 9 Mar 2020 12:09:39 -0400 Received: from pandora.armlinux.org.uk ([78.32.30.218]:50624 "EHLO pandora.armlinux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727080AbgCIQJj (ORCPT ); Mon, 9 Mar 2020 12:09:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Sender:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=4WJ6RRjRxj58Y2szEsveSp6vWyd/sdxRQxE7lizeTGg=; b=so5+iHtVgqSfai4qSOj1oxrE+ ZsvzKP9v8gREGRl/MnOEHqraNdvdCgWnOR4VC4jLNIf/7y2C9mFNsqDRtsDKr2onOebVCCrwu+y2p k0cZmvafWm45Gll8Aq3YrRWOJMk6ofZPxt67qQRS96IiV0+eN63zp+4ZBbOkDRpfyA4NaJRn8kaED 1rnbleBN1ggg6DBqfxzJKpODVEdtQ1uow9Z5bLvHLw/DzcNjV/t6BUJgi/4spPloXQZQqvY/I7kCu HZm5Fzt3WpbavxhUkfEVuZE4NRdpdtngH9REd60Rs3E5dGFSJqYiP0UrMN0L8ipP1n0cf4TZcmwOE UGvaPY97A==; Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:34200) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jBKy7-0007tm-Qi; Mon, 09 Mar 2020 16:09:28 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1jBKxz-0003Vd-9p; Mon, 09 Mar 2020 16:09:19 +0000 Date: Mon, 9 Mar 2020 16:09:19 +0000 From: Russell King - ARM Linux admin To: Catalin Marinas Cc: Arnd Bergmann , Nishanth Menon , Santosh Shilimkar , Tero Kristo , Linux ARM , Michal Hocko , Rik van Riel , Santosh Shilimkar , Dave Chinner , Linux Kernel Mailing List , Linux-MM , Yafang Shao , Al Viro , Johannes Weiner , linux-fsdevel , kernel-team@fb.com, Kishon Vijay Abraham I , Linus Torvalds , Andrew Morton , Roman Gushchin Subject: Re: [PATCH] vfs: keep inodes with page cache off the inode shrinker LRU Message-ID: <20200309160919.GM25745@shell.armlinux.org.uk> References: <20200211164701.4ac88d9222e23d1e8cc57c51@linux-foundation.org> <20200212085004.GL25745@shell.armlinux.org.uk> <671b05bc-7237-7422-3ece-f1a4a3652c92@oracle.com> <7c4c1459-60d5-24c8-6eb9-da299ead99ea@oracle.com> <20200306203439.peytghdqragjfhdx@kahuna> <20200309155945.GA4124965@arrakis.emea.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200309155945.GA4124965@arrakis.emea.arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 09, 2020 at 03:59:45PM +0000, Catalin Marinas wrote: > On Sun, Mar 08, 2020 at 11:58:52AM +0100, Arnd Bergmann wrote: > > - revisit CONFIG_VMSPLIT_4G_4G for arm32 (and maybe mips32) > > to see if it can be done, and what the overhead is. This is probably > > more work than the others combined, but also the most promising > > as it allows the most user address space and physical ram to be used. > > A rough outline of such support (and likely to miss some corner cases): > > 1. Kernel runs with its own ASID and non-global page tables. > > 2. Trampoline code on exception entry/exit to handle the TTBR0 switching > between user and kernel. > > 3. uaccess routines need to be reworked to pin the user pages in memory > (get_user_pages()) and access them via the kernel address space. > > Point 3 is probably the ugliest and it would introduce a noticeable > slowdown in certain syscalls. We also need to consider that it has implications for the single-kernel support; a kernel doing this kind of switching would likely be horrid for a kernel supporting v6+ with VIPT aliasing caches. Would we be adding a new red line between kernels supporting VIPT-aliasing caches (present in earlier v6 implementations) and kernels using this system? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C626BC10F27 for ; Mon, 9 Mar 2020 16:12:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 794CC2464B for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 09, 2020 at 03:59:45PM +0000, Catalin Marinas wrote: > On Sun, Mar 08, 2020 at 11:58:52AM +0100, Arnd Bergmann wrote: > > - revisit CONFIG_VMSPLIT_4G_4G for arm32 (and maybe mips32) > > to see if it can be done, and what the overhead is. This is probably > > more work than the others combined, but also the most promising > > as it allows the most user address space and physical ram to be used. > > A rough outline of such support (and likely to miss some corner cases): > > 1. Kernel runs with its own ASID and non-global page tables. > > 2. Trampoline code on exception entry/exit to handle the TTBR0 switching > between user and kernel. > > 3. uaccess routines need to be reworked to pin the user pages in memory > (get_user_pages()) and access them via the kernel address space. > > Point 3 is probably the ugliest and it would introduce a noticeable > slowdown in certain syscalls. We also need to consider that it has implications for the single-kernel support; a kernel doing this kind of switching would likely be horrid for a kernel supporting v6+ with VIPT aliasing caches. Would we be adding a new red line between kernels supporting VIPT-aliasing caches (present in earlier v6 implementations) and kernels using this system? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel