* [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support
@ 2020-03-09 16:11 Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
` (11 more replies)
0 siblings, 12 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:11 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
v17: Had to rebase the whole series.
v19: Added some new patches in between, rebased
Stanislav Lisovskiy (8):
drm/i915: Start passing latency as parameter
drm/i915: Introduce skl_plane_wm_level accessor.
drm/i915: Add intel_bw_get_*_state helpers
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Added required new PCode commands
drm/i915: Rename bw_state to new_bw_state
drm/i915: Restrict qgv points which don't have enough bandwidth.
drm/i915: Enable SAGV support for Gen12
drivers/gpu/drm/i915/display/intel_bw.c | 202 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 36 ++
drivers/gpu/drm/i915/display/intel_display.c | 33 +-
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 516 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 4 +
drivers/gpu/drm/i915/intel_sideband.c | 2 +
8 files changed, 689 insertions(+), 114 deletions(-)
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
@ 2020-03-09 16:11 ` Stanislav Lisovskiy
2020-03-10 14:32 ` Ville Syrjälä
2020-03-11 9:16 ` Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
` (10 subsequent siblings)
11 siblings, 2 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:11 UTC (permalink / raw)
To: intel-gfx
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..c7928c870b0a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
drm_WARN_ON(&dev_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
@ 2020-03-09 16:11 ` Stanislav Lisovskiy
[not found] ` <20200311160727.GA13686@intel.com>
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
` (9 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:11 UTC (permalink / raw)
To: intel-gfx
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c7928c870b0a..c72fa59a8302 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4547,6 +4547,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4606,22 +4618,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane + 1);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4644,10 +4663,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane + 1);
if (plane_id == PLANE_CURSOR)
continue;
@@ -4663,7 +4688,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -4674,7 +4699,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4717,8 +4742,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, color_plane + 1);
/*
* We only disable the watermarks for each plane if
@@ -4732,9 +4765,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane_id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane_id])
+ memset(&wm->wm[level], 0,
+ sizeof(struct skl_wm_level));
/*
* Wa_1408961008:icl, ehl
@@ -4742,9 +4776,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ 0, color_plane);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -5358,8 +5397,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5392,8 +5436,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-03-09 16:11 ` Stanislav Lisovskiy
[not found] ` <20200311160854.GB13686@intel.com>
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
` (8 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:11 UTC (permalink / raw)
To: intel-gfx
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..bdad7476dc7b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
-intel_atomic_get_bw_state(struct intel_atomic_state *state)
+struct intel_bw_state *
+intel_bw_get_old_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_bw_get_new_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_bw_get_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
@@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
+ bw_state = intel_bw_get_state(state);
if (IS_ERR(bw_state))
return PTR_ERR(bw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..b5f61463922f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_bw_get_old_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_bw_get_new_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_bw_get_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
@ 2020-03-09 16:12 ` Stanislav Lisovskiy
2020-03-11 9:13 ` Stanislav Lisovskiy
[not found] ` <20200311163130.GC13686@intel.com>
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
` (7 subsequent siblings)
11 siblings, 2 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:12 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
v14: - total_affected_planes is no longer needed to check for ddb changes,
just as active_pipe_changes.
v15: - Fixed stupid mistake with uninitialized crtc in
skl_compute_sagv_mask.
v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
- Added return value to intel_compute_sagv_mask which call
intel_atomic_serialize_global_state in order to properly
propagate EDEADLCK to drm.
- Based on the discussion with Ville, removed active_pipe_changes
check and also there seems to be no need for checking ddb_state_changes
as well. Instead we just iterate through crtcs in state - having
crtc in a state already guarantees that it is at least read-locked
Having additional flag to check if there actually were some plane
wm/ddb changes would be probably added later as an optimization.
- We can't get parent atomic state from crtc_state at commit stage
(nice drm feature), also propagating state through function call
chain seems to be overkill and not possible(cursor legacy updates)
Querying for bw_state object from global state is not possible as
it might get swapped with other global state.
So... just sticked can_sagv boolean into wm crtc state.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 23 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 1 +
5 files changed, 318 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index b5f61463922f..4083adf4b432 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f23c4d51c33..9e0058a78ea6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
@@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
-
dev_priv->active_pipes = state->active_pipes;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5e00e611f077..da0308b87dad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -669,11 +669,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c72fa59a8302..f598b55f4abc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = state->base.dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc;
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
+ crtc = to_intel_crtc(crtc_state->uapi.crtc);
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
+ if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
return false;
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(crtc->pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
return false;
+ }
}
return true;
}
+static bool
+tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
+
+static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
+{
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ int i;
+
+ /*
+ * If SAGV is not supported we just can't do anything
+ * not even set or reject SAGV points - just bail out.
+ * Thus avoid needless calculations.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return 0;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ bool pipe_sagv_enable;
+
+ new_bw_state = intel_bw_get_state(state);
+ old_bw_state = intel_bw_get_old_state(state);
+
+ if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return -EINVAL;
+ }
+
+ new_bw_state->sagv_calculated = false;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
+ else
+ pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
+
+ if (pipe_sagv_enable)
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
+
+ if (!new_bw_state || !old_bw_state)
+ return 0;
+
+ new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
+ new_bw_state->sagv_calculated = true;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = new_bw_state->can_sagv;
+ }
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+ DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
+ state,
+ old_bw_state->pipe_sagv_reject,
+ new_bw_state->pipe_sagv_reject);
+
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *bw_state;
+
+ if (!intel_has_sagv(dev_priv)) {
+ DRM_DEBUG_KMS("No SAGV support detected\n");
+ return false;
+ }
+
+ bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR_OR_NULL(bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return false;
+ }
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
@@ -4042,6 +4161,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
u32 latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4556,9 +4676,83 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ if (!level) {
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
+
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * If pipe is not active it can't affect SAGV rejection
+ * Checking it here is needed to leave only cases when
+ * alloc_size is 0 for any other reasons, except inactive
+ * pipe. As inactive pipe is fine, however having no ddb
+ * space available is already problematic - so need to
+ * to separate those.
+ */
+ if (!crtc_state->hw.active)
+ return true;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return false;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return false;
+ }
+ }
+ DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+ blocks, alloc_size);
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5140,11 +5334,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -5155,6 +5357,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5237,7 +5460,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5259,7 +5482,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5598,9 +5821,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
+ const struct skl_wm_level *old_wm_level, *new_wm_level;
+ u16 old_plane_res_l, new_plane_res_l;
+ u8 old_plane_res_b, new_plane_res_b;
+ u16 old_min_ddb_alloc, new_min_ddb_alloc;
+ int color_plane = 0;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
+ old_wm_level = skl_plane_wm_level(old_crtc_state, plane_id, 0, color_plane);
+ new_wm_level = skl_plane_wm_level(new_crtc_state, plane_id, 0, color_plane);
+
+ old_plane_res_l = old_wm_level->plane_res_l;
+ old_plane_res_b = old_wm_level->plane_res_b;
+
+ new_plane_res_l = new_wm_level->plane_res_l;
+ new_plane_res_b = new_wm_level->plane_res_b;
+
+ old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
+ new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue;
@@ -5624,7 +5863,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+ enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5634,7 +5873,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+ enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5648,12 +5887,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+ old_plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+ new_plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5663,12 +5902,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+ old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
- new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+ new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
return ret;
}
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5960,6 +6203,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..65743a4cbcf6 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
@ 2020-03-09 16:12 ` Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
` (6 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:12 UTC (permalink / raw)
To: intel-gfx
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80cf02a6eec1..ba35ff190bb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8992,6 +8992,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9013,6 +9014,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -9025,6 +9027,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-03-09 16:12 ` Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
` (5 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:12 UTC (permalink / raw)
To: intel-gfx
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bdad7476dc7b..256c9322636c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_bw_get_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(&dev_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(&bw_state->base);
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
@ 2020-03-09 16:12 ` Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
` (4 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:12 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
v17: - Moved qgv point related manipulations next to SAGV code, as
those are semantically related(Ville Syrjälä)
- Renamed those into intel_sagv_(pre)|(post)_plane_update
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 147 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 109 +++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 3 +
6 files changed, 244 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 256c9322636c..9619e8debea6 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
if (qgv_point >= bi->num_qgv_points)
return UINT_MAX;
- if (num_planes >= bi->num_planes)
+ if (num_planes >= bi->num_planes || !num_planes)
return bi->deratedbw[qgv_point];
}
@@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -419,10 +424,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -465,23 +475,86 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return 0;
ret = intel_atomic_lock_global_state(&new_bw_state->base);
- if (ret)
+ if (ret) {
+ DRM_DEBUG_KMS("Could not lock global state\n");
return ret;
+ }
data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth for display configuration.\n");
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(state)) {
+ allowed_points = 1 << max_bw_point;
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+ state, new_bw_state->qgv_points_mask);
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR(old_bw_state)) {
+ DRM_DEBUG_KMS("Could not get old bw state!\n");
+ return PTR_ERR(old_bw_state);
+ }
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 4083adf4b432..1ea3bad32b2b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -36,6 +36,13 @@ struct intel_bw_state {
*/
bool can_sagv;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
@@ -56,5 +63,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e0058a78ea6..c88ea12c5f7a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15541,6 +15541,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+ * Now we need to check if SAGV needs to be disabled(i.e QGV points
+ * modified even, when no modeset is done(for example plane updates
+ * can now trigger that).
+ */
+ if ((INTEL_GEN(dev_priv) >= 11) && state->modeset)
+ intel_sagv_pre_plane_update(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
@@ -15656,6 +15664,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (INTEL_GEN(dev_priv) < 11) {
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+ } else if (state->modeset) {
+ intel_sagv_post_plane_update(state);
}
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index da0308b87dad..29ffb0a8f778 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -674,6 +674,9 @@ struct skl_plane_wm {
bool is_planar;
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
bool can_sagv;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f598b55f4abc..4ec4dbba022f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3758,6 +3758,115 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR_OR_NULL(new_bw_state)) {
+ WARN(1, "Could not get new bw_state\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR_OR_NULL(old_bw_state)) {
+ WARN(1, "Could not get old bw_state\n");
+ return;
+ }
+
+ /*
+ * Nothing to mask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not mask required qgv points(%d)\n",
+ ret);
+}
+
+void intel_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ u32 new_mask = 0;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_bw_get_state(state);
+ if (IS_ERR_OR_NULL(new_bw_state)) {
+ WARN(1, "Could not get new bw_state\n");
+ return;
+ }
+
+ old_bw_state = intel_bw_get_old_state(state);
+ if (IS_ERR_OR_NULL(old_bw_state)) {
+ WARN(1, "Could not get old bw_state\n");
+ return;
+ }
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not unmask required qgv points(%d)\n",
+ ret);
+}
+
static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc_state->uapi.crtc->dev;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 65743a4cbcf6..6102bb52d8cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
+
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-03-09 16:12 ` Stanislav Lisovskiy
2020-03-09 16:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-09 16:12 UTC (permalink / raw)
To: intel-gfx
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4ec4dbba022f..a8a01a980b8f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (7 preceding siblings ...)
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-03-09 16:42 ` Patchwork
2020-03-10 13:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-03-09 16:42 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/74461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5a587535617 drm/i915: Start passing latency as parameter
33f087f7ad33 drm/i915: Introduce skl_plane_wm_level accessor.
187985037fe5 drm/i915: Add intel_bw_get_*_state helpers
0d3043296dee drm/i915: Refactor intel_can_enable_sagv
-:113: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#113:
check and also there seems to be no need for checking ddb_state_changes
total: 0 errors, 1 warnings, 0 checks, 548 lines checked
6bef05bea7fe drm/i915: Added required new PCode commands
794d317f4d58 drm/i915: Rename bw_state to new_bw_state
cf60e64c735d drm/i915: Restrict qgv points which don't have enough bandwidth.
0f8277c857a7 drm/i915: Enable SAGV support for Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (8 preceding siblings ...)
2020-03-09 16:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
@ 2020-03-10 13:58 ` Patchwork
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
2020-03-11 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4) Patchwork
11 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-03-10 13:58 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/74461/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8106 -> Patchwork_16893
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16893 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16893, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16893:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@evict:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-bwr-2160/igt@i915_selftest@live@evict.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-bwr-2160/igt@i915_selftest@live@evict.html
* igt@kms_busy@basic@modeset:
- fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
- fi-skl-guc: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-skl-guc/igt@kms_busy@basic@modeset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-skl-guc/igt@kms_busy@basic@modeset.html
- fi-kbl-7500u: NOTRUN -> [INCOMPLETE][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-kbl-7500u/igt@kms_busy@basic@modeset.html
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
Known issues
------------
Here are the changes found in Patchwork_16893 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-skl-6770hq: [PASS][11] -> [INCOMPLETE][12] ([i915#1242] / [i915#198])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-8700k: [PASS][13] -> [INCOMPLETE][14] ([i915#1242])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-guc: [PASS][15] -> [INCOMPLETE][16] ([i915#1242])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@dmabuf:
- fi-ivb-3770: [PASS][17] -> [DMESG-WARN][18] ([i915#1405])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-ivb-3770/igt@i915_selftest@live@dmabuf.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-ivb-3770/igt@i915_selftest@live@dmabuf.html
* igt@i915_selftest@live@hangcheck:
- fi-ivb-3770: [PASS][19] -> [INCOMPLETE][20] ([i915#1405])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@modeset:
- fi-cml-s: [PASS][21] -> [INCOMPLETE][22] ([i915#283])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-cml-s/igt@kms_busy@basic@modeset.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-cml-s/igt@kms_busy@basic@modeset.html
- fi-cml-u2: [PASS][23] -> [INCOMPLETE][24] ([i915#283])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-cml-u2/igt@kms_busy@basic@modeset.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-cml-u2/igt@kms_busy@basic@modeset.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][25] -> [DMESG-WARN][26] ([CI#94] / [i915#402])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242
[i915#1405]: https://gitlab.freedesktop.org/drm/intel/issues/1405
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 38)
------------------------------
Additional (4): fi-cfl-8109u fi-bdw-5557u fi-kbl-7500u fi-snb-2600
Missing (10): fi-hsw-4200u fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-kbl-7560u fi-byt-clapper fi-bdw-samus fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8106 -> Patchwork_16893
CI-20190529: 20190529
CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16893: 116c15e39e85e200b7eca05d90f64572400d5cbe @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
116c15e39e85 drm/i915: Enable SAGV support for Gen12
3733daf9704b drm/i915: Restrict qgv points which don't have enough bandwidth.
69c7f39fa5d4 drm/i915: Rename bw_state to new_bw_state
26fec9c73c37 drm/i915: Added required new PCode commands
e1d39e7c0310 drm/i915: Refactor intel_can_enable_sagv
1f389ea12cba drm/i915: Add intel_bw_get_*_state helpers
7f788a230fbe drm/i915: Introduce skl_plane_wm_level accessor.
9c1a1e8de31f drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16893/index.html
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* Re: [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
@ 2020-03-10 14:32 ` Ville Syrjälä
2020-03-10 14:54 ` Lisovskiy, Stanislav
2020-03-11 9:16 ` Stanislav Lisovskiy
1 sibling, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-10 14:32 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Mar 09, 2020 at 06:11:57PM +0200, Stanislav Lisovskiy wrote:
> We need to start passing memory latency as a
> parameter when calculating plane wm levels,
> as latency can get changed in different
> circumstances(for example with or without SAGV).
> So we need to be more flexible on that matter.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8375054ba27d..c7928c870b0a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
So you didn't change the types?
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */);
> @@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> drm_WARN_ON(&dev_priv->drm, ret);
>
> for (level = 0; level <= max_level; level++) {
> - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> + u32 latency = dev_priv->wm.skl_latency[level];
> +
> + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, wm_params,
> - result_prev, result);
> + skl_compute_plane_wm(crtc_state, level, latency,
> + wm_params, result_prev, result);
>
> result_prev = result;
> }
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
2020-03-10 14:32 ` Ville Syrjälä
@ 2020-03-10 14:54 ` Lisovskiy, Stanislav
2020-03-10 20:44 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-10 14:54 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, 2020-03-10 at 16:32 +0200, Ville Syrjälä wrote:
> On Mon, Mar 09, 2020 at 06:11:57PM +0200, Stanislav Lisovskiy wrote:
> > We need to start passing memory latency as a
> > parameter when calculating plane wm levels,
> > as latency can get changed in different
> > circumstances(for example with or without SAGV).
> > So we need to be more flexible on that matter.
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> > 1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8375054ba27d..c7928c870b0a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > int color_plane);
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
>
> So you didn't change the types?
Yes, I saw your comment there - and looked into this, however I just
wondered, does it make any sense do to that. The reason is because
skl_latency is anyway defined as u16 in i915_drv.h, just as pri/spr/cur
latencies, so wonder how this "unsigned int" going to fit into this.
Should I maybe then change it to u16 - at least that would somehow
comply with the current declarations.
>
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out
> > */);
> > @@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct
> > intel_crtc_state *crtc_state,
> > drm_WARN_ON(&dev_priv->drm, ret);
> >
> > for (level = 0; level <= max_level; level++) {
> > - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> > + u32 latency = dev_priv->wm.skl_latency[level];
> > +
> > + skl_compute_plane_wm(crtc_state, level, latency, &wp,
> > &wm, &wm);
> > if (wm.min_ddb_alloc == U16_MAX)
> > break;
> >
> > @@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct
> > drm_i915_private *dev_priv, int level)
> >
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out */)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > - u32 latency = dev_priv->wm.skl_latency[level];
> > uint_fixed_16_16_t method1, method2;
> > uint_fixed_16_16_t selected_result;
> > u32 res_blocks, res_lines, min_ddb_alloc = 0;
> > @@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct
> > intel_crtc_state *crtc_state,
> >
> > for (level = 0; level <= max_level; level++) {
> > struct skl_wm_level *result = &levels[level];
> > + u32 latency = dev_priv->wm.skl_latency[level];
> >
> > - skl_compute_plane_wm(crtc_state, level, wm_params,
> > - result_prev, result);
> > + skl_compute_plane_wm(crtc_state, level, latency,
> > + wm_params, result_prev, result);
> >
> > result_prev = result;
> > }
> > --
> > 2.24.1.485.gad05a3d8e5
>
>
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
2020-03-10 14:54 ` Lisovskiy, Stanislav
@ 2020-03-10 20:44 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-10 20:44 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Tue, Mar 10, 2020 at 02:54:12PM +0000, Lisovskiy, Stanislav wrote:
> On Tue, 2020-03-10 at 16:32 +0200, Ville Syrjälä wrote:
> > On Mon, Mar 09, 2020 at 06:11:57PM +0200, Stanislav Lisovskiy wrote:
> > > We need to start passing memory latency as a
> > > parameter when calculating plane wm levels,
> > > as latency can get changed in different
> > > circumstances(for example with or without SAGV).
> > > So we need to be more flexible on that matter.
> > >
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> > > 1 file changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 8375054ba27d..c7928c870b0a 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct
> > > intel_crtc_state *crtc_state,
> > > int color_plane);
> > > static void skl_compute_plane_wm(const struct intel_crtc_state
> > > *crtc_state,
> > > int level,
> > > + u32 latency,
> >
> > So you didn't change the types?
>
> Yes, I saw your comment there - and looked into this, however I just
> wondered, does it make any sense do to that. The reason is because
> skl_latency is anyway defined as u16 in i915_drv.h, just as pri/spr/cur
> latencies, so wonder how this "unsigned int" going to fit into this.
> Should I maybe then change it to u16 - at least that would somehow
> comply with the current declarations.
It's u16 in the struct to not waste space. In the code it's just
a number so a sized type doesn't make all that much sense.
And I think most of the code uses int/unsigned int for it anyway.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
@ 2020-03-11 9:13 ` Stanislav Lisovskiy
[not found] ` <20200311163130.GC13686@intel.com>
1 sibling, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-11 9:13 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
v14: - total_affected_planes is no longer needed to check for ddb changes,
just as active_pipe_changes.
v15: - Fixed stupid mistake with uninitialized crtc in
skl_compute_sagv_mask.
v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
- Added return value to intel_compute_sagv_mask which call
intel_atomic_serialize_global_state in order to properly
propagate EDEADLCK to drm.
- Based on the discussion with Ville, removed active_pipe_changes
check and also there seems to be no need for checking
ddb_state_changes as well.
Instead we just iterate through crtcs in state - having
crtc in a state already guarantees that it is at least read-locked
Having additional flag to check if there actually were some plane
wm/ddb changes would be probably added later as an optimization.
- We can't get parent atomic state from crtc_state at commit stage
(nice drm feature), also propagating state through function call
chain seems to be overkill and not possible(cursor legacy updates)
Querying for bw_state object from global state is not possible as
it might get swapped with other global state.
So... just sticked can_sagv boolean into wm crtc state.
v17: - Skip inactive crtcs, when checking for SAGV-readiness.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 23 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 317 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 1 +
5 files changed, 321 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index b5f61463922f..4083adf4b432 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
+ /*
+ * Contains final SAGV decision based on current mask,
+ * to prevent doing the same job over and over again.
+ */
+ bool can_sagv;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f23c4d51c33..9e0058a78ea6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
drm_err(&dev_priv->drm,
@@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
@@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
-
dev_priv->active_pipes = state->active_pipes;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5e00e611f077..da0308b87dad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -669,11 +669,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fec89722be75..a3b55713fd61 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = state->base.dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc;
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
+ crtc = to_intel_crtc(crtc_state->uapi.crtc);
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
+ if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
return false;
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(crtc->pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3816,13 +3803,148 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
return false;
+ }
}
return true;
}
+static bool
+tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
+
+static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
+{
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+ int i;
+
+ /*
+ * If SAGV is not supported we just can't do anything
+ * not even set or reject SAGV points - just bail out.
+ * Thus avoid needless calculations.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return 0;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ bool pipe_sagv_enable;
+
+ new_bw_state = intel_bw_get_state(state);
+ old_bw_state = intel_bw_get_old_state(state);
+
+ if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return -EINVAL;
+ }
+
+ new_bw_state->sagv_calculated = false;
+
+ if (!new_crtc_state->hw.active)
+ continue;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
+ else
+ pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
+
+ if (pipe_sagv_enable)
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
+
+ if (!new_bw_state || !old_bw_state)
+ return 0;
+
+ new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
+ new_bw_state->sagv_calculated = true;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = new_bw_state->can_sagv;
+ }
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+ DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
+ state,
+ old_bw_state->pipe_sagv_reject,
+ new_bw_state->pipe_sagv_reject);
+
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_bw_state *bw_state;
+
+ if (!intel_has_sagv(dev_priv)) {
+ DRM_DEBUG_KMS("No SAGV support detected\n");
+ return false;
+ }
+
+ bw_state = intel_bw_get_state(state);
+
+ if (IS_ERR_OR_NULL(bw_state)) {
+ WARN(1, "Could not get bw_state\n");
+ return false;
+ }
+
+ if (bw_state->sagv_calculated)
+ goto out;
+
+ bw_state->can_sagv = intel_calculate_sagv_result(bw_state);
+ bw_state->sagv_calculated = true;
+
+out:
+ return bw_state->can_sagv;
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
@@ -4042,6 +4164,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
unsigned int latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4556,9 +4679,83 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ if (!level) {
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
+
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * If pipe is not active it can't affect SAGV rejection
+ * Checking it here is needed to leave only cases when
+ * alloc_size is 0 for any other reasons, except inactive
+ * pipe. As inactive pipe is fine, however having no ddb
+ * space available is already problematic - so need to
+ * to separate those.
+ */
+ if (!crtc_state->hw.active)
+ return true;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return false;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return false;
+ }
+ }
+ DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+ blocks, alloc_size);
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5140,11 +5337,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -5155,6 +5360,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5237,7 +5463,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5259,7 +5485,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5598,9 +5824,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
+ const struct skl_wm_level *old_wm_level, *new_wm_level;
+ u16 old_plane_res_l, new_plane_res_l;
+ u8 old_plane_res_b, new_plane_res_b;
+ u16 old_min_ddb_alloc, new_min_ddb_alloc;
+ int color_plane = 0;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
+ old_wm_level = skl_plane_wm_level(old_crtc_state, plane_id, 0, color_plane);
+ new_wm_level = skl_plane_wm_level(new_crtc_state, plane_id, 0, color_plane);
+
+ old_plane_res_l = old_wm_level->plane_res_l;
+ old_plane_res_b = old_wm_level->plane_res_b;
+
+ new_plane_res_l = new_wm_level->plane_res_l;
+ new_plane_res_b = new_wm_level->plane_res_b;
+
+ old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
+ new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue;
@@ -5624,7 +5866,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+ enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5634,7 +5876,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+ enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5648,12 +5890,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+ old_plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+ new_plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5663,12 +5905,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+ old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
- new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+ new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5829,6 +6071,10 @@ skl_compute_wm(struct intel_atomic_state *state)
return ret;
}
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5960,6 +6206,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..65743a4cbcf6 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-10 14:32 ` Ville Syrjälä
@ 2020-03-11 9:16 ` Stanislav Lisovskiy
1 sibling, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2020-03-11 9:16 UTC (permalink / raw)
To: intel-gfx
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
v2: Changed latency type from u32 to unsigned int(Ville Syrjälä)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..b632b6bb9c3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
drm_WARN_ON(&dev_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ unsigned int latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3)
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (9 preceding siblings ...)
2020-03-10 13:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-03-11 12:54 ` Patchwork
2020-03-11 14:20 ` Lisovskiy, Stanislav
2020-03-11 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4) Patchwork
11 siblings, 1 reply; 32+ messages in thread
From: Patchwork @ 2020-03-11 12:54 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/74461/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8117 -> Patchwork_16922
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16922 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16922, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16922:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@basic@modeset:
- fi-skl-6700k2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-guc/igt@kms_busy@basic@modeset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-guc/igt@kms_busy@basic@modeset.html
- fi-kbl-7500u: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-kbl-7500u/igt@kms_busy@basic@modeset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-kbl-7500u/igt@kms_busy@basic@modeset.html
- fi-cfl-8109u: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
Known issues
------------
Here are the changes found in Patchwork_16922 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-skl-6600u: [PASS][11] -> [INCOMPLETE][12] ([i915#1242] / [i915#198])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6600u/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6600u/igt@gem_exec_suspend@basic-s0.html
- fi-skl-6770hq: [PASS][13] -> [INCOMPLETE][14] ([i915#1242] / [i915#198])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-8700k: [PASS][15] -> [INCOMPLETE][16] ([i915#1242])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-guc: [PASS][17] -> [INCOMPLETE][18] ([i915#1242])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
* igt@kms_busy@basic@modeset:
- fi-cml-s: [PASS][19] -> [INCOMPLETE][20] ([i915#283])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cml-s/igt@kms_busy@basic@modeset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cml-s/igt@kms_busy@basic@modeset.html
- fi-cml-u2: [PASS][21] -> [INCOMPLETE][22] ([i915#283])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cml-u2/igt@kms_busy@basic@modeset.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cml-u2/igt@kms_busy@basic@modeset.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-apl-guc/igt@i915_selftest@live@execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-apl-guc/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-apl-guc: [DMESG-WARN][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
Participating hosts (49 -> 40)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-byt-clapper fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8117 -> Patchwork_16922
CI-20190529: 20190529
CI_DRM_8117: 39a97a79462bf47caf47d8e56e1027dcedb92bb9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16922: f580b31fefefdc4e3175f47241c52a92d538821a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f580b31fefef drm/i915: Enable SAGV support for Gen12
a94ebc238e1b drm/i915: Restrict qgv points which don't have enough bandwidth.
c8c7805a79f0 drm/i915: Rename bw_state to new_bw_state
d423ddd36f1b drm/i915: Added required new PCode commands
7dc425c57481 drm/i915: Refactor intel_can_enable_sagv
6468178f6e57 drm/i915: Add intel_bw_get_*_state helpers
f4d2893b925e drm/i915: Introduce skl_plane_wm_level accessor.
aad38ffe3258 drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3)
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
@ 2020-03-11 14:20 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-11 14:20 UTC (permalink / raw)
To: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7279 bytes --]
BAT failure is due to rather funny issue, with plane states, this is a true failure however
apparently now the reason is identified. The old code was lacking a proper plane state enumeration, which caused an issue once SAGV changes forced it to be executed in other place.
Best Regards,
Lisovskiy Stanislav
________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Wednesday, March 11, 2020 2:54:09 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/74461/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8117 -> Patchwork_16922
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16922 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16922, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16922:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@basic@modeset:
- fi-skl-6700k2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6700k2/igt@kms_busy@basic@modeset.html
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-guc/igt@kms_busy@basic@modeset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-guc/igt@kms_busy@basic@modeset.html
- fi-kbl-7500u: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-kbl-7500u/igt@kms_busy@basic@modeset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-kbl-7500u/igt@kms_busy@basic@modeset.html
- fi-cfl-8109u: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
Known issues
------------
Here are the changes found in Patchwork_16922 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-skl-6600u: [PASS][11] -> [INCOMPLETE][12] ([i915#1242] / [i915#198])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6600u/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6600u/igt@gem_exec_suspend@basic-s0.html
- fi-skl-6770hq: [PASS][13] -> [INCOMPLETE][14] ([i915#1242] / [i915#198])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-skl-6770hq/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-8700k: [PASS][15] -> [INCOMPLETE][16] ([i915#1242])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-8700k/igt@gem_exec_suspend@basic-s0.html
- fi-cfl-guc: [PASS][17] -> [INCOMPLETE][18] ([i915#1242])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cfl-guc/igt@gem_exec_suspend@basic-s0.html
* igt@kms_busy@basic@modeset:
- fi-cml-s: [PASS][19] -> [INCOMPLETE][20] ([i915#283])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cml-s/igt@kms_busy@basic@modeset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cml-s/igt@kms_busy@basic@modeset.html
- fi-cml-u2: [PASS][21] -> [INCOMPLETE][22] ([i915#283])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-cml-u2/igt@kms_busy@basic@modeset.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-cml-u2/igt@kms_busy@basic@modeset.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-apl-guc/igt@i915_selftest@live@execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-apl-guc/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-apl-guc: [DMESG-WARN][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8117/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
Participating hosts (49 -> 40)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-byt-clapper fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8117 -> Patchwork_16922
CI-20190529: 20190529
CI_DRM_8117: 39a97a79462bf47caf47d8e56e1027dcedb92bb9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16922: f580b31fefefdc4e3175f47241c52a92d538821a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f580b31fefef drm/i915: Enable SAGV support for Gen12
a94ebc238e1b drm/i915: Restrict qgv points which don't have enough bandwidth.
c8c7805a79f0 drm/i915: Rename bw_state to new_bw_state
d423ddd36f1b drm/i915: Added required new PCode commands
7dc425c57481 drm/i915: Refactor intel_can_enable_sagv
6468178f6e57 drm/i915: Add intel_bw_get_*_state helpers
f4d2893b925e drm/i915: Introduce skl_plane_wm_level accessor.
aad38ffe3258 drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16922/index.html
[-- Attachment #1.2: Type: text/html, Size: 13691 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4)
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
` (10 preceding siblings ...)
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
@ 2020-03-11 19:36 ` Patchwork
11 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-03-11 19:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev4)
URL : https://patchwork.freedesktop.org/series/74461/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8121 -> Patchwork_16931
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16931/index.html
Changes
-------
No changes found
Participating hosts (42 -> 42)
------------------------------
Additional (4): fi-skl-6770hq fi-ivb-3770 fi-skl-6600u fi-snb-2600
Missing (4): fi-ctg-p8600 fi-byt-clapper fi-tgl-y fi-bsw-cyan
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8121 -> Patchwork_16931
CI-20190529: 20190529
CI_DRM_8121: c2e15accdf0c2b6e8b766659acc8159dc19c8869 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16931: 8dbc69849096985e98cc18057afdf65fd56e9676 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8dbc69849096 drm/i915: Enable SAGV support for Gen12
17ff47d315f5 drm/i915: Restrict qgv points which don't have enough bandwidth.
c88f1fe1eaf8 drm/i915: Rename bw_state to new_bw_state
3c883855330f drm/i915: Added required new PCode commands
d9f13126f85f drm/i915: Refactor intel_can_enable_sagv
4e7b174c5c7c drm/i915: Add intel_bw_get_*_state helpers
aecca32ce817 drm/i915: Introduce skl_plane_wm_level accessor.
2831e00f5567 drm/i915: Start passing latency as parameter
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16931/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
[not found] ` <20200311160727.GA13686@intel.com>
@ 2020-03-13 8:42 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-13 8:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14147 bytes --]
>> static int
>> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>> {
>> @@ -4606,22 +4618,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>> */
>> for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
>> blocks = 0;
>> +
>> for_each_plane_id_on_crtc(crtc, plane_id) {
>> - const struct skl_plane_wm *wm =
>> - &crtc_state->wm.skl.optimal.planes[plane_id];
>> + const struct skl_wm_level *wm_level;
>> + const struct skl_wm_level *wm_uv_level;
>> + int color_plane = 0;
>These color_plane variables seems kinda pointless. I'd just pass 0/1 directly
>(pretty sure that's what we do elsewhere too).
Nope. I have a different view - if this is allowed here. 0/1 passed into function are just a magic
numbers with no meaning - that way you see at least what's the param name and it's meaning.
Again, _absolutely_ pointless arguing and potentially waste of time instead of fixing some real thing. Whether those are variables or constants, doesn't make this code better or worse.
>> /*
>> * We only disable the watermarks for each plane if
>> @@ -4732,9 +4765,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>> * planes must be enabled before the level will be used."
>> * So this is actually safe to do.
>> */
>> - if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
>> - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
>> - memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
>> + if (wm_level->min_ddb_alloc > total[plane_id] ||
>> + wm_uv_level->min_ddb_alloc > uv_total[plane_id])
>> + memset(&wm->wm[level], 0,
>> + sizeof(struct skl_wm_level));
> memset(wm_level, 0, sizeof(*wm_level)) ?
Again - memset(wm_level, 0, sizeof(*wm_level)) and memset(wm_level, 0, sizeof(struct skl_wm_level)) are absolutely identical constructs according to C standard.
And I know that you are going to say that sizeof(*wm_level) won't require to change type -
well if you are changing the code anyway, this is trivial.
If I have any freedom to express my point of view at all, I'm not going to fix that.
Why are we even wasting time for this kind of stuff? Aren't there more serious problems no?
I myself have already decades of experience in coding in a rather big projects and big companies and can say that those kind of nitpicks are completely useless waste of time.
Best Regards,
Lisovskiy Stanislav
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Wednesday, March 11, 2020 6:07:27 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
Subject: Re: [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
On Mon, Mar 09, 2020 at 06:11:58PM +0200, Stanislav Lisovskiy wrote:
> For future Gen12 SAGV implementation we need to
> seemlessly alter wm levels calculated, depending
> on whether we are allowed to enable SAGV or not.
>
> So this accessor will give additional flexibility
> to do that.
>
> Currently this accessor is still simply working
> as "pass-through" function. This will be changed
> in next coming patches from this series.
>
> v2: - plane_id -> plane->id(Ville Syrjälä)
> - Moved wm_level var to have more local scope
> (Ville Syrjälä)
> - Renamed yuv to color_plane(Ville Syrjälä) in
> skl_plane_wm_level
>
> v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
> - Changed colorplane id type from boolean to int as index
> (Ville Syrjälä)
> - Moved crtc_state param so that it is first now
> (Ville Syrjälä)
> - Moved wm_level declaration to tigher scope in
> skl_write_plane_wm(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
> 1 file changed, 67 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c7928c870b0a..c72fa59a8302 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4547,6 +4547,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static const struct skl_wm_level *
> +skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> + enum plane_id plane_id,
> + int level,
> + int color_plane)
> +{
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -4606,22 +4618,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> blocks = 0;
> +
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> + int color_plane = 0;
These color_plane variables seems kinda pointless. I'd just pass 0/1 directly
(pretty sure that's what we do elsewhere too).
> +
> + wm_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane);
> + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane + 1);
>
> if (plane_id == PLANE_CURSOR) {
> - if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
> + if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
> drm_WARN_ON(&dev_priv->drm,
> - wm->wm[level].min_ddb_alloc != U16_MAX);
> + wm_level->min_ddb_alloc != U16_MAX);
> blocks = U32_MAX;
> break;
> }
> continue;
> }
>
> - blocks += wm->wm[level].min_ddb_alloc;
> - blocks += wm->uv_wm[level].min_ddb_alloc;
> + blocks += wm_level->min_ddb_alloc;
> + blocks += wm_uv_level->min_ddb_alloc;
> }
>
> if (blocks <= alloc_size) {
> @@ -4644,10 +4663,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * proportional to its relative data rate.
> */
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> u64 rate;
> u16 extra;
> + int color_plane = 0;
> +
> + wm_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane);
> + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane + 1);
>
> if (plane_id == PLANE_CURSOR)
> continue;
> @@ -4663,7 +4688,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> + total[plane_id] = wm_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
>
> @@ -4674,7 +4699,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> - uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> + uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> @@ -4717,8 +4742,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> for_each_plane_id_on_crtc(crtc, plane_id) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
> + int color_plane = 0;
> +
> + wm_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane);
> + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
> + level, color_plane + 1);
>
> /*
> * We only disable the watermarks for each plane if
> @@ -4732,9 +4765,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> * planes must be enabled before the level will be used."
> * So this is actually safe to do.
> */
> - if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> - memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> + if (wm_level->min_ddb_alloc > total[plane_id] ||
> + wm_uv_level->min_ddb_alloc > uv_total[plane_id])
> + memset(&wm->wm[level], 0,
> + sizeof(struct skl_wm_level));
memset(wm_level, 0, sizeof(*wm_level)) ?
Hmm. Also wondering why we're not clearing wm_uv here as well. I suppose
it might not mater since the hw doesn't use wm_uv (and I fixed the
"did the wms change?" check to ignore it too). Bit might be nice to clear
it for consistency. Should be a separate patch though.
>
> /*
> * Wa_1408961008:icl, ehl
> @@ -4742,9 +4776,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> */
> if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> - wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> + wm_level = skl_plane_wm_level(crtc_state, plane_id,
> + 0, color_plane);
> + wm->wm[level].plane_res_b =
> + wm_level->plane_res_b;
> + wm->wm[level].plane_res_l =
> + wm_level->plane_res_l;
> + wm->wm[level].ignore_lines =
> + wm_level->ignore_lines;
I would suggest we want this to read something like:
const struct skl_wm_level *wm_level0 = skl_plane_wm_level(...)
wm_level->foo = wm_level0->foo;
...
And with those we can throw out the 'wm' variable from this loop as
well.
> }
> }
> }
> @@ -5358,8 +5397,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.plane_ddb_uv[plane_id];
>
> for (level = 0; level <= max_level; level++) {
> + const struct skl_wm_level *wm_level;
> + int color_plane = 0;
> +
> + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
> +
> skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> &wm->trans_wm);
> @@ -5392,8 +5436,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
>
> for (level = 0; level <= max_level; level++) {
> + const struct skl_wm_level *wm_level;
> + int color_plane = 0;
> +
> + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
> +
> skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> - &wm->wm[level]);
> + wm_level);
> }
> skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
[not found] ` <20200311160854.GB13686@intel.com>
@ 2020-03-13 8:49 ` Lisovskiy, Stanislav
2020-03-13 13:26 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-13 8:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4236 bytes --]
>> Add correspondent helpers to be able to get old/new bandwidth
>> global state object.
>>
>> v2: - Fixed typo in function call
>> v3: - Changed new functions naming to use convention proposed
>> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>Still nak on the rename.
Cool. Discuss it with Jani Nikula then, to have at least some common strategy on how to be picky on me.
Best Regards,
Lisovskiy Stanislav
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Wednesday, March 11, 2020 6:08:54 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
Subject: Re: [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
On Mon, Mar 09, 2020 at 06:11:59PM +0200, Stanislav Lisovskiy wrote:
> Add correspondent helpers to be able to get old/new bandwidth
> global state object.
>
> v2: - Fixed typo in function call
> v3: - Changed new functions naming to use convention proposed
> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
Still nak on the rename.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
> 2 files changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..bdad7476dc7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> return data_rate;
> }
>
> -static struct intel_bw_state *
> -intel_atomic_get_bw_state(struct intel_atomic_state *state)
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
> +
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_global_state *bw_state;
> @@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_atomic_get_bw_state(state);
> + bw_state = intel_bw_get_state(state);
> if (IS_ERR(bw_state))
> return PTR_ERR(bw_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index a8aa7624c5aa..b5f61463922f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -24,6 +24,15 @@ struct intel_bw_state {
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
>
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state);
> +
> void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-03-13 8:49 ` Lisovskiy, Stanislav
@ 2020-03-13 13:26 ` Ville Syrjälä
2020-03-13 13:57 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-13 13:26 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Fri, Mar 13, 2020 at 08:49:30AM +0000, Lisovskiy, Stanislav wrote:
> >> Add correspondent helpers to be able to get old/new bandwidth
> >> global state object.
> >>
> >> v2: - Fixed typo in function call
> >> v3: - Changed new functions naming to use convention proposed
> >> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>
> >Still nak on the rename.
>
> Cool. Discuss it with Jani Nikula then, to have at least some common strategy on how to be picky on me.
The strategy is either rename all of these functions or none so that we
don't end up with random inconsistencies all over the place.
>
> Best Regards,
>
> Lisovskiy Stanislav
> ________________________________
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, March 11, 2020 6:08:54 PM
> To: Lisovskiy, Stanislav
> Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
> Subject: Re: [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
>
> On Mon, Mar 09, 2020 at 06:11:59PM +0200, Stanislav Lisovskiy wrote:
> > Add correspondent helpers to be able to get old/new bandwidth
> > global state object.
> >
> > v2: - Fixed typo in function call
> > v3: - Changed new functions naming to use convention proposed
> > by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>
> Still nak on the rename.
>
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
> > 2 files changed, 39 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 58b264bc318d..bdad7476dc7b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > return data_rate;
> > }
> >
> > -static struct intel_bw_state *
> > -intel_atomic_get_bw_state(struct intel_atomic_state *state)
> > +struct intel_bw_state *
> > +intel_bw_get_old_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_new_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
> > +
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_state(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_global_state *bw_state;
> > @@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> > old_active_planes == new_active_planes)
> > continue;
> >
> > - bw_state = intel_atomic_get_bw_state(state);
> > + bw_state = intel_bw_get_state(state);
> > if (IS_ERR(bw_state))
> > return PTR_ERR(bw_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index a8aa7624c5aa..b5f61463922f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -24,6 +24,15 @@ struct intel_bw_state {
> >
> > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> >
> > +struct intel_bw_state *
> > +intel_bw_get_old_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_new_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_state(struct intel_atomic_state *state);
> > +
> > void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> > int intel_bw_init(struct drm_i915_private *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-03-13 13:26 ` Ville Syrjälä
@ 2020-03-13 13:57 ` Lisovskiy, Stanislav
2020-03-13 14:14 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-13 13:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6077 bytes --]
>> >> Add correspondent helpers to be able to get old/new bandwidth
>> >> global state object.
>> >>
>> >> v2: - Fixed typo in function call
>> >> v3: - Changed new functions naming to use convention proposed
>> >> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>>
>> >Still nak on the rename.
>>
>> Cool. Discuss it with Jani Nikula then, to have at least some common strategy on how to be picky on me.
>The strategy is either rename all of these functions or none so that we
>don't end up with random inconsistencies all over the place.
Initially Jani Nikula wrote that he is trying to encourage people to call functions
starting with the module name. OK. Done it.
You say that the opposite and nack. Now it just turns out that it is again _me_ - poor minded, who didn't understand that I need to rename
all functions now here as well, including those completely unrelated to that patch.
Sure - we have "plenty" of time!
Or may be I shouldn't rename - kind of confused now.
Best Regards,
Lisovskiy Stanislav
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Friday, March 13, 2020 3:26:11 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
Subject: Re: [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
On Fri, Mar 13, 2020 at 08:49:30AM +0000, Lisovskiy, Stanislav wrote:
> >> Add correspondent helpers to be able to get old/new bandwidth
> >> global state object.
> >>
> >> v2: - Fixed typo in function call
> >> v3: - Changed new functions naming to use convention proposed
> >> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>
> >Still nak on the rename.
>
> Cool. Discuss it with Jani Nikula then, to have at least some common strategy on how to be picky on me.
The strategy is either rename all of these functions or none so that we
don't end up with random inconsistencies all over the place.
>
> Best Regards,
>
> Lisovskiy Stanislav
> ________________________________
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, March 11, 2020 6:08:54 PM
> To: Lisovskiy, Stanislav
> Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
> Subject: Re: [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
>
> On Mon, Mar 09, 2020 at 06:11:59PM +0200, Stanislav Lisovskiy wrote:
> > Add correspondent helpers to be able to get old/new bandwidth
> > global state object.
> >
> > v2: - Fixed typo in function call
> > v3: - Changed new functions naming to use convention proposed
> > by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>
> Still nak on the rename.
>
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 33 ++++++++++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++
> > 2 files changed, 39 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 58b264bc318d..bdad7476dc7b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > return data_rate;
> > }
> >
> > -static struct intel_bw_state *
> > -intel_atomic_get_bw_state(struct intel_atomic_state *state)
> > +struct intel_bw_state *
> > +intel_bw_get_old_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_new_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
> > +
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_state(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_global_state *bw_state;
> > @@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> > old_active_planes == new_active_planes)
> > continue;
> >
> > - bw_state = intel_atomic_get_bw_state(state);
> > + bw_state = intel_bw_get_state(state);
> > if (IS_ERR(bw_state))
> > return PTR_ERR(bw_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index a8aa7624c5aa..b5f61463922f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -24,6 +24,15 @@ struct intel_bw_state {
> >
> > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> >
> > +struct intel_bw_state *
> > +intel_bw_get_old_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_new_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_bw_get_state(struct intel_atomic_state *state);
> > +
> > void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> > int intel_bw_init(struct drm_i915_private *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers
2020-03-13 13:57 ` Lisovskiy, Stanislav
@ 2020-03-13 14:14 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-13 14:14 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Fri, Mar 13, 2020 at 01:57:58PM +0000, Lisovskiy, Stanislav wrote:
> >> >> Add correspondent helpers to be able to get old/new bandwidth
> >> >> global state object.
> >> >>
> >> >> v2: - Fixed typo in function call
> >> >> v3: - Changed new functions naming to use convention proposed
> >> >> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
> >>
> >> >Still nak on the rename.
> >>
> >> Cool. Discuss it with Jani Nikula then, to have at least some common strategy on how to be picky on me.
>
> >The strategy is either rename all of these functions or none so that we
> >don't end up with random inconsistencies all over the place.
>
>
> Initially Jani Nikula wrote that he is trying to encourage people to call functions
>
> starting with the module name. OK. Done it.
>
>
> You say that the opposite and nack. Now it just turns out that it is again _me_ - poor minded, who didn't understand that I need to rename
>
> all functions now here as well, including those completely unrelated to that patch.
>
> Sure - we have "plenty" of time!
>
>
> Or may be I shouldn't rename - kind of confused now.
If you do a mass rename do it as a separate series.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
[not found] ` <20200311163130.GC13686@intel.com>
@ 2020-03-18 11:52 ` Lisovskiy, Stanislav
2020-03-18 12:50 ` Ville Syrjälä
2020-03-20 12:51 ` Lisovskiy, Stanislav
1 sibling, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-18 11:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 37767 bytes --]
>> @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
>> return ret;
>> }
>>
>> + ret = intel_compute_sagv_mask(state);
>> + if (ret)
>> + return ret;
> This seems too early. We haven't even computed the ddb yet.
I was thinking about our discussion last week and actually I think there are simply two ways how
to do it.
1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
and then act accordingly.
However one thing to consider here: as you said besides the minimal requirements for each plane
(with or without sagv) there is an extra space being allocated in proportion to plane data rate,
however here we are actually hitting the prioritization issue - i.e we need to decide whether
it is more important to have SAGV or to have more extra space allocated to different planes
proportionally to their needs.
So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
So that way we would be more often power efficient but but planes get less extra ddb space.
2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
because that extra space is not actually distributed evenly but in proportion to data rate of each
plane, which means that some planes might lack space for SAGV theoretically, because some might be
getting more or less depending on the data_rate/total_data_rate ratio.
My position is such that I'm really not like "my approach should always win" here, but more searching for
solution which is more correct from product point of view.
Also could be that it doesn't really matter which approach we do take now,, but matter more like
that how fast we deliver. Because the actual outcome difference between two
might be minor, while time overhead for changing the approach could be major.
Best Regards,
Lisovskiy Stanislav
________________________________
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Wednesday, March 11, 2020 6:31:30 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper, Matthew D
Subject: Re: [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark calculation algorithm to
> attempt to calculate Level 0 watermark
> with added sagv block time latency and
> check if it fits in DBuf in order to
> determine if SAGV can be enabled already
> at this stage, just as BSpec 49325 states.
> if that fails rollback to usual Level 0
> latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
>
> v3: Rebased the patch
>
> v4: - Added back interlaced check for Gen12 and
> added separate function for TGL SAGV check
> (thanks to James Ausmus for spotting)
> - Removed unneeded gen check
> - Extracted Gen12 SAGV decision making code
> to a separate function from skl_compute_wm
>
> v5: - Added SAGV global state to dev_priv, because
> we need to track all pipes, not only those
> in atomic state. Each pipe has now correspondent
> bit mask reflecting, whether it can tolerate
> SAGV or not(thanks to Ville Syrjala for suggestions).
> - Now using active flag instead of enable in crc
> usage check.
>
> v6: - Fixed rebase conflicts
>
> v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> calls when copying level 0 water marks for enabled SAGV, to
> fix this now simply using that field right away, without copying,
> for that introduced a new wm_level accessor which decides which
> wm_level to return based on SAGV state.
>
> v8: - Protect crtc_sagv_mask same way as we do for other global state
> changes: i.e check if changes are needed, then grab all crtc locks
> to serialize the changes(Ville Syrjälä)
> - Add crtc_sagv_mask caching in order to avoid needless recalculations
> (Matthew Roper)
> - Put back Gen12 SAGV switch in order to get it enabled in separate
> patch(Matthew Roper)
> - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> - Check if there are no active pipes in intel_can_enable_sagv
> instead of platform specific functions(Matthew Roper), same
> for intel_has_sagv check.
>
> v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> - Extracted skl_plane_wm_level function and passing latency to
> separate patches(Ville Syrjälä)
> - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> (Ville Syrjälä)
> - Now using simple assignment for sagv_wm0 as it contains only
> pod types and no pointers(Ville Syrjälä)
> - Fixed intel_can_enable_sagv not to do double duty, now it only
> check SAGV bits by ANDing those between local and global state.
> The SAGV masks are now computed after watermarks are available,
> in order to be able to figure out if ddb ranges are fitting nicely.
> (Ville Syrjälä)
> - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> when using skl_plane_wm_level accessor, as we had previously for
> Gen11+ color plane and regular wm levels, so probably both
> has to be recalculated with additional SAGV block time for Level 0.
>
> v10: - Starting to use new global state for storing pipe_sagv_mask
>
> v11: - Fixed rebase conflict with recent drm-tip
> - Check if we really need to recalculate SAGV mask, otherwise
> bail out without making any changes.
> - Use cached SAGV result, instead of recalculating it everytime,
> if bw_state hasn't changed.
>
> v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> if we don't recalculated watermarks, bw_state is not recalculated,
> thus leading to SAGV state not recalculated by the commit state,
> which is still calling intel_can_enable_sagv function. Fix that
> by just analyzing the current global bw_state object - because
> we simply have no other objects related to that.
>
> v13: - Rebased, fixed warnings regarding long lines
> - Changed function call sites from intel_atomic_bw* to
> intel_wb_* as was suggested.(Jani Nikula)
> - Taken ddb_state_changed and bw_state_changed into use.
>
> v14: - total_affected_planes is no longer needed to check for ddb changes,
> just as active_pipe_changes.
>
> v15: - Fixed stupid mistake with uninitialized crtc in
> skl_compute_sagv_mask.
>
> v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> - Added return value to intel_compute_sagv_mask which call
> intel_atomic_serialize_global_state in order to properly
> propagate EDEADLCK to drm.
> - Based on the discussion with Ville, removed active_pipe_changes
> check and also there seems to be no need for checking ddb_state_changes
> as well. Instead we just iterate through crtcs in state - having
> crtc in a state already guarantees that it is at least read-locked
> Having additional flag to check if there actually were some plane
> wm/ddb changes would be probably added later as an optimization.
> - We can't get parent atomic state from crtc_state at commit stage
> (nice drm feature), also propagating state through function call
> chain seems to be overkill and not possible(cursor legacy updates)
> Querying for bw_state object from global state is not possible as
> it might get swapped with other global state.
> So... just sticked can_sagv boolean into wm crtc state.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> 5 files changed, 318 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index b5f61463922f..4083adf4b432 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -18,6 +18,24 @@ struct intel_crtc_state;
> struct intel_bw_state {
> struct intel_global_state base;
>
> + /*
> + * Contains a bit mask, used to determine, whether correspondent
> + * pipe allows SAGV or not.
> + */
> + u8 pipe_sagv_reject;
> +
> + /*
> + * Used to determine if we already had calculated
> + * SAGV mask for this state once.
> + */
> + bool sagv_calculated;
Why would we even attempt to calculate it many times?
> +
> + /*
> + * Contains final SAGV decision based on current mask,
> + * to prevent doing the same job over and over again.
> + */
> + bool can_sagv;
This is redundant since it's just sagv_reject==0.
> +
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8f23c4d51c33..9e0058a78ea6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]))
> + &sw_plane_wm->wm[level]) ||
> + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> + &sw_plane_wm->sagv_wm0) &&
> + (level == 0)))
Pointless parens. Also we should do the check as
'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
level != 0.
I guess we can't read out sagv state due to the silly pcode interface?
> continue;
>
> drm_err(&dev_priv->drm,
> @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]))
> + &sw_plane_wm->wm[level]) ||
> + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> + &sw_plane_wm->sagv_wm0) &&
> + (level == 0)))
> continue;
>
> drm_err(&dev_priv->drm,
> @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * SKL workaround: bspec recommends we disable the SAGV when we
> * have more then one pipe enabled
> */
> - if (!intel_can_enable_sagv(state))
> - intel_disable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (!intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
> + }
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset)
> intel_verify_planes(state);
>
> - if (state->modeset && intel_can_enable_sagv(state))
> - intel_enable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (state->modeset && intel_can_enable_sagv(state))
> + intel_enable_sagv(dev_priv);
> + }
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
>
> if (state->global_state_changed) {
> assert_global_state_locked(dev_priv);
> -
> dev_priv->active_pipes = state->active_pipes;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5e00e611f077..da0308b87dad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -669,11 +669,14 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm0;
> + struct skl_wm_level uv_sagv_wm0;
> bool is_planar;
> };
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> + bool can_sagv;
> };
>
> enum vlv_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c72fa59a8302..f598b55f4abc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -43,6 +43,7 @@
> #include "i915_fixed.h"
> #include "i915_irq.h"
> #include "i915_trace.h"
> +#include "display/intel_bw.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> #include "../../../platform/x86/intel_ips.h"
> @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> }
>
> -static bool
> +bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> /* HACK! */
> @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
This extraction looks to be trivially done as a separate patch.
> {
> - struct drm_device *dev = state->base.dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_crtc *crtc;
> struct intel_plane *plane;
> - struct intel_crtc_state *crtc_state;
> - enum pipe pipe;
> int level, latency;
>
> - if (!intel_has_sagv(dev_priv))
> - return false;
> -
> - /*
> - * If there are no active CRTCs, no additional checks need be performed
> - */
> - if (hweight8(state->active_pipes) == 0)
> - return true;
> + crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - /*
> - * SKL+ workaround: bspec recommends we disable SAGV when we have
> - * more then one pipe enabled
> - */
> - if (hweight8(state->active_pipes) > 1)
> + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> return false;
>
> - /* Since we're now guaranteed to only have one active CRTC... */
> - pipe = ffs(state->active_pipes) - 1;
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> -
> - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> + pipe_name(crtc->pipe));
> return false;
> + }
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> struct skl_plane_wm *wm =
> @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> * incur memory latencies higher than sagv_block_time_us we
> * can't enable SAGV.
> */
> - if (latency < dev_priv->sagv_block_time_us)
> + if (latency < dev_priv->sagv_block_time_us) {
> + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> return false;
> + }
> }
>
> return true;
> }
>
> +static bool
> +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> +
> +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> +{
> + return bw_state->pipe_sagv_reject == 0;
> +}
> +
> +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> +{
> + int ret;
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> + int i;
> +
> + /*
> + * If SAGV is not supported we just can't do anything
> + * not even set or reject SAGV points - just bail out.
> + * Thus avoid needless calculations.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return 0;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + bool pipe_sagv_enable;
> +
> + new_bw_state = intel_bw_get_state(state);
> + old_bw_state = intel_bw_get_old_state(state);
> +
> + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> + WARN(1, "Could not get bw_state\n");
> + return -EINVAL;
What is this?
> + }
> +
> + new_bw_state->sagv_calculated = false;
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> + else
> + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> +
> + if (pipe_sagv_enable)
> + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> + else
> + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> + }
> +
> + if (!new_bw_state || !old_bw_state)
> + return 0;
> +
> + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> + new_bw_state->sagv_calculated = true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> +
> + /*
> + * Due to drm limitation at commit state, when
> + * changes are written the whole atomic state is
> + * zeroed away => which prevents from using it,
> + * so just sticking it into pipe wm state for
> + * keeping it simple - anyway this is related to wm.
> + * Proper way in ideal universe would be of course not
> + * to lose parent atomic state object from child crtc_state,
> + * and stick to OOP programming principles, which had been
> + * scientifically proven to work.
> + */
> + pipe_wm->can_sagv = new_bw_state->can_sagv;
I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
what it does.
> + }
> +
> + /*
> + * For SAGV we need to account all the pipes,
> + * not only the ones which are in state currently.
> + * Grab all locks if we detect that we are actually
> + * going to do something.
> + */
> + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> + state,
> + old_bw_state->pipe_sagv_reject,
> + new_bw_state->pipe_sagv_reject);
> +
> + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> + if (ret) {
> + DRM_DEBUG_KMS("Could not serialize global state\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * This function to be used before swap state
> + */
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_bw_state *bw_state;
> +
> + if (!intel_has_sagv(dev_priv)) {
> + DRM_DEBUG_KMS("No SAGV support detected\n");
> + return false;
> + }
> +
> + bw_state = intel_bw_get_state(state);
> +
> + if (IS_ERR_OR_NULL(bw_state)) {
It can't be NULL. And if you get an error you must propagate it upwards.
> + WARN(1, "Could not get bw_state\n");
> + return false;
> + }
> +
> + if (bw_state->sagv_calculated)
> + goto out;
> +
> + bw_state->can_sagv = intel_calculate_sagv_result(bw_state);
> + bw_state->sagv_calculated = true;
> +
> +out:
> + return bw_state->can_sagv;
> +}
> +
> /*
> * Calculate initial DBuf slice offset, based on slice size
> * and mask(i.e if slice size is 1024 and second slice is enabled
> @@ -4042,6 +4161,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> u32 latency = dev_priv->wm.skl_latency[level];
>
> skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> +
Spurious whitespace.
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4556,9 +4676,83 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> + if (!level) {
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
Why is this here when &crtc_state->wm.skl.optimal is already being used
higher up?
> +
> + if (pipe_wm->can_sagv)
> + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> + }
> +
> return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> }
>
> +static bool
> +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_crtc *crtc = crtc_state->uapi.crtc;
Pls don't use the annoying drm_ types.
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> + u16 alloc_size;
> + u64 total_data_rate;
> + enum plane_id plane_id;
> + int num_active;
> + u64 plane_data_rate[I915_MAX_PLANES] = {};
> + u32 blocks;
> +
> + /*
> + * If pipe is not active it can't affect SAGV rejection
> + * Checking it here is needed to leave only cases when
> + * alloc_size is 0 for any other reasons, except inactive
> + * pipe. As inactive pipe is fine, however having no ddb
> + * space available is already problematic - so need to
> + * to separate those.
> + */
Can't figure out what this comment is trying to say or why it's here.
> + if (!crtc_state->hw.active)
> + return true;
> +
> + /*
> + * No need to check gen here, we call this only for gen12
> + */
> + total_data_rate =
> + icl_get_total_relative_data_rate(crtc_state,
> + plane_data_rate);
> +
> + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> + total_data_rate,
> + alloc, &num_active);
> + alloc_size = skl_ddb_entry_size(alloc);
Don't we already have this in the crtc state?
> + if (alloc_size == 0)
> + return false;
I don't think that can happen.
> +
> + /*
> + * Do check if we can fit L0 + sagv_block_time and
> + * disable SAGV if we can't.
> + */
> + blocks = 0;
> + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + /*
> + * The only place, where we can't use skl_plane_wm_level
> + * accessor, because if actually calls intel_can_enable_sagv
> + * which depends on that function.
> + */
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + blocks += wm->sagv_wm0.min_ddb_alloc;
> + blocks += wm->uv_sagv_wm0.min_ddb_alloc;
> +
> + if (blocks > alloc_size) {
> + DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
> + alloc_size, blocks, pipe_name(intel_crtc->pipe));
> + return false;
> + }
> + }
> + DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
> + blocks, alloc_size);
> + return true;
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -5140,11 +5334,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> - struct skl_wm_level *levels)
> + struct skl_plane_wm *plane_wm,
> + bool yuv)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> + /*
> + * Check which kind of plane is it and based on that calculate
> + * correspondent WM levels.
> + */
> + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
> struct skl_wm_level *result_prev = &levels[0];
> + struct skl_wm_level *sagv_wm = yuv ?
> + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> @@ -5155,6 +5357,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>
> result_prev = result;
> }
> + /*
> + * For Gen12 if it is an L0 we need to also
> + * consider sagv_block_time when calculating
> + * L0 watermark - we will need that when making
> + * a decision whether enable SAGV or not.
> + * For older gens we agreed to copy L0 value for
> + * compatibility.
> + */
> + if ((INTEL_GEN(dev_priv) >= 12)) {
> + u32 latency = dev_priv->wm.skl_latency[0];
> +
> + latency += dev_priv->sagv_block_time_us;
> + skl_compute_plane_wm(crtc_state, 0, latency,
> + wm_params, &levels[0],
> + sagv_wm);
> + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> + } else {
> + /* Since all members are POD */
> + *sagv_wm = levels[0];
> + }
I was thinking more along the lines of
skl_compute_wm_levels();
skl_compute_transition_wm();
+ skl_compute_sagv_wm();
> }
>
> static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> @@ -5237,7 +5460,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> skl_compute_transition_wm(crtc_state, &wm_params, wm);
>
> return 0;
> @@ -5259,7 +5482,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
>
> return 0;
> }
> @@ -5598,9 +5821,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> enum plane_id plane_id = plane->id;
> const struct skl_plane_wm *old_wm, *new_wm;
> + const struct skl_wm_level *old_wm_level, *new_wm_level;
> + u16 old_plane_res_l, new_plane_res_l;
> + u8 old_plane_res_b, new_plane_res_b;
> + u16 old_min_ddb_alloc, new_min_ddb_alloc;
> + int color_plane = 0;
>
> old_wm = &old_pipe_wm->planes[plane_id];
> new_wm = &new_pipe_wm->planes[plane_id];
> + old_wm_level = skl_plane_wm_level(old_crtc_state, plane_id, 0, color_plane);
> + new_wm_level = skl_plane_wm_level(new_crtc_state, plane_id, 0, color_plane);
> +
> + old_plane_res_l = old_wm_level->plane_res_l;
> + old_plane_res_b = old_wm_level->plane_res_b;
> +
> + new_plane_res_l = new_wm_level->plane_res_l;
> + new_plane_res_b = new_wm_level->plane_res_b;
> +
> + old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
> + new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
>
> if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
> continue;
> @@ -5624,7 +5863,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
> " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
> plane->base.base.id, plane->base.name,
> - enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
> + enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
> enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
> enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
> enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
> @@ -5634,7 +5873,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
> enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
>
> - enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
> + enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
> enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
> enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
> enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
> @@ -5648,12 +5887,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> plane->base.base.id, plane->base.name,
> - old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
> + old_plane_res_b, old_wm->wm[1].plane_res_b,
> old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
> old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
> old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
> old_wm->trans_wm.plane_res_b,
> - new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
> + new_plane_res_b, new_wm->wm[1].plane_res_b,
> new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
> new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
> new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> @@ -5663,12 +5902,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> plane->base.base.id, plane->base.name,
> - old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
> + old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
> old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
> old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
> old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
> old_wm->trans_wm.min_ddb_alloc,
> - new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
> + new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
> new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
> new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
Here too I think the sagv wm should be treated more or less like the
transition wm (ie. just printed as an extra).
> @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
> return ret;
> }
>
> + ret = intel_compute_sagv_mask(state);
> + if (ret)
> + return ret;
This seems too early. We haven't even computed the ddb yet.
> +
> ret = skl_compute_ddb(state);
> if (ret)
> return ret;
> @@ -5960,6 +6203,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> val = I915_READ(CUR_WM(pipe, level));
>
> skl_wm_level_from_reg_val(val, &wm->wm[level]);
> + if (level == 0)
> + memcpy(&wm->sagv_wm0, &wm->wm[level],
> + sizeof(struct skl_wm_level));
> }
>
> if (plane_id != PLANE_CURSOR)
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index d60a85421c5a..65743a4cbcf6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -42,6 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-18 11:52 ` Lisovskiy, Stanislav
@ 2020-03-18 12:50 ` Ville Syrjälä
2020-03-19 13:09 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-18 12:50 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, Mar 18, 2020 at 11:52:13AM +0000, Lisovskiy, Stanislav wrote:
> >> @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
> >> return ret;
> >> }
> >>
> >> + ret = intel_compute_sagv_mask(state);
> >> + if (ret)
> >> + return ret;
>
> > This seems too early. We haven't even computed the ddb yet.
>
>
> I was thinking about our discussion last week and actually I think there are simply two ways how
>
> to do it.
>
>
> 1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
>
> based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
>
> already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
>
> and then act accordingly.
>
> However one thing to consider here: as you said besides the minimal requirements for each plane
>
> (with or without sagv) there is an extra space being allocated in proportion to plane data rate,
>
> however here we are actually hitting the prioritization issue - i.e we need to decide whether
>
> it is more important to have SAGV or to have more extra space allocated to different planes
>
> proportionally to their needs.
>
> So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
>
> on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
>
> So that way we would be more often power efficient but but planes get less extra ddb space.
>
>
> 2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
>
> data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
>
> Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
>
> using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
>
> because that extra space is not actually distributed evenly but in proportion to data rate of each
>
> plane, which means that some planes might lack space for SAGV theoretically, because some might be
>
> getting more or less depending on the data_rate/total_data_rate ratio.
>
>
> My position is such that I'm really not like "my approach should always win" here, but more searching for
>
> solution which is more correct from product point of view.
>
>
> Also could be that it doesn't really matter which approach we do take now,, but matter more like
>
> that how fast we deliver. Because the actual outcome difference between two
>
> might be minor, while time overhead for changing the approach could be major.
Pls fix your MUA. Really hard to read this.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-18 12:50 ` Ville Syrjälä
@ 2020-03-19 13:09 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-19 13:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Mar 18, 2020 at 02:50:55PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 18, 2020 at 11:52:13AM +0000, Lisovskiy, Stanislav wrote:
> > >> @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
> > >> return ret;
> > >> }
> > >>
> > >> + ret = intel_compute_sagv_mask(state);
> > >> + if (ret)
> > >> + return ret;
> >
> > > This seems too early. We haven't even computed the ddb yet.
> >
> >
> > I was thinking about our discussion last week and actually I think there are simply two ways how
> >
> > to do it.
> >
> >
> > 1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
> >
> > based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
> >
> > already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
> >
> > and then act accordingly.
> >
> > However one thing to consider here: as you said besides the minimal requirements for each plane
> >
> > (with or without sagv) there is an extra space being allocated in proportion to plane data rate,
> >
> > however here we are actually hitting the prioritization issue - i.e we need to decide whether
> >
> > it is more important to have SAGV or to have more extra space allocated to different planes
> >
> > proportionally to their needs.
> >
> > So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
> >
> > on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
> >
> > So that way we would be more often power efficient but but planes get less extra ddb space.
> >
> >
> > 2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
> >
> > data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
> >
> > Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
> >
> > using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
> >
> > because that extra space is not actually distributed evenly but in proportion to data rate of each
> >
> > plane, which means that some planes might lack space for SAGV theoretically, because some might be
> >
> > getting more or less depending on the data_rate/total_data_rate ratio.
> >
> >
> > My position is such that I'm really not like "my approach should always win" here, but more searching for
> >
> > solution which is more correct from product point of view.
> >
> >
> > Also could be that it doesn't really matter which approach we do take now,, but matter more like
> >
> > that how fast we deliver. Because the actual outcome difference between two
> >
> > might be minor, while time overhead for changing the approach could be major.
>
> Pls fix your MUA. Really hard to read this.
>
> --
> Ville Syrjälä
> Intel
I was thinking about our discussion last week and actually I think there are simply two ways how
to do it.
1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
and then act accordingly.
However one thing to consider here: as you said besides the minimal requirements for each plane
(with or without sagv) there is an extra space being allocated in proportion to plane data rate,
however here we are actually hitting the prioritization issue - i.e we need to decide whether
it is more important to have SAGV or to have more extra space allocated to different planes
proportionally to their needs.
So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
So that way we would be more often power efficient but but planes get less extra ddb space.
2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
because that extra space is not actually distributed evenly but in proportion to data rate of each
plane, which means that some planes might lack space for SAGV theoretically, because some might be
getting more or less depending on the data_rate/total_data_rate ratio.
My position is such that I'm really not like "my approach should always win" here, but more searching for
solution which is more correct from product point of view.
Also could be that it doesn't really matter which approach we do take now,, but matter more like
that how fast we deliver. Because the actual outcome difference between two
might be minor, while time overhead for changing the approach could be major.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
[not found] ` <20200311163130.GC13686@intel.com>
2020-03-18 11:52 ` Lisovskiy, Stanislav
@ 2020-03-20 12:51 ` Lisovskiy, Stanislav
2020-03-23 14:18 ` Ville Syrjälä
1 sibling, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-20 12:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Mar 11, 2020 at 06:31:30PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> >
> > v2:
> > - Rework watermark calculation algorithm to
> > attempt to calculate Level 0 watermark
> > with added sagv block time latency and
> > check if it fits in DBuf in order to
> > determine if SAGV can be enabled already
> > at this stage, just as BSpec 49325 states.
> > if that fails rollback to usual Level 0
> > latency and disable SAGV.
> > - Remove unneeded tabs(James Ausmus)
> >
> > v3: Rebased the patch
> >
> > v4: - Added back interlaced check for Gen12 and
> > added separate function for TGL SAGV check
> > (thanks to James Ausmus for spotting)
> > - Removed unneeded gen check
> > - Extracted Gen12 SAGV decision making code
> > to a separate function from skl_compute_wm
> >
> > v5: - Added SAGV global state to dev_priv, because
> > we need to track all pipes, not only those
> > in atomic state. Each pipe has now correspondent
> > bit mask reflecting, whether it can tolerate
> > SAGV or not(thanks to Ville Syrjala for suggestions).
> > - Now using active flag instead of enable in crc
> > usage check.
> >
> > v6: - Fixed rebase conflicts
> >
> > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> > calls when copying level 0 water marks for enabled SAGV, to
> > fix this now simply using that field right away, without copying,
> > for that introduced a new wm_level accessor which decides which
> > wm_level to return based on SAGV state.
> >
> > v8: - Protect crtc_sagv_mask same way as we do for other global state
> > changes: i.e check if changes are needed, then grab all crtc locks
> > to serialize the changes(Ville Syrjälä)
> > - Add crtc_sagv_mask caching in order to avoid needless recalculations
> > (Matthew Roper)
> > - Put back Gen12 SAGV switch in order to get it enabled in separate
> > patch(Matthew Roper)
> > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> > - Check if there are no active pipes in intel_can_enable_sagv
> > instead of platform specific functions(Matthew Roper), same
> > for intel_has_sagv check.
> >
> > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> > - Extracted skl_plane_wm_level function and passing latency to
> > separate patches(Ville Syrjälä)
> > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> > (Ville Syrjälä)
> > - Now using simple assignment for sagv_wm0 as it contains only
> > pod types and no pointers(Ville Syrjälä)
> > - Fixed intel_can_enable_sagv not to do double duty, now it only
> > check SAGV bits by ANDing those between local and global state.
> > The SAGV masks are now computed after watermarks are available,
> > in order to be able to figure out if ddb ranges are fitting nicely.
> > (Ville Syrjälä)
> > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> > when using skl_plane_wm_level accessor, as we had previously for
> > Gen11+ color plane and regular wm levels, so probably both
> > has to be recalculated with additional SAGV block time for Level 0.
> >
> > v10: - Starting to use new global state for storing pipe_sagv_mask
> >
> > v11: - Fixed rebase conflict with recent drm-tip
> > - Check if we really need to recalculate SAGV mask, otherwise
> > bail out without making any changes.
> > - Use cached SAGV result, instead of recalculating it everytime,
> > if bw_state hasn't changed.
> >
> > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> > if we don't recalculated watermarks, bw_state is not recalculated,
> > thus leading to SAGV state not recalculated by the commit state,
> > which is still calling intel_can_enable_sagv function. Fix that
> > by just analyzing the current global bw_state object - because
> > we simply have no other objects related to that.
> >
> > v13: - Rebased, fixed warnings regarding long lines
> > - Changed function call sites from intel_atomic_bw* to
> > intel_wb_* as was suggested.(Jani Nikula)
> > - Taken ddb_state_changed and bw_state_changed into use.
> >
> > v14: - total_affected_planes is no longer needed to check for ddb changes,
> > just as active_pipe_changes.
> >
> > v15: - Fixed stupid mistake with uninitialized crtc in
> > skl_compute_sagv_mask.
> >
> > v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> > flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> > - Added return value to intel_compute_sagv_mask which call
> > intel_atomic_serialize_global_state in order to properly
> > propagate EDEADLCK to drm.
> > - Based on the discussion with Ville, removed active_pipe_changes
> > check and also there seems to be no need for checking ddb_state_changes
> > as well. Instead we just iterate through crtcs in state - having
> > crtc in a state already guarantees that it is at least read-locked
> > Having additional flag to check if there actually were some plane
> > wm/ddb changes would be probably added later as an optimization.
> > - We can't get parent atomic state from crtc_state at commit stage
> > (nice drm feature), also propagating state through function call
> > chain seems to be overkill and not possible(cursor legacy updates)
> > Querying for bw_state object from global state is not possible as
> > it might get swapped with other global state.
> > So... just sticked can_sagv boolean into wm crtc state.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> > drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > 5 files changed, 318 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index b5f61463922f..4083adf4b432 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -18,6 +18,24 @@ struct intel_crtc_state;
> > struct intel_bw_state {
> > struct intel_global_state base;
> >
> > + /*
> > + * Contains a bit mask, used to determine, whether correspondent
> > + * pipe allows SAGV or not.
> > + */
> > + u8 pipe_sagv_reject;
> > +
> > + /*
> > + * Used to determine if we already had calculated
> > + * SAGV mask for this state once.
> > + */
> > + bool sagv_calculated;
>
> Why would we even attempt to calculate it many times?
>
> > +
> > + /*
> > + * Contains final SAGV decision based on current mask,
> > + * to prevent doing the same job over and over again.
> > + */
> > + bool can_sagv;
>
> This is redundant since it's just sagv_reject==0.
>
> > +
> > unsigned int data_rate[I915_MAX_PIPES];
> > u8 num_active_planes[I915_MAX_PIPES];
> > };
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8f23c4d51c33..9e0058a78ea6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > - &sw_plane_wm->wm[level]))
> > + &sw_plane_wm->wm[level]) ||
> > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > + &sw_plane_wm->sagv_wm0) &&
> > + (level == 0)))
>
> Pointless parens. Also we should do the check as
> 'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
> level != 0.
>
> I guess we can't read out sagv state due to the silly pcode interface?
>
> > continue;
> >
> > drm_err(&dev_priv->drm,
> > @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > - &sw_plane_wm->wm[level]))
> > + &sw_plane_wm->wm[level]) ||
> > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > + &sw_plane_wm->sagv_wm0) &&
> > + (level == 0)))
> > continue;
> >
> > drm_err(&dev_priv->drm,
> > @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > * SKL workaround: bspec recommends we disable the SAGV when we
> > * have more then one pipe enabled
> > */
> > - if (!intel_can_enable_sagv(state))
> > - intel_disable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + if (!intel_can_enable_sagv(state))
> > + intel_disable_sagv(dev_priv);
> > + }
> >
> > intel_modeset_verify_disabled(dev_priv, state);
> > }
> > @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (state->modeset)
> > intel_verify_planes(state);
> >
> > - if (state->modeset && intel_can_enable_sagv(state))
> > - intel_enable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + if (state->modeset && intel_can_enable_sagv(state))
> > + intel_enable_sagv(dev_priv);
> > + }
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> >
> > @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> >
> > if (state->global_state_changed) {
> > assert_global_state_locked(dev_priv);
> > -
> > dev_priv->active_pipes = state->active_pipes;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5e00e611f077..da0308b87dad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -669,11 +669,14 @@ struct skl_plane_wm {
> > struct skl_wm_level wm[8];
> > struct skl_wm_level uv_wm[8];
> > struct skl_wm_level trans_wm;
> > + struct skl_wm_level sagv_wm0;
> > + struct skl_wm_level uv_sagv_wm0;
> > bool is_planar;
> > };
> >
> > struct skl_pipe_wm {
> > struct skl_plane_wm planes[I915_MAX_PLANES];
> > + bool can_sagv;
> > };
> >
> > enum vlv_wm_level {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c72fa59a8302..f598b55f4abc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -43,6 +43,7 @@
> > #include "i915_fixed.h"
> > #include "i915_irq.h"
> > #include "i915_trace.h"
> > +#include "display/intel_bw.h"
> > #include "intel_pm.h"
> > #include "intel_sideband.h"
> > #include "../../../platform/x86/intel_ips.h"
> > @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > }
> >
> > -static bool
> > +bool
> > intel_has_sagv(struct drm_i915_private *dev_priv)
> > {
> > /* HACK! */
> > @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > return 0;
> > }
> >
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
>
> This extraction looks to be trivially done as a separate patch.
>
> > {
> > - struct drm_device *dev = state->base.dev;
> > + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > struct intel_crtc *crtc;
> > struct intel_plane *plane;
> > - struct intel_crtc_state *crtc_state;
> > - enum pipe pipe;
> > int level, latency;
> >
> > - if (!intel_has_sagv(dev_priv))
> > - return false;
> > -
> > - /*
> > - * If there are no active CRTCs, no additional checks need be performed
> > - */
> > - if (hweight8(state->active_pipes) == 0)
> > - return true;
> > + crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >
> > - /*
> > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > - * more then one pipe enabled
> > - */
> > - if (hweight8(state->active_pipes) > 1)
> > + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> > return false;
> >
> > - /* Since we're now guaranteed to only have one active CRTC... */
> > - pipe = ffs(state->active_pipes) - 1;
> > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > -
> > - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> > + pipe_name(crtc->pipe));
> > return false;
> > + }
> >
> > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > struct skl_plane_wm *wm =
> > @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > * incur memory latencies higher than sagv_block_time_us we
> > * can't enable SAGV.
> > */
> > - if (latency < dev_priv->sagv_block_time_us)
> > + if (latency < dev_priv->sagv_block_time_us) {
> > + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> > + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> > return false;
> > + }
> > }
> >
> > return true;
> > }
> >
> > +static bool
> > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> > +
> > +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> > +{
> > + return bw_state->pipe_sagv_reject == 0;
> > +}
> > +
> > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + int ret;
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + struct intel_bw_state *old_bw_state = NULL;
> > + int i;
> > +
> > + /*
> > + * If SAGV is not supported we just can't do anything
> > + * not even set or reject SAGV points - just bail out.
> > + * Thus avoid needless calculations.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return 0;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + bool pipe_sagv_enable;
> > +
> > + new_bw_state = intel_bw_get_state(state);
> > + old_bw_state = intel_bw_get_old_state(state);
> > +
> > + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> > + WARN(1, "Could not get bw_state\n");
> > + return -EINVAL;
>
> What is this?
>
> > + }
> > +
> > + new_bw_state->sagv_calculated = false;
> > +
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> > + else
> > + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> > +
> > + if (pipe_sagv_enable)
> > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > + else
> > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > + }
> > +
> > + if (!new_bw_state || !old_bw_state)
> > + return 0;
> > +
> > + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> > + new_bw_state->sagv_calculated = true;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > +
> > + /*
> > + * Due to drm limitation at commit state, when
> > + * changes are written the whole atomic state is
> > + * zeroed away => which prevents from using it,
> > + * so just sticking it into pipe wm state for
> > + * keeping it simple - anyway this is related to wm.
> > + * Proper way in ideal universe would be of course not
> > + * to lose parent atomic state object from child crtc_state,
> > + * and stick to OOP programming principles, which had been
> > + * scientifically proven to work.
> > + */
> > + pipe_wm->can_sagv = new_bw_state->can_sagv;
>
> I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
> what it does.
>
> > + }
> > +
> > + /*
> > + * For SAGV we need to account all the pipes,
> > + * not only the ones which are in state currently.
> > + * Grab all locks if we detect that we are actually
> > + * going to do something.
> > + */
> > + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> > + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> > + state,
> > + old_bw_state->pipe_sagv_reject,
> > + new_bw_state->pipe_sagv_reject);
> > +
> > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > + if (ret) {
> > + DRM_DEBUG_KMS("Could not serialize global state\n");
> > + return ret;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * This function to be used before swap state
> > + */
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_bw_state *bw_state;
> > +
> > + if (!intel_has_sagv(dev_priv)) {
> > + DRM_DEBUG_KMS("No SAGV support detected\n");
> > + return false;
> > + }
> > +
> > + bw_state = intel_bw_get_state(state);
> > +
> > + if (IS_ERR_OR_NULL(bw_state)) {
>
> It can't be NULL. And if you get an error you must propagate it upwards.
Can you please elaborate what I should do here?
Just want to save some time without wasting time guessing.
The options are:
1) If I propagate an error upwards, I obviously need to change a signature
to int intel_can_enable_sagv, also if I do that usage at legacy callsites
for this function will change, i.e you won't be able to call it like
if (intel_can_enable_sagv()) anymore. Is it that what you want?
Should note also that most of the legacy call sites are from commit_tail
which wouldn't even propagate it further, because as you know it is already
point of no return.
So if I do this without asking, I might get comments that intel_can_enable_sagv
is now unneccessarily complicated to use and you can't use it to have a trivial
check.
2) I can stop using bw_state completely in this function, but add some
flag to intel_atomic_state or somewhere else or even use this hacky
pipe_wm which now contains sagv flag, i.e then there would be no
need to propagate any error.
However you then might say that adding
or using some additional flag is ugly,wrong and we should stick to
bw_state :)
3) I can continue to return boolean however print the error code here,
if we could not get bw_state.
IMO I would use that one - it is the easiest and propagating it higher
from that helper function doesn't make any sense.
However, again it can be then argued that we need to propagate an error
upwards and not swallow it returning false.
Stan
>
> > + WARN(1, "Could not get bw_state\n");
> > + return false;
> > + }
> > +
> > + if (bw_state->sagv_calculated)
> > + goto out;
> > +
> > + bw_state->can_sagv = intel_calculate_sagv_result(bw_state);
> > + bw_state->sagv_calculated = true;
> > +
> > +out:
> > + return bw_state->can_sagv;
> > +}
> > +
> > /*
> > * Calculate initial DBuf slice offset, based on slice size
> > * and mask(i.e if slice size is 1024 and second slice is enabled
> > @@ -4042,6 +4161,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> > u32 latency = dev_priv->wm.skl_latency[level];
> >
> > skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> > +
>
> Spurious whitespace.
>
> > if (wm.min_ddb_alloc == U16_MAX)
> > break;
> >
> > @@ -4556,9 +4676,83 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > const struct skl_plane_wm *wm =
> > &crtc_state->wm.skl.optimal.planes[plane_id];
> >
> > + if (!level) {
> > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
>
> Why is this here when &crtc_state->wm.skl.optimal is already being used
> higher up?
>
> > +
> > + if (pipe_wm->can_sagv)
> > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > + }
> > +
> > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > }
> >
> > +static bool
> > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_crtc *crtc = crtc_state->uapi.crtc;
>
> Pls don't use the annoying drm_ types.
>
> > + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > + u16 alloc_size;
> > + u64 total_data_rate;
> > + enum plane_id plane_id;
> > + int num_active;
> > + u64 plane_data_rate[I915_MAX_PLANES] = {};
> > + u32 blocks;
> > +
> > + /*
> > + * If pipe is not active it can't affect SAGV rejection
> > + * Checking it here is needed to leave only cases when
> > + * alloc_size is 0 for any other reasons, except inactive
> > + * pipe. As inactive pipe is fine, however having no ddb
> > + * space available is already problematic - so need to
> > + * to separate those.
> > + */
>
> Can't figure out what this comment is trying to say or why it's here.
>
> > + if (!crtc_state->hw.active)
> > + return true;
> > +
> > + /*
> > + * No need to check gen here, we call this only for gen12
> > + */
> > + total_data_rate =
> > + icl_get_total_relative_data_rate(crtc_state,
> > + plane_data_rate);
> > +
> > + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > + total_data_rate,
> > + alloc, &num_active);
> > + alloc_size = skl_ddb_entry_size(alloc);
>
> Don't we already have this in the crtc state?
>
> > + if (alloc_size == 0)
> > + return false;
>
> I don't think that can happen.
>
> > +
> > + /*
> > + * Do check if we can fit L0 + sagv_block_time and
> > + * disable SAGV if we can't.
> > + */
> > + blocks = 0;
> > + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + /*
> > + * The only place, where we can't use skl_plane_wm_level
> > + * accessor, because if actually calls intel_can_enable_sagv
> > + * which depends on that function.
> > + */
> > + const struct skl_plane_wm *wm =
> > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > + blocks += wm->sagv_wm0.min_ddb_alloc;
> > + blocks += wm->uv_sagv_wm0.min_ddb_alloc;
> > +
> > + if (blocks > alloc_size) {
> > + DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
> > + alloc_size, blocks, pipe_name(intel_crtc->pipe));
> > + return false;
> > + }
> > + }
> > + DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
> > + blocks, alloc_size);
> > + return true;
> > +}
> > +
> > static int
> > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > {
> > @@ -5140,11 +5334,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > static void
> > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > const struct skl_wm_params *wm_params,
> > - struct skl_wm_level *levels)
> > + struct skl_plane_wm *plane_wm,
> > + bool yuv)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > int level, max_level = ilk_wm_max_level(dev_priv);
> > + /*
> > + * Check which kind of plane is it and based on that calculate
> > + * correspondent WM levels.
> > + */
> > + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
> > struct skl_wm_level *result_prev = &levels[0];
> > + struct skl_wm_level *sagv_wm = yuv ?
> > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> >
> > for (level = 0; level <= max_level; level++) {
> > struct skl_wm_level *result = &levels[level];
> > @@ -5155,6 +5357,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> >
> > result_prev = result;
> > }
> > + /*
> > + * For Gen12 if it is an L0 we need to also
> > + * consider sagv_block_time when calculating
> > + * L0 watermark - we will need that when making
> > + * a decision whether enable SAGV or not.
> > + * For older gens we agreed to copy L0 value for
> > + * compatibility.
> > + */
> > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > + u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > + latency += dev_priv->sagv_block_time_us;
> > + skl_compute_plane_wm(crtc_state, 0, latency,
> > + wm_params, &levels[0],
> > + sagv_wm);
> > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > + } else {
> > + /* Since all members are POD */
> > + *sagv_wm = levels[0];
> > + }
>
> I was thinking more along the lines of
>
> skl_compute_wm_levels();
> skl_compute_transition_wm();
> + skl_compute_sagv_wm();
>
>
> > }
> >
> > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > @@ -5237,7 +5460,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >
> > return 0;
> > @@ -5259,7 +5482,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
> >
> > return 0;
> > }
> > @@ -5598,9 +5821,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> > enum plane_id plane_id = plane->id;
> > const struct skl_plane_wm *old_wm, *new_wm;
> > + const struct skl_wm_level *old_wm_level, *new_wm_level;
> > + u16 old_plane_res_l, new_plane_res_l;
> > + u8 old_plane_res_b, new_plane_res_b;
> > + u16 old_min_ddb_alloc, new_min_ddb_alloc;
> > + int color_plane = 0;
> >
> > old_wm = &old_pipe_wm->planes[plane_id];
> > new_wm = &new_pipe_wm->planes[plane_id];
> > + old_wm_level = skl_plane_wm_level(old_crtc_state, plane_id, 0, color_plane);
> > + new_wm_level = skl_plane_wm_level(new_crtc_state, plane_id, 0, color_plane);
> > +
> > + old_plane_res_l = old_wm_level->plane_res_l;
> > + old_plane_res_b = old_wm_level->plane_res_b;
> > +
> > + new_plane_res_l = new_wm_level->plane_res_l;
> > + new_plane_res_b = new_wm_level->plane_res_b;
> > +
> > + old_min_ddb_alloc = old_wm_level->min_ddb_alloc;
> > + new_min_ddb_alloc = new_wm_level->min_ddb_alloc;
> >
> > if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
> > continue;
> > @@ -5624,7 +5863,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
> > " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
> > plane->base.base.id, plane->base.name,
> > - enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
> > + enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
> > enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
> > enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
> > enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
> > @@ -5634,7 +5873,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
> > enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
> >
> > - enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
> > + enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
> > enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
> > enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
> > enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
> > @@ -5648,12 +5887,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > plane->base.base.id, plane->base.name,
> > - old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
> > + old_plane_res_b, old_wm->wm[1].plane_res_b,
> > old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
> > old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
> > old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
> > old_wm->trans_wm.plane_res_b,
> > - new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
> > + new_plane_res_b, new_wm->wm[1].plane_res_b,
> > new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
> > new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
> > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > @@ -5663,12 +5902,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > plane->base.base.id, plane->base.name,
> > - old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
> > + old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
> > old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
> > old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
> > old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
> > old_wm->trans_wm.min_ddb_alloc,
> > - new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
> > + new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
> > new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
> > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
>
> Here too I think the sagv wm should be treated more or less like the
> transition wm (ie. just printed as an extra).
>
> > @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
> > return ret;
> > }
> >
> > + ret = intel_compute_sagv_mask(state);
> > + if (ret)
> > + return ret;
>
> This seems too early. We haven't even computed the ddb yet.
>
> > +
> > ret = skl_compute_ddb(state);
> > if (ret)
> > return ret;
> > @@ -5960,6 +6203,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > val = I915_READ(CUR_WM(pipe, level));
> >
> > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > + if (level == 0)
> > + memcpy(&wm->sagv_wm0, &wm->wm[level],
> > + sizeof(struct skl_wm_level));
> > }
> >
> > if (plane_id != PLANE_CURSOR)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > index d60a85421c5a..65743a4cbcf6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -42,6 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-20 12:51 ` Lisovskiy, Stanislav
@ 2020-03-23 14:18 ` Ville Syrjälä
2020-03-23 14:36 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-23 14:18 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Fri, Mar 20, 2020 at 02:51:41PM +0200, Lisovskiy, Stanislav wrote:
> On Wed, Mar 11, 2020 at 06:31:30PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> > > Currently intel_can_enable_sagv function contains
> > > a mix of workarounds for different platforms
> > > some of them are not valid for gens >= 11 already,
> > > so lets split it into separate functions.
> > >
> > > v2:
> > > - Rework watermark calculation algorithm to
> > > attempt to calculate Level 0 watermark
> > > with added sagv block time latency and
> > > check if it fits in DBuf in order to
> > > determine if SAGV can be enabled already
> > > at this stage, just as BSpec 49325 states.
> > > if that fails rollback to usual Level 0
> > > latency and disable SAGV.
> > > - Remove unneeded tabs(James Ausmus)
> > >
> > > v3: Rebased the patch
> > >
> > > v4: - Added back interlaced check for Gen12 and
> > > added separate function for TGL SAGV check
> > > (thanks to James Ausmus for spotting)
> > > - Removed unneeded gen check
> > > - Extracted Gen12 SAGV decision making code
> > > to a separate function from skl_compute_wm
> > >
> > > v5: - Added SAGV global state to dev_priv, because
> > > we need to track all pipes, not only those
> > > in atomic state. Each pipe has now correspondent
> > > bit mask reflecting, whether it can tolerate
> > > SAGV or not(thanks to Ville Syrjala for suggestions).
> > > - Now using active flag instead of enable in crc
> > > usage check.
> > >
> > > v6: - Fixed rebase conflicts
> > >
> > > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> > > calls when copying level 0 water marks for enabled SAGV, to
> > > fix this now simply using that field right away, without copying,
> > > for that introduced a new wm_level accessor which decides which
> > > wm_level to return based on SAGV state.
> > >
> > > v8: - Protect crtc_sagv_mask same way as we do for other global state
> > > changes: i.e check if changes are needed, then grab all crtc locks
> > > to serialize the changes(Ville Syrjälä)
> > > - Add crtc_sagv_mask caching in order to avoid needless recalculations
> > > (Matthew Roper)
> > > - Put back Gen12 SAGV switch in order to get it enabled in separate
> > > patch(Matthew Roper)
> > > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> > > - Check if there are no active pipes in intel_can_enable_sagv
> > > instead of platform specific functions(Matthew Roper), same
> > > for intel_has_sagv check.
> > >
> > > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> > > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> > > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> > > - Extracted skl_plane_wm_level function and passing latency to
> > > separate patches(Ville Syrjälä)
> > > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> > > (Ville Syrjälä)
> > > - Now using simple assignment for sagv_wm0 as it contains only
> > > pod types and no pointers(Ville Syrjälä)
> > > - Fixed intel_can_enable_sagv not to do double duty, now it only
> > > check SAGV bits by ANDing those between local and global state.
> > > The SAGV masks are now computed after watermarks are available,
> > > in order to be able to figure out if ddb ranges are fitting nicely.
> > > (Ville Syrjälä)
> > > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> > > when using skl_plane_wm_level accessor, as we had previously for
> > > Gen11+ color plane and regular wm levels, so probably both
> > > has to be recalculated with additional SAGV block time for Level 0.
> > >
> > > v10: - Starting to use new global state for storing pipe_sagv_mask
> > >
> > > v11: - Fixed rebase conflict with recent drm-tip
> > > - Check if we really need to recalculate SAGV mask, otherwise
> > > bail out without making any changes.
> > > - Use cached SAGV result, instead of recalculating it everytime,
> > > if bw_state hasn't changed.
> > >
> > > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> > > if we don't recalculated watermarks, bw_state is not recalculated,
> > > thus leading to SAGV state not recalculated by the commit state,
> > > which is still calling intel_can_enable_sagv function. Fix that
> > > by just analyzing the current global bw_state object - because
> > > we simply have no other objects related to that.
> > >
> > > v13: - Rebased, fixed warnings regarding long lines
> > > - Changed function call sites from intel_atomic_bw* to
> > > intel_wb_* as was suggested.(Jani Nikula)
> > > - Taken ddb_state_changed and bw_state_changed into use.
> > >
> > > v14: - total_affected_planes is no longer needed to check for ddb changes,
> > > just as active_pipe_changes.
> > >
> > > v15: - Fixed stupid mistake with uninitialized crtc in
> > > skl_compute_sagv_mask.
> > >
> > > v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> > > flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> > > - Added return value to intel_compute_sagv_mask which call
> > > intel_atomic_serialize_global_state in order to properly
> > > propagate EDEADLCK to drm.
> > > - Based on the discussion with Ville, removed active_pipe_changes
> > > check and also there seems to be no need for checking ddb_state_changes
> > > as well. Instead we just iterate through crtcs in state - having
> > > crtc in a state already guarantees that it is at least read-locked
> > > Having additional flag to check if there actually were some plane
> > > wm/ddb changes would be probably added later as an optimization.
> > > - We can't get parent atomic state from crtc_state at commit stage
> > > (nice drm feature), also propagating state through function call
> > > chain seems to be overkill and not possible(cursor legacy updates)
> > > Querying for bw_state object from global state is not possible as
> > > it might get swapped with other global state.
> > > So... just sticked can_sagv boolean into wm crtc state.
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> > > drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> > > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > > 5 files changed, 318 insertions(+), 41 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index b5f61463922f..4083adf4b432 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -18,6 +18,24 @@ struct intel_crtc_state;
> > > struct intel_bw_state {
> > > struct intel_global_state base;
> > >
> > > + /*
> > > + * Contains a bit mask, used to determine, whether correspondent
> > > + * pipe allows SAGV or not.
> > > + */
> > > + u8 pipe_sagv_reject;
> > > +
> > > + /*
> > > + * Used to determine if we already had calculated
> > > + * SAGV mask for this state once.
> > > + */
> > > + bool sagv_calculated;
> >
> > Why would we even attempt to calculate it many times?
> >
> > > +
> > > + /*
> > > + * Contains final SAGV decision based on current mask,
> > > + * to prevent doing the same job over and over again.
> > > + */
> > > + bool can_sagv;
> >
> > This is redundant since it's just sagv_reject==0.
> >
> > > +
> > > unsigned int data_rate[I915_MAX_PIPES];
> > > u8 num_active_planes[I915_MAX_PIPES];
> > > };
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 8f23c4d51c33..9e0058a78ea6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > - &sw_plane_wm->wm[level]))
> > > + &sw_plane_wm->wm[level]) ||
> > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > + &sw_plane_wm->sagv_wm0) &&
> > > + (level == 0)))
> >
> > Pointless parens. Also we should do the check as
> > 'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
> > level != 0.
> >
> > I guess we can't read out sagv state due to the silly pcode interface?
> >
> > > continue;
> > >
> > > drm_err(&dev_priv->drm,
> > > @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > - &sw_plane_wm->wm[level]))
> > > + &sw_plane_wm->wm[level]) ||
> > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > + &sw_plane_wm->sagv_wm0) &&
> > > + (level == 0)))
> > > continue;
> > >
> > > drm_err(&dev_priv->drm,
> > > @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > * SKL workaround: bspec recommends we disable the SAGV when we
> > > * have more then one pipe enabled
> > > */
> > > - if (!intel_can_enable_sagv(state))
> > > - intel_disable_sagv(dev_priv);
> > > + if (INTEL_GEN(dev_priv) < 11) {
> > > + if (!intel_can_enable_sagv(state))
> > > + intel_disable_sagv(dev_priv);
> > > + }
> > >
> > > intel_modeset_verify_disabled(dev_priv, state);
> > > }
> > > @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > if (state->modeset)
> > > intel_verify_planes(state);
> > >
> > > - if (state->modeset && intel_can_enable_sagv(state))
> > > - intel_enable_sagv(dev_priv);
> > > + if (INTEL_GEN(dev_priv) < 11) {
> > > + if (state->modeset && intel_can_enable_sagv(state))
> > > + intel_enable_sagv(dev_priv);
> > > + }
> > >
> > > drm_atomic_helper_commit_hw_done(&state->base);
> > >
> > > @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > >
> > > if (state->global_state_changed) {
> > > assert_global_state_locked(dev_priv);
> > > -
> > > dev_priv->active_pipes = state->active_pipes;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5e00e611f077..da0308b87dad 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -669,11 +669,14 @@ struct skl_plane_wm {
> > > struct skl_wm_level wm[8];
> > > struct skl_wm_level uv_wm[8];
> > > struct skl_wm_level trans_wm;
> > > + struct skl_wm_level sagv_wm0;
> > > + struct skl_wm_level uv_sagv_wm0;
> > > bool is_planar;
> > > };
> > >
> > > struct skl_pipe_wm {
> > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > + bool can_sagv;
> > > };
> > >
> > > enum vlv_wm_level {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index c72fa59a8302..f598b55f4abc 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -43,6 +43,7 @@
> > > #include "i915_fixed.h"
> > > #include "i915_irq.h"
> > > #include "i915_trace.h"
> > > +#include "display/intel_bw.h"
> > > #include "intel_pm.h"
> > > #include "intel_sideband.h"
> > > #include "../../../platform/x86/intel_ips.h"
> > > @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > > }
> > >
> > > -static bool
> > > +bool
> > > intel_has_sagv(struct drm_i915_private *dev_priv)
> > > {
> > > /* HACK! */
> > > @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > return 0;
> > > }
> > >
> > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> >
> > This extraction looks to be trivially done as a separate patch.
> >
> > > {
> > > - struct drm_device *dev = state->base.dev;
> > > + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > struct intel_crtc *crtc;
> > > struct intel_plane *plane;
> > > - struct intel_crtc_state *crtc_state;
> > > - enum pipe pipe;
> > > int level, latency;
> > >
> > > - if (!intel_has_sagv(dev_priv))
> > > - return false;
> > > -
> > > - /*
> > > - * If there are no active CRTCs, no additional checks need be performed
> > > - */
> > > - if (hweight8(state->active_pipes) == 0)
> > > - return true;
> > > + crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >
> > > - /*
> > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > - * more then one pipe enabled
> > > - */
> > > - if (hweight8(state->active_pipes) > 1)
> > > + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> > > return false;
> > >
> > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > - pipe = ffs(state->active_pipes) - 1;
> > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > -
> > > - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> > > + pipe_name(crtc->pipe));
> > > return false;
> > > + }
> > >
> > > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > struct skl_plane_wm *wm =
> > > @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > * incur memory latencies higher than sagv_block_time_us we
> > > * can't enable SAGV.
> > > */
> > > - if (latency < dev_priv->sagv_block_time_us)
> > > + if (latency < dev_priv->sagv_block_time_us) {
> > > + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> > > + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> > > return false;
> > > + }
> > > }
> > >
> > > return true;
> > > }
> > >
> > > +static bool
> > > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> > > +
> > > +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> > > +{
> > > + return bw_state->pipe_sagv_reject == 0;
> > > +}
> > > +
> > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > +{
> > > + int ret;
> > > + struct drm_device *dev = state->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_crtc *crtc;
> > > + struct intel_crtc_state *new_crtc_state;
> > > + struct intel_bw_state *new_bw_state = NULL;
> > > + struct intel_bw_state *old_bw_state = NULL;
> > > + int i;
> > > +
> > > + /*
> > > + * If SAGV is not supported we just can't do anything
> > > + * not even set or reject SAGV points - just bail out.
> > > + * Thus avoid needless calculations.
> > > + */
> > > + if (!intel_has_sagv(dev_priv))
> > > + return 0;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > + new_crtc_state, i) {
> > > + bool pipe_sagv_enable;
> > > +
> > > + new_bw_state = intel_bw_get_state(state);
> > > + old_bw_state = intel_bw_get_old_state(state);
> > > +
> > > + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> > > + WARN(1, "Could not get bw_state\n");
> > > + return -EINVAL;
> >
> > What is this?
> >
> > > + }
> > > +
> > > + new_bw_state->sagv_calculated = false;
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 12)
> > > + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> > > + else
> > > + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> > > +
> > > + if (pipe_sagv_enable)
> > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > + else
> > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > + }
> > > +
> > > + if (!new_bw_state || !old_bw_state)
> > > + return 0;
> > > +
> > > + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> > > + new_bw_state->sagv_calculated = true;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > + new_crtc_state, i) {
> > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > +
> > > + /*
> > > + * Due to drm limitation at commit state, when
> > > + * changes are written the whole atomic state is
> > > + * zeroed away => which prevents from using it,
> > > + * so just sticking it into pipe wm state for
> > > + * keeping it simple - anyway this is related to wm.
> > > + * Proper way in ideal universe would be of course not
> > > + * to lose parent atomic state object from child crtc_state,
> > > + * and stick to OOP programming principles, which had been
> > > + * scientifically proven to work.
> > > + */
> > > + pipe_wm->can_sagv = new_bw_state->can_sagv;
> >
> > I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
> > what it does.
> >
> > > + }
> > > +
> > > + /*
> > > + * For SAGV we need to account all the pipes,
> > > + * not only the ones which are in state currently.
> > > + * Grab all locks if we detect that we are actually
> > > + * going to do something.
> > > + */
> > > + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> > > + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> > > + state,
> > > + old_bw_state->pipe_sagv_reject,
> > > + new_bw_state->pipe_sagv_reject);
> > > +
> > > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > + if (ret) {
> > > + DRM_DEBUG_KMS("Could not serialize global state\n");
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/*
> > > + * This function to be used before swap state
> > > + */
> > > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > +{
> > > + struct drm_device *dev = state->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_bw_state *bw_state;
> > > +
> > > + if (!intel_has_sagv(dev_priv)) {
> > > + DRM_DEBUG_KMS("No SAGV support detected\n");
> > > + return false;
> > > + }
> > > +
> > > + bw_state = intel_bw_get_state(state);
> > > +
> > > + if (IS_ERR_OR_NULL(bw_state)) {
> >
> > It can't be NULL. And if you get an error you must propagate it upwards.
>
> Can you please elaborate what I should do here?
> Just want to save some time without wasting time guessing.
> The options are:
>
> 1) If I propagate an error upwards, I obviously need to change a signature
> to int intel_can_enable_sagv, also if I do that usage at legacy callsites
> for this function will change, i.e you won't be able to call it like
> if (intel_can_enable_sagv()) anymore. Is it that what you want?
> Should note also that most of the legacy call sites are from commit_tail
> which wouldn't even propagate it further, because as you know it is already
> point of no return.
Looks like intel_can_enable_sagv() should not exist anymore. We should
just precompute the sagv mask in the bw atomic check, and then the commit
time checks will simply become checks of the sagv mask.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-23 14:18 ` Ville Syrjälä
@ 2020-03-23 14:36 ` Lisovskiy, Stanislav
2020-03-23 14:50 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-23 14:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Mar 23, 2020 at 04:18:36PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 20, 2020 at 02:51:41PM +0200, Lisovskiy, Stanislav wrote:
> > On Wed, Mar 11, 2020 at 06:31:30PM +0200, Ville Syrjälä wrote:
> > > On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> > > > Currently intel_can_enable_sagv function contains
> > > > a mix of workarounds for different platforms
> > > > some of them are not valid for gens >= 11 already,
> > > > so lets split it into separate functions.
> > > >
> > > > v2:
> > > > - Rework watermark calculation algorithm to
> > > > attempt to calculate Level 0 watermark
> > > > with added sagv block time latency and
> > > > check if it fits in DBuf in order to
> > > > determine if SAGV can be enabled already
> > > > at this stage, just as BSpec 49325 states.
> > > > if that fails rollback to usual Level 0
> > > > latency and disable SAGV.
> > > > - Remove unneeded tabs(James Ausmus)
> > > >
> > > > v3: Rebased the patch
> > > >
> > > > v4: - Added back interlaced check for Gen12 and
> > > > added separate function for TGL SAGV check
> > > > (thanks to James Ausmus for spotting)
> > > > - Removed unneeded gen check
> > > > - Extracted Gen12 SAGV decision making code
> > > > to a separate function from skl_compute_wm
> > > >
> > > > v5: - Added SAGV global state to dev_priv, because
> > > > we need to track all pipes, not only those
> > > > in atomic state. Each pipe has now correspondent
> > > > bit mask reflecting, whether it can tolerate
> > > > SAGV or not(thanks to Ville Syrjala for suggestions).
> > > > - Now using active flag instead of enable in crc
> > > > usage check.
> > > >
> > > > v6: - Fixed rebase conflicts
> > > >
> > > > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> > > > calls when copying level 0 water marks for enabled SAGV, to
> > > > fix this now simply using that field right away, without copying,
> > > > for that introduced a new wm_level accessor which decides which
> > > > wm_level to return based on SAGV state.
> > > >
> > > > v8: - Protect crtc_sagv_mask same way as we do for other global state
> > > > changes: i.e check if changes are needed, then grab all crtc locks
> > > > to serialize the changes(Ville Syrjälä)
> > > > - Add crtc_sagv_mask caching in order to avoid needless recalculations
> > > > (Matthew Roper)
> > > > - Put back Gen12 SAGV switch in order to get it enabled in separate
> > > > patch(Matthew Roper)
> > > > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> > > > - Check if there are no active pipes in intel_can_enable_sagv
> > > > instead of platform specific functions(Matthew Roper), same
> > > > for intel_has_sagv check.
> > > >
> > > > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> > > > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> > > > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> > > > - Extracted skl_plane_wm_level function and passing latency to
> > > > separate patches(Ville Syrjälä)
> > > > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> > > > (Ville Syrjälä)
> > > > - Now using simple assignment for sagv_wm0 as it contains only
> > > > pod types and no pointers(Ville Syrjälä)
> > > > - Fixed intel_can_enable_sagv not to do double duty, now it only
> > > > check SAGV bits by ANDing those between local and global state.
> > > > The SAGV masks are now computed after watermarks are available,
> > > > in order to be able to figure out if ddb ranges are fitting nicely.
> > > > (Ville Syrjälä)
> > > > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> > > > when using skl_plane_wm_level accessor, as we had previously for
> > > > Gen11+ color plane and regular wm levels, so probably both
> > > > has to be recalculated with additional SAGV block time for Level 0.
> > > >
> > > > v10: - Starting to use new global state for storing pipe_sagv_mask
> > > >
> > > > v11: - Fixed rebase conflict with recent drm-tip
> > > > - Check if we really need to recalculate SAGV mask, otherwise
> > > > bail out without making any changes.
> > > > - Use cached SAGV result, instead of recalculating it everytime,
> > > > if bw_state hasn't changed.
> > > >
> > > > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> > > > if we don't recalculated watermarks, bw_state is not recalculated,
> > > > thus leading to SAGV state not recalculated by the commit state,
> > > > which is still calling intel_can_enable_sagv function. Fix that
> > > > by just analyzing the current global bw_state object - because
> > > > we simply have no other objects related to that.
> > > >
> > > > v13: - Rebased, fixed warnings regarding long lines
> > > > - Changed function call sites from intel_atomic_bw* to
> > > > intel_wb_* as was suggested.(Jani Nikula)
> > > > - Taken ddb_state_changed and bw_state_changed into use.
> > > >
> > > > v14: - total_affected_planes is no longer needed to check for ddb changes,
> > > > just as active_pipe_changes.
> > > >
> > > > v15: - Fixed stupid mistake with uninitialized crtc in
> > > > skl_compute_sagv_mask.
> > > >
> > > > v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> > > > flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> > > > - Added return value to intel_compute_sagv_mask which call
> > > > intel_atomic_serialize_global_state in order to properly
> > > > propagate EDEADLCK to drm.
> > > > - Based on the discussion with Ville, removed active_pipe_changes
> > > > check and also there seems to be no need for checking ddb_state_changes
> > > > as well. Instead we just iterate through crtcs in state - having
> > > > crtc in a state already guarantees that it is at least read-locked
> > > > Having additional flag to check if there actually were some plane
> > > > wm/ddb changes would be probably added later as an optimization.
> > > > - We can't get parent atomic state from crtc_state at commit stage
> > > > (nice drm feature), also propagating state through function call
> > > > chain seems to be overkill and not possible(cursor legacy updates)
> > > > Querying for bw_state object from global state is not possible as
> > > > it might get swapped with other global state.
> > > > So... just sticked can_sagv boolean into wm crtc state.
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> > > > drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> > > > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > > > 5 files changed, 318 insertions(+), 41 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > index b5f61463922f..4083adf4b432 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > @@ -18,6 +18,24 @@ struct intel_crtc_state;
> > > > struct intel_bw_state {
> > > > struct intel_global_state base;
> > > >
> > > > + /*
> > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > + * pipe allows SAGV or not.
> > > > + */
> > > > + u8 pipe_sagv_reject;
> > > > +
> > > > + /*
> > > > + * Used to determine if we already had calculated
> > > > + * SAGV mask for this state once.
> > > > + */
> > > > + bool sagv_calculated;
> > >
> > > Why would we even attempt to calculate it many times?
> > >
> > > > +
> > > > + /*
> > > > + * Contains final SAGV decision based on current mask,
> > > > + * to prevent doing the same job over and over again.
> > > > + */
> > > > + bool can_sagv;
> > >
> > > This is redundant since it's just sagv_reject==0.
> > >
> > > > +
> > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > };
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 8f23c4d51c33..9e0058a78ea6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > - &sw_plane_wm->wm[level]))
> > > > + &sw_plane_wm->wm[level]) ||
> > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > + &sw_plane_wm->sagv_wm0) &&
> > > > + (level == 0)))
> > >
> > > Pointless parens. Also we should do the check as
> > > 'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
> > > level != 0.
> > >
> > > I guess we can't read out sagv state due to the silly pcode interface?
> > >
> > > > continue;
> > > >
> > > > drm_err(&dev_priv->drm,
> > > > @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > - &sw_plane_wm->wm[level]))
> > > > + &sw_plane_wm->wm[level]) ||
> > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > + &sw_plane_wm->sagv_wm0) &&
> > > > + (level == 0)))
> > > > continue;
> > > >
> > > > drm_err(&dev_priv->drm,
> > > > @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > * SKL workaround: bspec recommends we disable the SAGV when we
> > > > * have more then one pipe enabled
> > > > */
> > > > - if (!intel_can_enable_sagv(state))
> > > > - intel_disable_sagv(dev_priv);
> > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > + if (!intel_can_enable_sagv(state))
> > > > + intel_disable_sagv(dev_priv);
> > > > + }
> > > >
> > > > intel_modeset_verify_disabled(dev_priv, state);
> > > > }
> > > > @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > if (state->modeset)
> > > > intel_verify_planes(state);
> > > >
> > > > - if (state->modeset && intel_can_enable_sagv(state))
> > > > - intel_enable_sagv(dev_priv);
> > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > + if (state->modeset && intel_can_enable_sagv(state))
> > > > + intel_enable_sagv(dev_priv);
> > > > + }
> > > >
> > > > drm_atomic_helper_commit_hw_done(&state->base);
> > > >
> > > > @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > > >
> > > > if (state->global_state_changed) {
> > > > assert_global_state_locked(dev_priv);
> > > > -
> > > > dev_priv->active_pipes = state->active_pipes;
> > > > }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 5e00e611f077..da0308b87dad 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -669,11 +669,14 @@ struct skl_plane_wm {
> > > > struct skl_wm_level wm[8];
> > > > struct skl_wm_level uv_wm[8];
> > > > struct skl_wm_level trans_wm;
> > > > + struct skl_wm_level sagv_wm0;
> > > > + struct skl_wm_level uv_sagv_wm0;
> > > > bool is_planar;
> > > > };
> > > >
> > > > struct skl_pipe_wm {
> > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > + bool can_sagv;
> > > > };
> > > >
> > > > enum vlv_wm_level {
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index c72fa59a8302..f598b55f4abc 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -43,6 +43,7 @@
> > > > #include "i915_fixed.h"
> > > > #include "i915_irq.h"
> > > > #include "i915_trace.h"
> > > > +#include "display/intel_bw.h"
> > > > #include "intel_pm.h"
> > > > #include "intel_sideband.h"
> > > > #include "../../../platform/x86/intel_ips.h"
> > > > @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > > > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > > > }
> > > >
> > > > -static bool
> > > > +bool
> > > > intel_has_sagv(struct drm_i915_private *dev_priv)
> > > > {
> > > > /* HACK! */
> > > > @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > return 0;
> > > > }
> > > >
> > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> > >
> > > This extraction looks to be trivially done as a separate patch.
> > >
> > > > {
> > > > - struct drm_device *dev = state->base.dev;
> > > > + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > struct intel_crtc *crtc;
> > > > struct intel_plane *plane;
> > > > - struct intel_crtc_state *crtc_state;
> > > > - enum pipe pipe;
> > > > int level, latency;
> > > >
> > > > - if (!intel_has_sagv(dev_priv))
> > > > - return false;
> > > > -
> > > > - /*
> > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > - */
> > > > - if (hweight8(state->active_pipes) == 0)
> > > > - return true;
> > > > + crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > >
> > > > - /*
> > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > - * more then one pipe enabled
> > > > - */
> > > > - if (hweight8(state->active_pipes) > 1)
> > > > + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> > > > return false;
> > > >
> > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > - pipe = ffs(state->active_pipes) - 1;
> > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > -
> > > > - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > > > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> > > > + pipe_name(crtc->pipe));
> > > > return false;
> > > > + }
> > > >
> > > > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > struct skl_plane_wm *wm =
> > > > @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > * incur memory latencies higher than sagv_block_time_us we
> > > > * can't enable SAGV.
> > > > */
> > > > - if (latency < dev_priv->sagv_block_time_us)
> > > > + if (latency < dev_priv->sagv_block_time_us) {
> > > > + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> > > > + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> > > > return false;
> > > > + }
> > > > }
> > > >
> > > > return true;
> > > > }
> > > >
> > > > +static bool
> > > > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> > > > +
> > > > +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> > > > +{
> > > > + return bw_state->pipe_sagv_reject == 0;
> > > > +}
> > > > +
> > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > +{
> > > > + int ret;
> > > > + struct drm_device *dev = state->base.dev;
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_crtc *crtc;
> > > > + struct intel_crtc_state *new_crtc_state;
> > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > + struct intel_bw_state *old_bw_state = NULL;
> > > > + int i;
> > > > +
> > > > + /*
> > > > + * If SAGV is not supported we just can't do anything
> > > > + * not even set or reject SAGV points - just bail out.
> > > > + * Thus avoid needless calculations.
> > > > + */
> > > > + if (!intel_has_sagv(dev_priv))
> > > > + return 0;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > + new_crtc_state, i) {
> > > > + bool pipe_sagv_enable;
> > > > +
> > > > + new_bw_state = intel_bw_get_state(state);
> > > > + old_bw_state = intel_bw_get_old_state(state);
> > > > +
> > > > + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> > > > + WARN(1, "Could not get bw_state\n");
> > > > + return -EINVAL;
> > >
> > > What is this?
> > >
> > > > + }
> > > > +
> > > > + new_bw_state->sagv_calculated = false;
> > > > +
> > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > + else
> > > > + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > +
> > > > + if (pipe_sagv_enable)
> > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > + else
> > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > + }
> > > > +
> > > > + if (!new_bw_state || !old_bw_state)
> > > > + return 0;
> > > > +
> > > > + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> > > > + new_bw_state->sagv_calculated = true;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > + new_crtc_state, i) {
> > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > +
> > > > + /*
> > > > + * Due to drm limitation at commit state, when
> > > > + * changes are written the whole atomic state is
> > > > + * zeroed away => which prevents from using it,
> > > > + * so just sticking it into pipe wm state for
> > > > + * keeping it simple - anyway this is related to wm.
> > > > + * Proper way in ideal universe would be of course not
> > > > + * to lose parent atomic state object from child crtc_state,
> > > > + * and stick to OOP programming principles, which had been
> > > > + * scientifically proven to work.
> > > > + */
> > > > + pipe_wm->can_sagv = new_bw_state->can_sagv;
> > >
> > > I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
> > > what it does.
> > >
> > > > + }
> > > > +
> > > > + /*
> > > > + * For SAGV we need to account all the pipes,
> > > > + * not only the ones which are in state currently.
> > > > + * Grab all locks if we detect that we are actually
> > > > + * going to do something.
> > > > + */
> > > > + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> > > > + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> > > > + state,
> > > > + old_bw_state->pipe_sagv_reject,
> > > > + new_bw_state->pipe_sagv_reject);
> > > > +
> > > > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > + if (ret) {
> > > > + DRM_DEBUG_KMS("Could not serialize global state\n");
> > > > + return ret;
> > > > + }
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/*
> > > > + * This function to be used before swap state
> > > > + */
> > > > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > +{
> > > > + struct drm_device *dev = state->base.dev;
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_bw_state *bw_state;
> > > > +
> > > > + if (!intel_has_sagv(dev_priv)) {
> > > > + DRM_DEBUG_KMS("No SAGV support detected\n");
> > > > + return false;
> > > > + }
> > > > +
> > > > + bw_state = intel_bw_get_state(state);
> > > > +
> > > > + if (IS_ERR_OR_NULL(bw_state)) {
> > >
> > > It can't be NULL. And if you get an error you must propagate it upwards.
> >
> > Can you please elaborate what I should do here?
> > Just want to save some time without wasting time guessing.
> > The options are:
> >
> > 1) If I propagate an error upwards, I obviously need to change a signature
> > to int intel_can_enable_sagv, also if I do that usage at legacy callsites
> > for this function will change, i.e you won't be able to call it like
> > if (intel_can_enable_sagv()) anymore. Is it that what you want?
> > Should note also that most of the legacy call sites are from commit_tail
> > which wouldn't even propagate it further, because as you know it is already
> > point of no return.
>
> Looks like intel_can_enable_sagv() should not exist anymore. We should
> just precompute the sagv mask in the bw atomic check, and then the commit
> time checks will simply become checks of the sagv mask.
Was thinking about that, but then the question is how to deal with legacy
stuff - for instance, skl doesn't have QGV points at all, as I understand
some platforms just have it as a switch so we'll have to have somekind
of code like this anyway, i.e just checking if we can and then switch.
Or basically we would be just inlining the intel_can_enable_sagv to
intel_atomic_commit_tail as I understand. Because yep for gen >=11
it just a matter of pre/post updating qgv points, but for skl we
still need some condition to check when we are calling intel_enable/disable sagv
Stan
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-23 14:36 ` Lisovskiy, Stanislav
@ 2020-03-23 14:50 ` Ville Syrjälä
2020-03-23 14:58 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-03-23 14:50 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Mon, Mar 23, 2020 at 04:36:16PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Mar 23, 2020 at 04:18:36PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 20, 2020 at 02:51:41PM +0200, Lisovskiy, Stanislav wrote:
> > > On Wed, Mar 11, 2020 at 06:31:30PM +0200, Ville Syrjälä wrote:
> > > > On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> > > > > Currently intel_can_enable_sagv function contains
> > > > > a mix of workarounds for different platforms
> > > > > some of them are not valid for gens >= 11 already,
> > > > > so lets split it into separate functions.
> > > > >
> > > > > v2:
> > > > > - Rework watermark calculation algorithm to
> > > > > attempt to calculate Level 0 watermark
> > > > > with added sagv block time latency and
> > > > > check if it fits in DBuf in order to
> > > > > determine if SAGV can be enabled already
> > > > > at this stage, just as BSpec 49325 states.
> > > > > if that fails rollback to usual Level 0
> > > > > latency and disable SAGV.
> > > > > - Remove unneeded tabs(James Ausmus)
> > > > >
> > > > > v3: Rebased the patch
> > > > >
> > > > > v4: - Added back interlaced check for Gen12 and
> > > > > added separate function for TGL SAGV check
> > > > > (thanks to James Ausmus for spotting)
> > > > > - Removed unneeded gen check
> > > > > - Extracted Gen12 SAGV decision making code
> > > > > to a separate function from skl_compute_wm
> > > > >
> > > > > v5: - Added SAGV global state to dev_priv, because
> > > > > we need to track all pipes, not only those
> > > > > in atomic state. Each pipe has now correspondent
> > > > > bit mask reflecting, whether it can tolerate
> > > > > SAGV or not(thanks to Ville Syrjala for suggestions).
> > > > > - Now using active flag instead of enable in crc
> > > > > usage check.
> > > > >
> > > > > v6: - Fixed rebase conflicts
> > > > >
> > > > > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> > > > > calls when copying level 0 water marks for enabled SAGV, to
> > > > > fix this now simply using that field right away, without copying,
> > > > > for that introduced a new wm_level accessor which decides which
> > > > > wm_level to return based on SAGV state.
> > > > >
> > > > > v8: - Protect crtc_sagv_mask same way as we do for other global state
> > > > > changes: i.e check if changes are needed, then grab all crtc locks
> > > > > to serialize the changes(Ville Syrjälä)
> > > > > - Add crtc_sagv_mask caching in order to avoid needless recalculations
> > > > > (Matthew Roper)
> > > > > - Put back Gen12 SAGV switch in order to get it enabled in separate
> > > > > patch(Matthew Roper)
> > > > > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> > > > > - Check if there are no active pipes in intel_can_enable_sagv
> > > > > instead of platform specific functions(Matthew Roper), same
> > > > > for intel_has_sagv check.
> > > > >
> > > > > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> > > > > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> > > > > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> > > > > - Extracted skl_plane_wm_level function and passing latency to
> > > > > separate patches(Ville Syrjälä)
> > > > > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> > > > > (Ville Syrjälä)
> > > > > - Now using simple assignment for sagv_wm0 as it contains only
> > > > > pod types and no pointers(Ville Syrjälä)
> > > > > - Fixed intel_can_enable_sagv not to do double duty, now it only
> > > > > check SAGV bits by ANDing those between local and global state.
> > > > > The SAGV masks are now computed after watermarks are available,
> > > > > in order to be able to figure out if ddb ranges are fitting nicely.
> > > > > (Ville Syrjälä)
> > > > > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> > > > > when using skl_plane_wm_level accessor, as we had previously for
> > > > > Gen11+ color plane and regular wm levels, so probably both
> > > > > has to be recalculated with additional SAGV block time for Level 0.
> > > > >
> > > > > v10: - Starting to use new global state for storing pipe_sagv_mask
> > > > >
> > > > > v11: - Fixed rebase conflict with recent drm-tip
> > > > > - Check if we really need to recalculate SAGV mask, otherwise
> > > > > bail out without making any changes.
> > > > > - Use cached SAGV result, instead of recalculating it everytime,
> > > > > if bw_state hasn't changed.
> > > > >
> > > > > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> > > > > if we don't recalculated watermarks, bw_state is not recalculated,
> > > > > thus leading to SAGV state not recalculated by the commit state,
> > > > > which is still calling intel_can_enable_sagv function. Fix that
> > > > > by just analyzing the current global bw_state object - because
> > > > > we simply have no other objects related to that.
> > > > >
> > > > > v13: - Rebased, fixed warnings regarding long lines
> > > > > - Changed function call sites from intel_atomic_bw* to
> > > > > intel_wb_* as was suggested.(Jani Nikula)
> > > > > - Taken ddb_state_changed and bw_state_changed into use.
> > > > >
> > > > > v14: - total_affected_planes is no longer needed to check for ddb changes,
> > > > > just as active_pipe_changes.
> > > > >
> > > > > v15: - Fixed stupid mistake with uninitialized crtc in
> > > > > skl_compute_sagv_mask.
> > > > >
> > > > > v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> > > > > flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> > > > > - Added return value to intel_compute_sagv_mask which call
> > > > > intel_atomic_serialize_global_state in order to properly
> > > > > propagate EDEADLCK to drm.
> > > > > - Based on the discussion with Ville, removed active_pipe_changes
> > > > > check and also there seems to be no need for checking ddb_state_changes
> > > > > as well. Instead we just iterate through crtcs in state - having
> > > > > crtc in a state already guarantees that it is at least read-locked
> > > > > Having additional flag to check if there actually were some plane
> > > > > wm/ddb changes would be probably added later as an optimization.
> > > > > - We can't get parent atomic state from crtc_state at commit stage
> > > > > (nice drm feature), also propagating state through function call
> > > > > chain seems to be overkill and not possible(cursor legacy updates)
> > > > > Querying for bw_state object from global state is not possible as
> > > > > it might get swapped with other global state.
> > > > > So... just sticked can_sagv boolean into wm crtc state.
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> > > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> > > > > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > > > > 5 files changed, 318 insertions(+), 41 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > index b5f61463922f..4083adf4b432 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > @@ -18,6 +18,24 @@ struct intel_crtc_state;
> > > > > struct intel_bw_state {
> > > > > struct intel_global_state base;
> > > > >
> > > > > + /*
> > > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > > + * pipe allows SAGV or not.
> > > > > + */
> > > > > + u8 pipe_sagv_reject;
> > > > > +
> > > > > + /*
> > > > > + * Used to determine if we already had calculated
> > > > > + * SAGV mask for this state once.
> > > > > + */
> > > > > + bool sagv_calculated;
> > > >
> > > > Why would we even attempt to calculate it many times?
> > > >
> > > > > +
> > > > > + /*
> > > > > + * Contains final SAGV decision based on current mask,
> > > > > + * to prevent doing the same job over and over again.
> > > > > + */
> > > > > + bool can_sagv;
> > > >
> > > > This is redundant since it's just sagv_reject==0.
> > > >
> > > > > +
> > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > };
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 8f23c4d51c33..9e0058a78ea6 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > - &sw_plane_wm->wm[level]))
> > > > > + &sw_plane_wm->wm[level]) ||
> > > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > + &sw_plane_wm->sagv_wm0) &&
> > > > > + (level == 0)))
> > > >
> > > > Pointless parens. Also we should do the check as
> > > > 'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
> > > > level != 0.
> > > >
> > > > I guess we can't read out sagv state due to the silly pcode interface?
> > > >
> > > > > continue;
> > > > >
> > > > > drm_err(&dev_priv->drm,
> > > > > @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > - &sw_plane_wm->wm[level]))
> > > > > + &sw_plane_wm->wm[level]) ||
> > > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > + &sw_plane_wm->sagv_wm0) &&
> > > > > + (level == 0)))
> > > > > continue;
> > > > >
> > > > > drm_err(&dev_priv->drm,
> > > > > @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > > * SKL workaround: bspec recommends we disable the SAGV when we
> > > > > * have more then one pipe enabled
> > > > > */
> > > > > - if (!intel_can_enable_sagv(state))
> > > > > - intel_disable_sagv(dev_priv);
> > > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > > + if (!intel_can_enable_sagv(state))
> > > > > + intel_disable_sagv(dev_priv);
> > > > > + }
> > > > >
> > > > > intel_modeset_verify_disabled(dev_priv, state);
> > > > > }
> > > > > @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > > if (state->modeset)
> > > > > intel_verify_planes(state);
> > > > >
> > > > > - if (state->modeset && intel_can_enable_sagv(state))
> > > > > - intel_enable_sagv(dev_priv);
> > > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > > + if (state->modeset && intel_can_enable_sagv(state))
> > > > > + intel_enable_sagv(dev_priv);
> > > > > + }
> > > > >
> > > > > drm_atomic_helper_commit_hw_done(&state->base);
> > > > >
> > > > > @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > > > >
> > > > > if (state->global_state_changed) {
> > > > > assert_global_state_locked(dev_priv);
> > > > > -
> > > > > dev_priv->active_pipes = state->active_pipes;
> > > > > }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 5e00e611f077..da0308b87dad 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -669,11 +669,14 @@ struct skl_plane_wm {
> > > > > struct skl_wm_level wm[8];
> > > > > struct skl_wm_level uv_wm[8];
> > > > > struct skl_wm_level trans_wm;
> > > > > + struct skl_wm_level sagv_wm0;
> > > > > + struct skl_wm_level uv_sagv_wm0;
> > > > > bool is_planar;
> > > > > };
> > > > >
> > > > > struct skl_pipe_wm {
> > > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > + bool can_sagv;
> > > > > };
> > > > >
> > > > > enum vlv_wm_level {
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index c72fa59a8302..f598b55f4abc 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -43,6 +43,7 @@
> > > > > #include "i915_fixed.h"
> > > > > #include "i915_irq.h"
> > > > > #include "i915_trace.h"
> > > > > +#include "display/intel_bw.h"
> > > > > #include "intel_pm.h"
> > > > > #include "intel_sideband.h"
> > > > > #include "../../../platform/x86/intel_ips.h"
> > > > > @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > > > > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > > > > }
> > > > >
> > > > > -static bool
> > > > > +bool
> > > > > intel_has_sagv(struct drm_i915_private *dev_priv)
> > > > > {
> > > > > /* HACK! */
> > > > > @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> > > >
> > > > This extraction looks to be trivially done as a separate patch.
> > > >
> > > > > {
> > > > > - struct drm_device *dev = state->base.dev;
> > > > > + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > struct intel_crtc *crtc;
> > > > > struct intel_plane *plane;
> > > > > - struct intel_crtc_state *crtc_state;
> > > > > - enum pipe pipe;
> > > > > int level, latency;
> > > > >
> > > > > - if (!intel_has_sagv(dev_priv))
> > > > > - return false;
> > > > > -
> > > > > - /*
> > > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > > - */
> > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > - return true;
> > > > > + crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > >
> > > > > - /*
> > > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > - * more then one pipe enabled
> > > > > - */
> > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> > > > > return false;
> > > > >
> > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > -
> > > > > - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > > + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > > > > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> > > > > + pipe_name(crtc->pipe));
> > > > > return false;
> > > > > + }
> > > > >
> > > > > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > struct skl_plane_wm *wm =
> > > > > @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > * incur memory latencies higher than sagv_block_time_us we
> > > > > * can't enable SAGV.
> > > > > */
> > > > > - if (latency < dev_priv->sagv_block_time_us)
> > > > > + if (latency < dev_priv->sagv_block_time_us) {
> > > > > + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> > > > > + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> > > > > return false;
> > > > > + }
> > > > > }
> > > > >
> > > > > return true;
> > > > > }
> > > > >
> > > > > +static bool
> > > > > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> > > > > +
> > > > > +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> > > > > +{
> > > > > + return bw_state->pipe_sagv_reject == 0;
> > > > > +}
> > > > > +
> > > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > +{
> > > > > + int ret;
> > > > > + struct drm_device *dev = state->base.dev;
> > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > + struct intel_crtc *crtc;
> > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > > + struct intel_bw_state *old_bw_state = NULL;
> > > > > + int i;
> > > > > +
> > > > > + /*
> > > > > + * If SAGV is not supported we just can't do anything
> > > > > + * not even set or reject SAGV points - just bail out.
> > > > > + * Thus avoid needless calculations.
> > > > > + */
> > > > > + if (!intel_has_sagv(dev_priv))
> > > > > + return 0;
> > > > > +
> > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > + new_crtc_state, i) {
> > > > > + bool pipe_sagv_enable;
> > > > > +
> > > > > + new_bw_state = intel_bw_get_state(state);
> > > > > + old_bw_state = intel_bw_get_old_state(state);
> > > > > +
> > > > > + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> > > > > + WARN(1, "Could not get bw_state\n");
> > > > > + return -EINVAL;
> > > >
> > > > What is this?
> > > >
> > > > > + }
> > > > > +
> > > > > + new_bw_state->sagv_calculated = false;
> > > > > +
> > > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > > + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > > + else
> > > > > + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > > +
> > > > > + if (pipe_sagv_enable)
> > > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > + else
> > > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > + }
> > > > > +
> > > > > + if (!new_bw_state || !old_bw_state)
> > > > > + return 0;
> > > > > +
> > > > > + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> > > > > + new_bw_state->sagv_calculated = true;
> > > > > +
> > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > + new_crtc_state, i) {
> > > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > +
> > > > > + /*
> > > > > + * Due to drm limitation at commit state, when
> > > > > + * changes are written the whole atomic state is
> > > > > + * zeroed away => which prevents from using it,
> > > > > + * so just sticking it into pipe wm state for
> > > > > + * keeping it simple - anyway this is related to wm.
> > > > > + * Proper way in ideal universe would be of course not
> > > > > + * to lose parent atomic state object from child crtc_state,
> > > > > + * and stick to OOP programming principles, which had been
> > > > > + * scientifically proven to work.
> > > > > + */
> > > > > + pipe_wm->can_sagv = new_bw_state->can_sagv;
> > > >
> > > > I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
> > > > what it does.
> > > >
> > > > > + }
> > > > > +
> > > > > + /*
> > > > > + * For SAGV we need to account all the pipes,
> > > > > + * not only the ones which are in state currently.
> > > > > + * Grab all locks if we detect that we are actually
> > > > > + * going to do something.
> > > > > + */
> > > > > + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> > > > > + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> > > > > + state,
> > > > > + old_bw_state->pipe_sagv_reject,
> > > > > + new_bw_state->pipe_sagv_reject);
> > > > > +
> > > > > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > > + if (ret) {
> > > > > + DRM_DEBUG_KMS("Could not serialize global state\n");
> > > > > + return ret;
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +/*
> > > > > + * This function to be used before swap state
> > > > > + */
> > > > > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > +{
> > > > > + struct drm_device *dev = state->base.dev;
> > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > + struct intel_bw_state *bw_state;
> > > > > +
> > > > > + if (!intel_has_sagv(dev_priv)) {
> > > > > + DRM_DEBUG_KMS("No SAGV support detected\n");
> > > > > + return false;
> > > > > + }
> > > > > +
> > > > > + bw_state = intel_bw_get_state(state);
> > > > > +
> > > > > + if (IS_ERR_OR_NULL(bw_state)) {
> > > >
> > > > It can't be NULL. And if you get an error you must propagate it upwards.
> > >
> > > Can you please elaborate what I should do here?
> > > Just want to save some time without wasting time guessing.
> > > The options are:
> > >
> > > 1) If I propagate an error upwards, I obviously need to change a signature
> > > to int intel_can_enable_sagv, also if I do that usage at legacy callsites
> > > for this function will change, i.e you won't be able to call it like
> > > if (intel_can_enable_sagv()) anymore. Is it that what you want?
> > > Should note also that most of the legacy call sites are from commit_tail
> > > which wouldn't even propagate it further, because as you know it is already
> > > point of no return.
> >
> > Looks like intel_can_enable_sagv() should not exist anymore. We should
> > just precompute the sagv mask in the bw atomic check, and then the commit
> > time checks will simply become checks of the sagv mask.
>
> Was thinking about that, but then the question is how to deal with legacy
> stuff - for instance, skl doesn't have QGV points at all, as I understand
> some platforms just have it as a switch so we'll have to have somekind
> of code like this anyway, i.e just checking if we can and then switch.
We should just have two different ways to calculate whether a pipe can
do sagv or not, one for skl+ another for icl+. Then we use the
appropriate method when computing the sagv mask.
>
> Or basically we would be just inlining the intel_can_enable_sagv to
> intel_atomic_commit_tail as I understand. Because yep for gen >=11
> it just a matter of pre/post updating qgv points, but for skl we
> still need some condition to check when we are calling intel_enable/disable sagv
>
>
> Stan
>
>
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
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Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
2020-03-23 14:50 ` Ville Syrjälä
@ 2020-03-23 14:58 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2020-03-23 14:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Mar 23, 2020 at 04:50:08PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 23, 2020 at 04:36:16PM +0200, Lisovskiy, Stanislav wrote:
> > On Mon, Mar 23, 2020 at 04:18:36PM +0200, Ville Syrjälä wrote:
> > > On Fri, Mar 20, 2020 at 02:51:41PM +0200, Lisovskiy, Stanislav wrote:
> > > > On Wed, Mar 11, 2020 at 06:31:30PM +0200, Ville Syrjälä wrote:
> > > > > On Mon, Mar 09, 2020 at 06:12:00PM +0200, Stanislav Lisovskiy wrote:
> > > > > > Currently intel_can_enable_sagv function contains
> > > > > > a mix of workarounds for different platforms
> > > > > > some of them are not valid for gens >= 11 already,
> > > > > > so lets split it into separate functions.
> > > > > >
> > > > > > v2:
> > > > > > - Rework watermark calculation algorithm to
> > > > > > attempt to calculate Level 0 watermark
> > > > > > with added sagv block time latency and
> > > > > > check if it fits in DBuf in order to
> > > > > > determine if SAGV can be enabled already
> > > > > > at this stage, just as BSpec 49325 states.
> > > > > > if that fails rollback to usual Level 0
> > > > > > latency and disable SAGV.
> > > > > > - Remove unneeded tabs(James Ausmus)
> > > > > >
> > > > > > v3: Rebased the patch
> > > > > >
> > > > > > v4: - Added back interlaced check for Gen12 and
> > > > > > added separate function for TGL SAGV check
> > > > > > (thanks to James Ausmus for spotting)
> > > > > > - Removed unneeded gen check
> > > > > > - Extracted Gen12 SAGV decision making code
> > > > > > to a separate function from skl_compute_wm
> > > > > >
> > > > > > v5: - Added SAGV global state to dev_priv, because
> > > > > > we need to track all pipes, not only those
> > > > > > in atomic state. Each pipe has now correspondent
> > > > > > bit mask reflecting, whether it can tolerate
> > > > > > SAGV or not(thanks to Ville Syrjala for suggestions).
> > > > > > - Now using active flag instead of enable in crc
> > > > > > usage check.
> > > > > >
> > > > > > v6: - Fixed rebase conflicts
> > > > > >
> > > > > > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
> > > > > > calls when copying level 0 water marks for enabled SAGV, to
> > > > > > fix this now simply using that field right away, without copying,
> > > > > > for that introduced a new wm_level accessor which decides which
> > > > > > wm_level to return based on SAGV state.
> > > > > >
> > > > > > v8: - Protect crtc_sagv_mask same way as we do for other global state
> > > > > > changes: i.e check if changes are needed, then grab all crtc locks
> > > > > > to serialize the changes(Ville Syrjälä)
> > > > > > - Add crtc_sagv_mask caching in order to avoid needless recalculations
> > > > > > (Matthew Roper)
> > > > > > - Put back Gen12 SAGV switch in order to get it enabled in separate
> > > > > > patch(Matthew Roper)
> > > > > > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
> > > > > > - Check if there are no active pipes in intel_can_enable_sagv
> > > > > > instead of platform specific functions(Matthew Roper), same
> > > > > > for intel_has_sagv check.
> > > > > >
> > > > > > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
> > > > > > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
> > > > > > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
> > > > > > - Extracted skl_plane_wm_level function and passing latency to
> > > > > > separate patches(Ville Syrjälä)
> > > > > > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
> > > > > > (Ville Syrjälä)
> > > > > > - Now using simple assignment for sagv_wm0 as it contains only
> > > > > > pod types and no pointers(Ville Syrjälä)
> > > > > > - Fixed intel_can_enable_sagv not to do double duty, now it only
> > > > > > check SAGV bits by ANDing those between local and global state.
> > > > > > The SAGV masks are now computed after watermarks are available,
> > > > > > in order to be able to figure out if ddb ranges are fitting nicely.
> > > > > > (Ville Syrjälä)
> > > > > > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
> > > > > > when using skl_plane_wm_level accessor, as we had previously for
> > > > > > Gen11+ color plane and regular wm levels, so probably both
> > > > > > has to be recalculated with additional SAGV block time for Level 0.
> > > > > >
> > > > > > v10: - Starting to use new global state for storing pipe_sagv_mask
> > > > > >
> > > > > > v11: - Fixed rebase conflict with recent drm-tip
> > > > > > - Check if we really need to recalculate SAGV mask, otherwise
> > > > > > bail out without making any changes.
> > > > > > - Use cached SAGV result, instead of recalculating it everytime,
> > > > > > if bw_state hasn't changed.
> > > > > >
> > > > > > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
> > > > > > if we don't recalculated watermarks, bw_state is not recalculated,
> > > > > > thus leading to SAGV state not recalculated by the commit state,
> > > > > > which is still calling intel_can_enable_sagv function. Fix that
> > > > > > by just analyzing the current global bw_state object - because
> > > > > > we simply have no other objects related to that.
> > > > > >
> > > > > > v13: - Rebased, fixed warnings regarding long lines
> > > > > > - Changed function call sites from intel_atomic_bw* to
> > > > > > intel_wb_* as was suggested.(Jani Nikula)
> > > > > > - Taken ddb_state_changed and bw_state_changed into use.
> > > > > >
> > > > > > v14: - total_affected_planes is no longer needed to check for ddb changes,
> > > > > > just as active_pipe_changes.
> > > > > >
> > > > > > v15: - Fixed stupid mistake with uninitialized crtc in
> > > > > > skl_compute_sagv_mask.
> > > > > >
> > > > > > v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
> > > > > > flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
> > > > > > - Added return value to intel_compute_sagv_mask which call
> > > > > > intel_atomic_serialize_global_state in order to properly
> > > > > > propagate EDEADLCK to drm.
> > > > > > - Based on the discussion with Ville, removed active_pipe_changes
> > > > > > check and also there seems to be no need for checking ddb_state_changes
> > > > > > as well. Instead we just iterate through crtcs in state - having
> > > > > > crtc in a state already guarantees that it is at least read-locked
> > > > > > Having additional flag to check if there actually were some plane
> > > > > > wm/ddb changes would be probably added later as an optimization.
> > > > > > - We can't get parent atomic state from crtc_state at commit stage
> > > > > > (nice drm feature), also propagating state through function call
> > > > > > chain seems to be overkill and not possible(cursor legacy updates)
> > > > > > Querying for bw_state object from global state is not possible as
> > > > > > it might get swapped with other global state.
> > > > > > So... just sticked can_sagv boolean into wm crtc state.
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 18 +
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 23 +-
> > > > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 314 ++++++++++++++++--
> > > > > > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > > > > > 5 files changed, 318 insertions(+), 41 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > index b5f61463922f..4083adf4b432 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > @@ -18,6 +18,24 @@ struct intel_crtc_state;
> > > > > > struct intel_bw_state {
> > > > > > struct intel_global_state base;
> > > > > >
> > > > > > + /*
> > > > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > > > + * pipe allows SAGV or not.
> > > > > > + */
> > > > > > + u8 pipe_sagv_reject;
> > > > > > +
> > > > > > + /*
> > > > > > + * Used to determine if we already had calculated
> > > > > > + * SAGV mask for this state once.
> > > > > > + */
> > > > > > + bool sagv_calculated;
> > > > >
> > > > > Why would we even attempt to calculate it many times?
> > > > >
> > > > > > +
> > > > > > + /*
> > > > > > + * Contains final SAGV decision based on current mask,
> > > > > > + * to prevent doing the same job over and over again.
> > > > > > + */
> > > > > > + bool can_sagv;
> > > > >
> > > > > This is redundant since it's just sagv_reject==0.
> > > > >
> > > > > > +
> > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > };
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 8f23c4d51c33..9e0058a78ea6 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -14010,7 +14010,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > - &sw_plane_wm->wm[level]))
> > > > > > + &sw_plane_wm->wm[level]) ||
> > > > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > + &sw_plane_wm->sagv_wm0) &&
> > > > > > + (level == 0)))
> > > > >
> > > > > Pointless parens. Also we should do the check as
> > > > > 'level == 0 && wm_equals(sagv)' to skip the pointless comparison when
> > > > > level != 0.
> > > > >
> > > > > I guess we can't read out sagv state due to the silly pcode interface?
> > > > >
> > > > > > continue;
> > > > > >
> > > > > > drm_err(&dev_priv->drm,
> > > > > > @@ -14065,7 +14068,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > - &sw_plane_wm->wm[level]))
> > > > > > + &sw_plane_wm->wm[level]) ||
> > > > > > + (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > + &sw_plane_wm->sagv_wm0) &&
> > > > > > + (level == 0)))
> > > > > > continue;
> > > > > >
> > > > > > drm_err(&dev_priv->drm,
> > > > > > @@ -15544,8 +15550,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > > > * SKL workaround: bspec recommends we disable the SAGV when we
> > > > > > * have more then one pipe enabled
> > > > > > */
> > > > > > - if (!intel_can_enable_sagv(state))
> > > > > > - intel_disable_sagv(dev_priv);
> > > > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > > > + if (!intel_can_enable_sagv(state))
> > > > > > + intel_disable_sagv(dev_priv);
> > > > > > + }
> > > > > >
> > > > > > intel_modeset_verify_disabled(dev_priv, state);
> > > > > > }
> > > > > > @@ -15645,8 +15653,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > > > if (state->modeset)
> > > > > > intel_verify_planes(state);
> > > > > >
> > > > > > - if (state->modeset && intel_can_enable_sagv(state))
> > > > > > - intel_enable_sagv(dev_priv);
> > > > > > + if (INTEL_GEN(dev_priv) < 11) {
> > > > > > + if (state->modeset && intel_can_enable_sagv(state))
> > > > > > + intel_enable_sagv(dev_priv);
> > > > > > + }
> > > > > >
> > > > > > drm_atomic_helper_commit_hw_done(&state->base);
> > > > > >
> > > > > > @@ -15798,7 +15808,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > > > > >
> > > > > > if (state->global_state_changed) {
> > > > > > assert_global_state_locked(dev_priv);
> > > > > > -
> > > > > > dev_priv->active_pipes = state->active_pipes;
> > > > > > }
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 5e00e611f077..da0308b87dad 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -669,11 +669,14 @@ struct skl_plane_wm {
> > > > > > struct skl_wm_level wm[8];
> > > > > > struct skl_wm_level uv_wm[8];
> > > > > > struct skl_wm_level trans_wm;
> > > > > > + struct skl_wm_level sagv_wm0;
> > > > > > + struct skl_wm_level uv_sagv_wm0;
> > > > > > bool is_planar;
> > > > > > };
> > > > > >
> > > > > > struct skl_pipe_wm {
> > > > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > + bool can_sagv;
> > > > > > };
> > > > > >
> > > > > > enum vlv_wm_level {
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index c72fa59a8302..f598b55f4abc 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -43,6 +43,7 @@
> > > > > > #include "i915_fixed.h"
> > > > > > #include "i915_irq.h"
> > > > > > #include "i915_trace.h"
> > > > > > +#include "display/intel_bw.h"
> > > > > > #include "intel_pm.h"
> > > > > > #include "intel_sideband.h"
> > > > > > #include "../../../platform/x86/intel_ips.h"
> > > > > > @@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > > > > > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > > > > > }
> > > > > >
> > > > > > -static bool
> > > > > > +bool
> > > > > > intel_has_sagv(struct drm_i915_private *dev_priv)
> > > > > > {
> > > > > > /* HACK! */
> > > > > > @@ -3757,39 +3758,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > > > return 0;
> > > > > > }
> > > > > >
> > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> > > > >
> > > > > This extraction looks to be trivially done as a separate patch.
> > > > >
> > > > > > {
> > > > > > - struct drm_device *dev = state->base.dev;
> > > > > > + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > > struct intel_crtc *crtc;
> > > > > > struct intel_plane *plane;
> > > > > > - struct intel_crtc_state *crtc_state;
> > > > > > - enum pipe pipe;
> > > > > > int level, latency;
> > > > > >
> > > > > > - if (!intel_has_sagv(dev_priv))
> > > > > > - return false;
> > > > > > -
> > > > > > - /*
> > > > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > > > - */
> > > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > > - return true;
> > > > > > + crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > >
> > > > > > - /*
> > > > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > > - * more then one pipe enabled
> > > > > > - */
> > > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > > + if ((INTEL_GEN(dev_priv) <= 9) && (hweight8(state->active_pipes) > 1))
> > > > > > return false;
> > > > > >
> > > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > > -
> > > > > > - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > > > + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > > > > > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> > > > > > + pipe_name(crtc->pipe));
> > > > > > return false;
> > > > > > + }
> > > > > >
> > > > > > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > > struct skl_plane_wm *wm =
> > > > > > @@ -3816,13 +3803,145 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > * incur memory latencies higher than sagv_block_time_us we
> > > > > > * can't enable SAGV.
> > > > > > */
> > > > > > - if (latency < dev_priv->sagv_block_time_us)
> > > > > > + if (latency < dev_priv->sagv_block_time_us) {
> > > > > > + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> > > > > > + latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
> > > > > > return false;
> > > > > > + }
> > > > > > }
> > > > > >
> > > > > > return true;
> > > > > > }
> > > > > >
> > > > > > +static bool
> > > > > > +tgl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state);
> > > > > > +
> > > > > > +static bool intel_calculate_sagv_result(struct intel_bw_state *bw_state)
> > > > > > +{
> > > > > > + return bw_state->pipe_sagv_reject == 0;
> > > > > > +}
> > > > > > +
> > > > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > +{
> > > > > > + int ret;
> > > > > > + struct drm_device *dev = state->base.dev;
> > > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + struct intel_crtc *crtc;
> > > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > > > + struct intel_bw_state *old_bw_state = NULL;
> > > > > > + int i;
> > > > > > +
> > > > > > + /*
> > > > > > + * If SAGV is not supported we just can't do anything
> > > > > > + * not even set or reject SAGV points - just bail out.
> > > > > > + * Thus avoid needless calculations.
> > > > > > + */
> > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > + return 0;
> > > > > > +
> > > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > + new_crtc_state, i) {
> > > > > > + bool pipe_sagv_enable;
> > > > > > +
> > > > > > + new_bw_state = intel_bw_get_state(state);
> > > > > > + old_bw_state = intel_bw_get_old_state(state);
> > > > > > +
> > > > > > + if (IS_ERR_OR_NULL(new_bw_state) || IS_ERR_OR_NULL(old_bw_state)) {a
> > > > > > + WARN(1, "Could not get bw_state\n");
> > > > > > + return -EINVAL;
> > > > >
> > > > > What is this?
> > > > >
> > > > > > + }
> > > > > > +
> > > > > > + new_bw_state->sagv_calculated = false;
> > > > > > +
> > > > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > > > + pipe_sagv_enable = tgl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > > > + else
> > > > > > + pipe_sagv_enable = skl_can_enable_sagv_on_pipe(new_crtc_state);
> > > > > > +
> > > > > > + if (pipe_sagv_enable)
> > > > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > + else
> > > > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > + }
> > > > > > +
> > > > > > + if (!new_bw_state || !old_bw_state)
> > > > > > + return 0;
> > > > > > +
> > > > > > + new_bw_state->can_sagv = intel_calculate_sagv_result(new_bw_state);
> > > > > > + new_bw_state->sagv_calculated = true;
> > > > > > +
> > > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > + new_crtc_state, i) {
> > > > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > +
> > > > > > + /*
> > > > > > + * Due to drm limitation at commit state, when
> > > > > > + * changes are written the whole atomic state is
> > > > > > + * zeroed away => which prevents from using it,
> > > > > > + * so just sticking it into pipe wm state for
> > > > > > + * keeping it simple - anyway this is related to wm.
> > > > > > + * Proper way in ideal universe would be of course not
> > > > > > + * to lose parent atomic state object from child crtc_state,
> > > > > > + * and stick to OOP programming principles, which had been
> > > > > > + * scientifically proven to work.
> > > > > > + */
> > > > > > + pipe_wm->can_sagv = new_bw_state->can_sagv;
> > > > >
> > > > > I would probably name that wm->can_sagv as wm->use_sagv_wm so it's clear
> > > > > what it does.
> > > > >
> > > > > > + }
> > > > > > +
> > > > > > + /*
> > > > > > + * For SAGV we need to account all the pipes,
> > > > > > + * not only the ones which are in state currently.
> > > > > > + * Grab all locks if we detect that we are actually
> > > > > > + * going to do something.
> > > > > > + */
> > > > > > + if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
> > > > > > + DRM_DEBUG_KMS("State %p: old sagv mask 0x%x, new sagv mask 0x%x\n",
> > > > > > + state,
> > > > > > + old_bw_state->pipe_sagv_reject,
> > > > > > + new_bw_state->pipe_sagv_reject);
> > > > > > +
> > > > > > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > > > + if (ret) {
> > > > > > + DRM_DEBUG_KMS("Could not serialize global state\n");
> > > > > > + return ret;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +/*
> > > > > > + * This function to be used before swap state
> > > > > > + */
> > > > > > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > +{
> > > > > > + struct drm_device *dev = state->base.dev;
> > > > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + struct intel_bw_state *bw_state;
> > > > > > +
> > > > > > + if (!intel_has_sagv(dev_priv)) {
> > > > > > + DRM_DEBUG_KMS("No SAGV support detected\n");
> > > > > > + return false;
> > > > > > + }
> > > > > > +
> > > > > > + bw_state = intel_bw_get_state(state);
> > > > > > +
> > > > > > + if (IS_ERR_OR_NULL(bw_state)) {
> > > > >
> > > > > It can't be NULL. And if you get an error you must propagate it upwards.
> > > >
> > > > Can you please elaborate what I should do here?
> > > > Just want to save some time without wasting time guessing.
> > > > The options are:
> > > >
> > > > 1) If I propagate an error upwards, I obviously need to change a signature
> > > > to int intel_can_enable_sagv, also if I do that usage at legacy callsites
> > > > for this function will change, i.e you won't be able to call it like
> > > > if (intel_can_enable_sagv()) anymore. Is it that what you want?
> > > > Should note also that most of the legacy call sites are from commit_tail
> > > > which wouldn't even propagate it further, because as you know it is already
> > > > point of no return.
> > >
> > > Looks like intel_can_enable_sagv() should not exist anymore. We should
> > > just precompute the sagv mask in the bw atomic check, and then the commit
> > > time checks will simply become checks of the sagv mask.
> >
> > Was thinking about that, but then the question is how to deal with legacy
> > stuff - for instance, skl doesn't have QGV points at all, as I understand
> > some platforms just have it as a switch so we'll have to have somekind
> > of code like this anyway, i.e just checking if we can and then switch.
>
> We should just have two different ways to calculate whether a pipe can
> do sagv or not, one for skl+ another for icl+. Then we use the
> appropriate method when computing the sagv mask.
Yes, I have two ways already, but I would like to have sagv mask
computed in some centralized place i.e intel_compute_sagv_mask, so that
each part of code has its own responsiblity and it is not spread across different
functions/areas(SOLID).
As I understand you want wm sagv checks to be done in allocate_pipe_ddb - ok
I can transfer it there, but still I would like pipe_reject_mask to be set
in a single place for obvious reasons.
Also still the question is how we evaluate pipe_reject_mask - as I understand
from you mean that I just nuke intel_can_enable_sagv and start just checking
pipe_reject_mask == 0 instead everywhere.
I'm still more in favour of having helpers for that - however in order to
avoid continuing wasting time discussing err propagation and other secondary
stuff - I'm fine with this :)
>
> >
> > Or basically we would be just inlining the intel_can_enable_sagv to
> > intel_atomic_commit_tail as I understand. Because yep for gen >=11
> > it just a matter of pre/post updating qgv points, but for skl we
> > still need some condition to check when we are calling intel_enable/disable sagv
> >
> >
> > Stan
> >
> >
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2020-03-23 15:02 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-10 14:32 ` Ville Syrjälä
2020-03-10 14:54 ` Lisovskiy, Stanislav
2020-03-10 20:44 ` Ville Syrjälä
2020-03-11 9:16 ` Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
[not found] ` <20200311160727.GA13686@intel.com>
2020-03-13 8:42 ` Lisovskiy, Stanislav
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
[not found] ` <20200311160854.GB13686@intel.com>
2020-03-13 8:49 ` Lisovskiy, Stanislav
2020-03-13 13:26 ` Ville Syrjälä
2020-03-13 13:57 ` Lisovskiy, Stanislav
2020-03-13 14:14 ` Ville Syrjälä
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2020-03-11 9:13 ` Stanislav Lisovskiy
[not found] ` <20200311163130.GC13686@intel.com>
2020-03-18 11:52 ` Lisovskiy, Stanislav
2020-03-18 12:50 ` Ville Syrjälä
2020-03-19 13:09 ` Lisovskiy, Stanislav
2020-03-20 12:51 ` Lisovskiy, Stanislav
2020-03-23 14:18 ` Ville Syrjälä
2020-03-23 14:36 ` Lisovskiy, Stanislav
2020-03-23 14:50 ` Ville Syrjälä
2020-03-23 14:58 ` Lisovskiy, Stanislav
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-03-09 16:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
2020-03-10 13:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
2020-03-11 14:20 ` Lisovskiy, Stanislav
2020-03-11 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4) Patchwork
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