From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39775C18E5A for ; Mon, 9 Mar 2020 16:57:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1930024670 for ; Mon, 9 Mar 2020 16:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727231AbgCIQ5y (ORCPT ); Mon, 9 Mar 2020 12:57:54 -0400 Received: from foss.arm.com ([217.140.110.172]:54694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727101AbgCIQ5y (ORCPT ); Mon, 9 Mar 2020 12:57:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2E1C1FB; Mon, 9 Mar 2020 09:57:53 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 332003F534; Mon, 9 Mar 2020 09:57:51 -0700 (PDT) Date: Mon, 9 Mar 2020 16:57:49 +0000 From: Catalin Marinas To: Russell King - ARM Linux admin Cc: Arnd Bergmann , Nishanth Menon , Santosh Shilimkar , Tero Kristo , Linux ARM , Michal Hocko , Rik van Riel , Santosh Shilimkar , Dave Chinner , Linux Kernel Mailing List , Linux-MM , Yafang Shao , Al Viro , Johannes Weiner , linux-fsdevel , kernel-team@fb.com, Kishon Vijay Abraham I , Linus Torvalds , Andrew Morton , Roman Gushchin Subject: Re: [PATCH] vfs: keep inodes with page cache off the inode shrinker LRU Message-ID: <20200309165749.GB4124965@arrakis.emea.arm.com> References: <20200212085004.GL25745@shell.armlinux.org.uk> <671b05bc-7237-7422-3ece-f1a4a3652c92@oracle.com> <7c4c1459-60d5-24c8-6eb9-da299ead99ea@oracle.com> <20200306203439.peytghdqragjfhdx@kahuna> <20200309155945.GA4124965@arrakis.emea.arm.com> <20200309160919.GM25745@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200309160919.GM25745@shell.armlinux.org.uk> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 09, 2020 at 04:09:19PM +0000, Russell King wrote: > On Mon, Mar 09, 2020 at 03:59:45PM +0000, Catalin Marinas wrote: > > On Sun, Mar 08, 2020 at 11:58:52AM +0100, Arnd Bergmann wrote: > > > - revisit CONFIG_VMSPLIT_4G_4G for arm32 (and maybe mips32) > > > to see if it can be done, and what the overhead is. This is probably > > > more work than the others combined, but also the most promising > > > as it allows the most user address space and physical ram to be used. > > > > A rough outline of such support (and likely to miss some corner cases): > > > > 1. Kernel runs with its own ASID and non-global page tables. > > > > 2. Trampoline code on exception entry/exit to handle the TTBR0 switching > > between user and kernel. > > > > 3. uaccess routines need to be reworked to pin the user pages in memory > > (get_user_pages()) and access them via the kernel address space. > > > > Point 3 is probably the ugliest and it would introduce a noticeable > > slowdown in certain syscalls. > > We also need to consider that it has implications for the single-kernel > support; a kernel doing this kind of switching would likely be horrid > for a kernel supporting v6+ with VIPT aliasing caches. Good point. I think with VIPT aliasing cache uaccess would have to flush the cache before/after access, depending on direction. > Would we be adding a new red line between kernels supporting > VIPT-aliasing caches (present in earlier v6 implementations) and > kernels using this system? get_user_pages() should handle the flush_dcache_page() call and the latter would dial with the aliases. But this adds heavily to the cost of the uaccess. Maybe some trick with temporarily locking the user page table and copying the user pmd into a dedicated kernel pmd, then accessing the user via this location. The fault handler would need to figure out the real user address and I'm not sure how we deal with the page table lock (or mmap_sem). An alternative to the above would be to have all uaccess routines in a trampoline which restores the user pgd but with only a couple of pmds for mapping the kernel address temporarily. This would avoid the issue of concurrent modification of the user page tables. Anyway, I don't think any of the above looks better than highmem. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD2D8C18E5B for ; Mon, 9 Mar 2020 16:57:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 92347222D9 for ; Mon, 9 Mar 2020 16:57:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L2N642iF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 92347222D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=I29ywSeD+7k4SstAV6geh80SWyaK3FVPAX6tqFX5SVo=; b=L2N642iFPF8p1h 2wtXsLhb1HXUO9RNc5GCtfCLxwLQ2WSIlnGsqfcQVPrI6CmOZauZ/QFpFj2X8BA9XbQMNUuKx1N6j /IU2evVytuWpWTqtHJxGToGQGpYkp/MK/7g5cD73U7uFI4Bu/oOgpxJsA2NrBwPrRkIqub6Qx1cr8 mrMzwBHxYFV1xNdJk59cLK6A1HxGKua4z0LRbDgbIVq/i+CaTnqghypMz0bQaSkn0XjrrZ3HxSQpC CLOGI6Th9LXXXQlhcu4PVqHuvD6yN0a6Gb0vFGclkm5jWmyUWg/y7K8DOcZZ1tqjxAP3kgkxxMfyd dCw40gdJCPaQ9JsNotLg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBLj3-0002UR-4k; Mon, 09 Mar 2020 16:57:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBLj0-0002U1-Dj for linux-arm-kernel@lists.infradead.org; Mon, 09 Mar 2020 16:57:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2E1C1FB; Mon, 9 Mar 2020 09:57:53 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 332003F534; Mon, 9 Mar 2020 09:57:51 -0700 (PDT) Date: Mon, 9 Mar 2020 16:57:49 +0000 From: Catalin Marinas To: Russell King - ARM Linux admin Subject: Re: [PATCH] vfs: keep inodes with page cache off the inode shrinker LRU Message-ID: <20200309165749.GB4124965@arrakis.emea.arm.com> References: <20200212085004.GL25745@shell.armlinux.org.uk> <671b05bc-7237-7422-3ece-f1a4a3652c92@oracle.com> <7c4c1459-60d5-24c8-6eb9-da299ead99ea@oracle.com> <20200306203439.peytghdqragjfhdx@kahuna> <20200309155945.GA4124965@arrakis.emea.arm.com> <20200309160919.GM25745@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200309160919.GM25745@shell.armlinux.org.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200309_095754_549715_22144B4A X-CRM114-Status: GOOD ( 20.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Michal Hocko , Arnd Bergmann , Rik van Riel , Roman Gushchin , Santosh Shilimkar , Dave Chinner , Linux Kernel Mailing List , Kishon Vijay Abraham I , Tero Kristo , Linux-MM , Yafang Shao , Johannes Weiner , Al Viro , Santosh Shilimkar , linux-fsdevel , kernel-team@fb.com, Linus Torvalds , Andrew Morton , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 09, 2020 at 04:09:19PM +0000, Russell King wrote: > On Mon, Mar 09, 2020 at 03:59:45PM +0000, Catalin Marinas wrote: > > On Sun, Mar 08, 2020 at 11:58:52AM +0100, Arnd Bergmann wrote: > > > - revisit CONFIG_VMSPLIT_4G_4G for arm32 (and maybe mips32) > > > to see if it can be done, and what the overhead is. This is probably > > > more work than the others combined, but also the most promising > > > as it allows the most user address space and physical ram to be used. > > > > A rough outline of such support (and likely to miss some corner cases): > > > > 1. Kernel runs with its own ASID and non-global page tables. > > > > 2. Trampoline code on exception entry/exit to handle the TTBR0 switching > > between user and kernel. > > > > 3. uaccess routines need to be reworked to pin the user pages in memory > > (get_user_pages()) and access them via the kernel address space. > > > > Point 3 is probably the ugliest and it would introduce a noticeable > > slowdown in certain syscalls. > > We also need to consider that it has implications for the single-kernel > support; a kernel doing this kind of switching would likely be horrid > for a kernel supporting v6+ with VIPT aliasing caches. Good point. I think with VIPT aliasing cache uaccess would have to flush the cache before/after access, depending on direction. > Would we be adding a new red line between kernels supporting > VIPT-aliasing caches (present in earlier v6 implementations) and > kernels using this system? get_user_pages() should handle the flush_dcache_page() call and the latter would dial with the aliases. But this adds heavily to the cost of the uaccess. Maybe some trick with temporarily locking the user page table and copying the user pmd into a dedicated kernel pmd, then accessing the user via this location. The fault handler would need to figure out the real user address and I'm not sure how we deal with the page table lock (or mmap_sem). An alternative to the above would be to have all uaccess routines in a trampoline which restores the user pgd but with only a couple of pmds for mapping the kernel address temporarily. This would avoid the issue of concurrent modification of the user page tables. Anyway, I don't think any of the above looks better than highmem. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel