tree: https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git agilex_clks_v3 head: f935b30f4dc30e7fabaf7eb5017a4754f17181f1 commit: b3b5131c30f4b0307c9762b6bf7d4127194433be [4/6] clk: socfpga: add const to _ops data structures config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout b3b5131c30f4b0307c9762b6bf7d4127194433be # save the attached .config to linux build tree GCC_VERSION=9.2.0 make.cross ARCH=arm If you fix the issue, kindly add following tag Reported-by: kbuild test robot All errors (new ones prefixed by >>): drivers/clk/socfpga/clk-pll.c: In function '__socfpga_pll_init': >> drivers/clk/socfpga/clk-pll.c:108:21: error: assignment of member 'enable' in read-only object 108 | clk_pll_ops.enable = clk_gate_ops.enable; | ^ >> drivers/clk/socfpga/clk-pll.c:109:22: error: assignment of member 'disable' in read-only object 109 | clk_pll_ops.disable = clk_gate_ops.disable; | ^ -- drivers/clk/socfpga/clk-pll-a10.c: In function '__socfpga_pll_init': >> drivers/clk/socfpga/clk-pll-a10.c:105:21: error: assignment of member 'enable' in read-only object 105 | clk_pll_ops.enable = clk_gate_ops.enable; | ^ >> drivers/clk/socfpga/clk-pll-a10.c:106:22: error: assignment of member 'disable' in read-only object 106 | clk_pll_ops.disable = clk_gate_ops.disable; | ^ -- drivers/clk/socfpga/clk-gate-a10.c: In function '__socfpga_gate_init': >> drivers/clk/socfpga/clk-gate-a10.c:120:22: error: assignment of member 'enable' in read-only object 120 | gateclk_ops.enable = clk_gate_ops.enable; | ^ >> drivers/clk/socfpga/clk-gate-a10.c:121:23: error: assignment of member 'disable' in read-only object 121 | gateclk_ops.disable = clk_gate_ops.disable; | ^ vim +/enable +108 drivers/clk/socfpga/clk-pll.c 97259e99bdc914 Steffen Trumtrar 2014-01-06 72 97259e99bdc914 Steffen Trumtrar 2014-01-06 73 static __init struct clk *__socfpga_pll_init(struct device_node *node, 97259e99bdc914 Steffen Trumtrar 2014-01-06 74 const struct clk_ops *ops) 97259e99bdc914 Steffen Trumtrar 2014-01-06 75 { 97259e99bdc914 Steffen Trumtrar 2014-01-06 76 u32 reg; 97259e99bdc914 Steffen Trumtrar 2014-01-06 77 struct clk *clk; 97259e99bdc914 Steffen Trumtrar 2014-01-06 78 struct socfpga_pll *pll_clk; 97259e99bdc914 Steffen Trumtrar 2014-01-06 79 const char *clk_name = node->name; b89cd950cbcd6a Dinh Nguyen 2014-02-19 80 const char *parent_name[SOCFPGA_MAX_PARENTS]; 97259e99bdc914 Steffen Trumtrar 2014-01-06 81 struct clk_init_data init; a30d27ed739b2c Dinh Nguyen 2014-04-14 82 struct device_node *clkmgr_np; 97259e99bdc914 Steffen Trumtrar 2014-01-06 83 int rc; 97259e99bdc914 Steffen Trumtrar 2014-01-06 84 97259e99bdc914 Steffen Trumtrar 2014-01-06 85 of_property_read_u32(node, "reg", ®); 97259e99bdc914 Steffen Trumtrar 2014-01-06 86 97259e99bdc914 Steffen Trumtrar 2014-01-06 87 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 97259e99bdc914 Steffen Trumtrar 2014-01-06 88 if (WARN_ON(!pll_clk)) 97259e99bdc914 Steffen Trumtrar 2014-01-06 89 return NULL; 97259e99bdc914 Steffen Trumtrar 2014-01-06 90 a30d27ed739b2c Dinh Nguyen 2014-04-14 91 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); a30d27ed739b2c Dinh Nguyen 2014-04-14 92 clk_mgr_base_addr = of_iomap(clkmgr_np, 0); 7f9705beeb3759 Yangtao Li 2018-12-26 93 of_node_put(clkmgr_np); a30d27ed739b2c Dinh Nguyen 2014-04-14 94 BUG_ON(!clk_mgr_base_addr); 97259e99bdc914 Steffen Trumtrar 2014-01-06 95 pll_clk->hw.reg = clk_mgr_base_addr + reg; 97259e99bdc914 Steffen Trumtrar 2014-01-06 96 97259e99bdc914 Steffen Trumtrar 2014-01-06 97 of_property_read_string(node, "clock-output-names", &clk_name); 97259e99bdc914 Steffen Trumtrar 2014-01-06 98 97259e99bdc914 Steffen Trumtrar 2014-01-06 99 init.name = clk_name; 97259e99bdc914 Steffen Trumtrar 2014-01-06 100 init.ops = ops; 97259e99bdc914 Steffen Trumtrar 2014-01-06 101 init.flags = 0; 97259e99bdc914 Steffen Trumtrar 2014-01-06 102 761d3e328c503c Dinh Nguyen 2015-06-05 103 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); b89cd950cbcd6a Dinh Nguyen 2014-02-19 104 init.parent_names = parent_name; 97259e99bdc914 Steffen Trumtrar 2014-01-06 105 pll_clk->hw.hw.init = &init; 97259e99bdc914 Steffen Trumtrar 2014-01-06 106 97259e99bdc914 Steffen Trumtrar 2014-01-06 107 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; 97259e99bdc914 Steffen Trumtrar 2014-01-06 @108 clk_pll_ops.enable = clk_gate_ops.enable; 97259e99bdc914 Steffen Trumtrar 2014-01-06 @109 clk_pll_ops.disable = clk_gate_ops.disable; 97259e99bdc914 Steffen Trumtrar 2014-01-06 110 97259e99bdc914 Steffen Trumtrar 2014-01-06 111 clk = clk_register(NULL, &pll_clk->hw.hw); 97259e99bdc914 Steffen Trumtrar 2014-01-06 112 if (WARN_ON(IS_ERR(clk))) { 97259e99bdc914 Steffen Trumtrar 2014-01-06 113 kfree(pll_clk); 97259e99bdc914 Steffen Trumtrar 2014-01-06 114 return NULL; 97259e99bdc914 Steffen Trumtrar 2014-01-06 115 } 97259e99bdc914 Steffen Trumtrar 2014-01-06 116 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 97259e99bdc914 Steffen Trumtrar 2014-01-06 117 return clk; 97259e99bdc914 Steffen Trumtrar 2014-01-06 118 } 97259e99bdc914 Steffen Trumtrar 2014-01-06 119 :::::: The code at line 108 was first introduced by commit :::::: 97259e99bdc9144d071815536f1dbc2e41c6b5a8 clk: socfpga: split clk code :::::: TO: Steffen Trumtrar :::::: CC: Mike Turquette --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org