From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Restrict gen7 w/a batch to Haswell
Date: Fri, 13 Mar 2020 17:45:35 -0700 [thread overview]
Message-ID: <20200314004535.GI1853544@intel.com> (raw)
In-Reply-To: <877dzr5fc3.fsf@gaia.fi.intel.com>
On Wed, Mar 11, 2020 at 12:57:32PM +0200, Mika Kuoppala wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > The residual w/a batch is casing system instablity on Ivybridge and
little typo here ^ ?
> > Baytrail under some workloads, so disable until resolved.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1405
> > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> > ---
> > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > index 1424582e4a9b..fdc3f10e12aa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > @@ -2088,7 +2088,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
> >
> > GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
> >
> > - if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
> > + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
this was out of the latest pull request for drm-next, but if that gets in
soon we might send with next-fixes...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > err = gen7_ctx_switch_bb_init(engine);
> > if (err)
> > goto err_ring_unpin;
> > --
> > 2.20.1
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next prev parent reply other threads:[~2020-03-14 0:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 10:36 [Intel-gfx] [PATCH] drm/i915/gt: Restrict gen7 w/a batch to Haswell Chris Wilson
2020-03-11 10:57 ` Mika Kuoppala
2020-03-14 0:45 ` Rodrigo Vivi [this message]
2020-03-12 8:33 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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