* [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH
@ 2020-03-18 14:47 Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver Ioana Ciornei
` (14 more replies)
0 siblings, 15 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
This patch set targets to add support for CONFIG_DM_ETH in DPAA2 based
SoCs. We start by adding a DM MDIO driver for the MDIO interface found
on the mEMAC. The next two patches start the transition of the ldpaa_eth
and fsl-mc drivers towards using the 'struct udevice' and probing on DTS
nodes.
Any unnecessary configurations made for the DPAA2 ethernet devices are
compiled out when CONFIG_DM_ETH. This is because any information
necessary is available in its associated DTS node.
For the moment, only configs of RDB boards are transitioned to
CONFIG_DM_ETH since its more of a straightforward move than for the QDS
ones.
As an example, the 'dm tree' output for a LS2088ARDB board looks
something like the following:
=> dm tree
Class Index Probed Driver Name
-----------------------------------------------------------
(...)
simple_bus 0 [ + ] generic_simple_bus |-- fsl-mc at 80c000000
simple_bus 1 [ + ] generic_simple_bus | `-- dpmacs
eth 0 [ + ] ldpaa_eth | |-- DPMAC1 at xfi
eth 1 [ + ] ldpaa_eth | |-- DPMAC2 at xfi
eth 2 [ + ] ldpaa_eth | |-- DPMAC3 at xfi
eth 3 [ + ] ldpaa_eth | |-- DPMAC4 at xfi
eth 4 [ + ] ldpaa_eth | |-- DPMAC5 at xfi
eth 5 [ + ] ldpaa_eth | |-- DPMAC6 at xfi
eth 6 [ + ] ldpaa_eth | |-- DPMAC7 at xfi
eth 7 [ + ] ldpaa_eth | `-- DPMAC8 at xfi
mdio 0 [ + ] fsl_ls_mdio |-- mdio at 8B96000
mdio 1 [ + ] fsl_ls_mdio `-- mdio at 8B97000
Changes in v2:
- used the positive logic (ifdef CONFIG_DM_ETH instead of ifndef)
- refactor the mdio read/write code for code reuse
Ioana Ciornei (14):
drivers: net: add Layerscape mEMAC MDIO driver
drivers: net: ldpaa: add support for probing based on the DTS
drivers: net: fsl-mc: add support for CONFIG_DM_ETH
board: ls1088ardb: transition to DM_ETH
board: ls2088ardb: transition to DM_ETH
arm: dts: lx2160a: add external MDIO nodes
arm: dts: ls2088a: add external MDIO nodes
arm: dts: ls1088a: add external MDIO nodes
arm: dts: lx2160ardb: add DPMAC and PHY nodes
arm: dts: ls2088ardb: add DPMAC and PHY nodes
arm: dts: ls1088ardb: add DPMAC and PHY nodes
configs: ls1088ardb: enable CONFIG_DM_ETH and related
configs: ls2088ardb: enable CONFIG_DM_ETH and related
configs: lx2160ardb: enable CONFIG_DM_ETH and related
arch/arm/dts/fsl-ls1088a-rdb.dts | 102 ++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 102 +++++++-
arch/arm/dts/fsl-ls2080a.dtsi | 90 ++++++-
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++
arch/arm/dts/fsl-lx2160a-rdb.dts | 52 ++++
arch/arm/dts/fsl-lx2160a.dtsi | 65 +++++
board/freescale/ls1088a/eth_ls1088ardb.c | 2 +
board/freescale/ls1088a/ls1088a.c | 5 +
board/freescale/ls2080ardb/eth_ls2080rdb.c | 7 +
board/freescale/ls2080ardb/ls2080ardb.c | 4 +
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 5 +
configs/ls1088ardb_qspi_defconfig | 5 +
...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 5 +
configs/ls1088ardb_sdcard_qspi_defconfig | 5 +
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 5 +
configs/ls1088ardb_tfa_defconfig | 5 +
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 4 +
configs/ls2088ardb_qspi_defconfig | 4 +
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 4 +
configs/ls2088ardb_tfa_defconfig | 4 +
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 4 +
configs/lx2160ardb_tfa_defconfig | 4 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/fsl-mc/mc.c | 48 +++-
drivers/net/fsl_ls_mdio.c | 146 +++++++++++
drivers/net/ldpaa_eth/ldpaa_eth.c | 231 +++++++++++++++---
drivers/net/ldpaa_eth/ldpaa_eth.h | 6 +
include/configs/ls1088ardb.h | 2 +
29 files changed, 956 insertions(+), 56 deletions(-)
create mode 100644 drivers/net/fsl_ls_mdio.c
--
2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-04-07 6:28 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS Ioana Ciornei
` (13 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Add a driver for the MDIO interface integrated in the mEMAC (Multi-rate
Ethernet Media Access Controller) and the Fman 10G Ethernet MACs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- refactor the mdio read/write code for code reuse
drivers/net/Kconfig | 7 ++
drivers/net/Makefile | 1 +
drivers/net/fsl_ls_mdio.c | 146 ++++++++++++++++++++++++++++++++++++++
3 files changed, 154 insertions(+)
create mode 100644 drivers/net/fsl_ls_mdio.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c98466..bc518f218da6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -640,4 +640,11 @@ config MVMDIO
This driver is used by the MVPP2 and MVNETA drivers.
+config FSL_LS_MDIO
+ bool "NXP Layerscape MDIO interface support"
+ depends on DM_MDIO
+ help
+ This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
+ on the mEMAC (which supports both Clauses 22 and 45).
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6e0a68834d97..6d9b8772b1a5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -83,3 +83,4 @@ obj-y += mscc_eswitch/
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
+obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c
new file mode 100644
index 000000000000..6d8332d19ae0
--- /dev/null
+++ b/drivers/net/fsl_ls_mdio.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <fsl_memac.h>
+
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+#define memac_out_32(a, v) out_le32(a, v)
+#define memac_clrbits_32(a, v) clrbits_le32(a, v)
+#define memac_setbits_32(a, v) setbits_le32(a, v)
+#else
+#define memac_out_32(a, v) out_be32(a, v)
+#define memac_clrbits_32(a, v) clrbits_be32(a, v)
+#define memac_setbits_32(a, v) setbits_be32(a, v)
+#endif
+
+static u32 memac_in_32(u32 *reg)
+{
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+ return in_le32(reg);
+#else
+ return in_be32(reg);
+#endif
+}
+
+struct fsl_ls_mdio_priv {
+ void *regs_base;
+};
+
+static u32 fsl_ls_mdio_setup_operation(struct udevice *dev, int addr, int devad,
+ int reg)
+{
+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+ struct memac_mdio_controller *regs;
+ u32 mdio_ctl;
+ u32 c45 = 1;
+
+ regs = (struct memac_mdio_controller *)(priv->regs_base);
+ if (devad == MDIO_DEVAD_NONE) {
+ c45 = 0; /* clause 22 */
+ devad = reg & 0x1f;
+ memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
+ } else {
+ memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
+ }
+
+ /* Wait till the bus is free */
+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Set the Port and Device Addrs */
+ mdio_ctl = MDIO_CTL_PORT_ADDR(addr) | MDIO_CTL_DEV_ADDR(devad);
+ memac_out_32(®s->mdio_ctl, mdio_ctl);
+
+ /* Set the register address */
+ if (c45)
+ memac_out_32(®s->mdio_addr, reg & 0xffff);
+
+ /* Wait till the bus is free */
+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ return mdio_ctl;
+}
+
+static int dm_fsl_ls_mdio_read(struct udevice *dev, int addr,
+ int devad, int reg)
+{
+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+ struct memac_mdio_controller *regs;
+ u32 mdio_ctl;
+
+ regs = (struct memac_mdio_controller *)(priv->regs_base);
+ mdio_ctl = fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
+
+ /* Initiate the read */
+ mdio_ctl |= MDIO_CTL_READ;
+ memac_out_32(®s->mdio_ctl, mdio_ctl);
+
+ /* Wait till the MDIO write is complete */
+ while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ /* Return all Fs if nothing was there */
+ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
+ return 0xffff;
+
+ return memac_in_32(®s->mdio_data) & 0xffff;
+}
+
+static int dm_fsl_ls_mdio_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 val)
+{
+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+ struct memac_mdio_controller *regs;
+
+ regs = (struct memac_mdio_controller *)(priv->regs_base);
+ fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
+
+ /* Write the value to the register */
+ memac_out_32(®s->mdio_data, MDIO_DATA(val));
+
+ /* Wait till the MDIO write is complete */
+ while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ return 0;
+}
+
+static const struct mdio_ops fsl_ls_mdio_ops = {
+ .read = dm_fsl_ls_mdio_read,
+ .write = dm_fsl_ls_mdio_write,
+};
+
+static int fsl_ls_mdio_probe(struct udevice *dev)
+{
+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
+ struct memac_mdio_controller *regs;
+
+ priv->regs_base = dev_read_addr_ptr(dev);
+ regs = (struct memac_mdio_controller *)(priv->regs_base);
+
+ memac_setbits_32(®s->mdio_stat,
+ MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
+
+ return 0;
+}
+
+static const struct udevice_id fsl_ls_mdio_of_ids[] = {
+ { .compatible = "fsl,ls-mdio" },
+};
+
+U_BOOT_DRIVER(fsl_ls_mdio) = {
+ .name = "fsl_ls_mdio",
+ .id = UCLASS_MDIO,
+ .of_match = fsl_ls_mdio_of_ids,
+ .probe = fsl_ls_mdio_probe,
+ .ops = &fsl_ls_mdio_ops,
+ .priv_auto_alloc_size = sizeof(struct fsl_ls_mdio_priv),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-04-07 6:28 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 03/14] drivers: net: fsl-mc: add support for CONFIG_DM_ETH Ioana Ciornei
` (12 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe
based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible.
In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver
and reuse the _open()/_tx()/_stop() functions already inplemented.
For the moment, the ldpaa_eth driver will support both configurations:
with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence
now has a matching 'struct udevice' made mutually exclusive based on the
state of CONFIG_DM_ETH.
Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- used the positive logic (ifdef CONFIG_DM_ETH instead of ifndef)
drivers/net/ldpaa_eth/ldpaa_eth.c | 231 +++++++++++++++++++++++++-----
drivers/net/ldpaa_eth/ldpaa_eth.h | 6 +
2 files changed, 205 insertions(+), 32 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index a3b9c152b256..f589a482b734 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -12,6 +12,7 @@
#include <net.h>
#include <hwconfig.h>
#include <phy.h>
+#include <miiphy.h>
#include <linux/compat.h>
#include <fsl-mc/fsl_dpmac.h>
@@ -19,6 +20,19 @@
#include "ldpaa_eth.h"
#ifdef CONFIG_PHYLIB
+#ifdef CONFIG_DM_ETH
+static void init_phy(struct udevice *dev)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+
+ priv->phy = dm_eth_phy_connect(dev);
+
+ if (!priv->phy)
+ return;
+
+ phy_config(priv->phy);
+}
+#else
static int init_phy(struct eth_device *dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
@@ -63,6 +77,7 @@ static int init_phy(struct eth_device *dev)
return ret;
}
#endif
+#endif
#ifdef DEBUG
@@ -128,9 +143,15 @@ static void ldpaa_eth_get_dpni_counter(void)
}
}
+#ifdef CONFIG_DM_ETH
+static void ldpaa_eth_get_dpmac_counter(struct udevice *dev)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
int err = 0;
u64 value;
@@ -263,9 +284,16 @@ error:
return;
}
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev,
+ int flags, uchar **packetp)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
+#endif
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int i = 5, err = 0, status;
@@ -322,9 +350,15 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
return err;
}
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
struct dpaa_fd fd;
u64 buffer_start;
int data_offset, err;
@@ -400,15 +434,32 @@ error:
return err;
}
+static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv)
+{
+#ifdef CONFIG_DM_ETH
+ return priv->phy;
+#else
+#ifdef CONFIG_PHYLIB
+ struct phy_device *phydev = NULL;
+ int phy_num;
+
+ /* start the phy devices one by one and update the dpmac state */
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
+ if (phydev)
+ return phydev;
+ }
+ return NULL;
+#endif
+#endif
+}
+
static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
struct dpmac_link_state *state)
{
phy_interface_t enet_if;
- int phys_detected;
-#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
- int err, phy_num;
-#endif
+ int err;
/* let's start off with maximum capabilities */
enet_if = wriop_get_enet_if(priv->dpmac_id);
@@ -420,39 +471,28 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
state->rate = SPEED_1000;
break;
}
- state->up = 1;
- phys_detected = 0;
-#ifdef CONFIG_PHYLIB
+ state->up = 1;
state->options |= DPMAC_LINK_OPT_AUTONEG;
+ phydev = ldpaa_get_phydev(priv);
- /* start the phy devices one by one and update the dpmac state */
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
- if (!phydev)
- continue;
-
- phys_detected++;
+ if (phydev) {
err = phy_startup(phydev);
if (err) {
printf("%s: Could not initialize\n", phydev->dev->name);
state->up = 0;
- break;
- }
- if (phydev->link) {
+ } else if (phydev->link) {
state->rate = min(state->rate, (uint32_t)phydev->speed);
if (!phydev->duplex)
state->options |= DPMAC_LINK_OPT_HALF_DUPLEX;
if (!phydev->autoneg)
state->options &= ~DPMAC_LINK_OPT_AUTONEG;
} else {
- /* break out of loop even if one phy is down */
state->up = 0;
- break;
}
}
-#endif
- if (!phys_detected)
+
+ if (!phydev)
state->options &= ~DPMAC_LINK_OPT_AUTONEG;
if (!state->up) {
@@ -464,9 +504,16 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
return 0;
}
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_open(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+#endif
struct dpmac_link_state dpmac_link_state = { 0 };
#ifdef DEBUG
struct dpni_link_state link_state;
@@ -474,8 +521,13 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
int err = 0;
struct dpni_queue d_queue;
+#ifdef CONFIG_DM_ETH
+ if (eth_is_active(dev))
+ return 0;
+#else
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
+#endif
if (get_mc_boot_status() != 0) {
printf("ERROR (MC is not booted)\n");
@@ -515,8 +567,13 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
if (err)
goto err_dpni_bind;
+#ifdef CONFIG_DM_ETH
+ err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, plat->enetaddr);
+#else
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, net_dev->enetaddr);
+#endif
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
@@ -589,22 +646,34 @@ err_dpmac_setup:
return err;
}
+#ifdef CONFIG_DM_ETH
+static void ldpaa_eth_stop(struct udevice *dev)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+#else
static void ldpaa_eth_stop(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
- int err = 0;
-#ifdef CONFIG_PHYLIB
- struct phy_device *phydev = NULL;
- int phy_num;
#endif
+ struct phy_device *phydev = NULL;
+ int err = 0;
+#ifdef CONFIG_DM_ETH
+ if (!eth_is_active(dev))
+ return;
+#else
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
+#endif
#ifdef DEBUG
ldpaa_eth_get_dpni_counter();
+#ifdef CONFIG_DM_ETH
+ ldpaa_eth_get_dpmac_counter(dev);
+#else
ldpaa_eth_get_dpmac_counter(net_dev);
+#endif
#endif
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
@@ -628,13 +697,9 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
if (err < 0)
printf("dpni_disable() failed\n");
-#ifdef CONFIG_PHYLIB
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
- if (phydev)
- phy_shutdown(phydev);
- }
-#endif
+ phydev = ldpaa_get_phydev(priv);
+ if (phydev)
+ phy_shutdown(phydev);
/* Free DPBP handle and reset. */
ldpaa_dpbp_free();
@@ -1027,6 +1092,107 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
return 0;
}
+#ifdef CONFIG_DM_ETH
+static int ldpaa_eth_probe(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle;
+
+ /* Nothing to do if there is no "phy-handle" in the DTS node */
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL,
+ 0, 0, &phandle)) {
+ return 0;
+ }
+
+ init_phy(dev);
+
+ return 0;
+}
+
+static uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev)
+{
+ int port_node = dev_of_offset(dev);
+
+ return fdtdec_get_uint(gd->fdt_blob, port_node, "reg", -1);
+}
+
+static const char *ldpaa_eth_get_phy_mode_str(struct udevice *dev)
+{
+ int port_node = dev_of_offset(dev);
+ const char *phy_mode_str;
+
+ phy_mode_str = fdt_getprop(gd->fdt_blob, port_node,
+ "phy-connection-type", NULL);
+ if (phy_mode_str)
+ return phy_mode_str;
+
+ phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
+ return phy_mode_str;
+}
+
+static int ldpaa_eth_bind(struct udevice *dev)
+{
+ const char *phy_mode_str = NULL;
+ uint32_t dpmac_id;
+ char eth_name[16];
+ int phy_mode = -1;
+
+ phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
+ if (phy_mode_str)
+ phy_mode = phy_get_interface_by_name(phy_mode_str);
+ if (phy_mode == -1) {
+ dev_err(dev, "incorrect phy mode\n");
+ return -EINVAL;
+ }
+
+ dpmac_id = ldpaa_eth_get_dpmac_id(dev);
+ if (dpmac_id == -1) {
+ dev_err(dev, "missing reg field from the dpmac node\n");
+ return -EINVAL;
+ }
+
+ sprintf(eth_name, "DPMAC%d@%s", dpmac_id, phy_mode_str);
+ device_set_name(dev, eth_name);
+
+ return 0;
+}
+
+static int ldpaa_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
+ const char *phy_mode_str;
+
+ priv->dpmac_id = ldpaa_eth_get_dpmac_id(dev);
+ phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
+ priv->phy_mode = phy_get_interface_by_name(phy_mode_str);
+
+ return 0;
+}
+
+static const struct eth_ops ldpaa_eth_ops = {
+ .start = ldpaa_eth_open,
+ .send = ldpaa_eth_tx,
+ .recv = ldpaa_eth_pull_dequeue_rx,
+ .stop = ldpaa_eth_stop,
+};
+
+static const struct udevice_id ldpaa_eth_of_ids[] = {
+ { .compatible = "fsl,qoriq-mc-dpmac" },
+};
+
+U_BOOT_DRIVER(ldpaa_eth) = {
+ .name = "ldpaa_eth",
+ .id = UCLASS_ETH,
+ .of_match = ldpaa_eth_of_ids,
+ .ofdata_to_platdata = ldpaa_eth_ofdata_to_platdata,
+ .bind = ldpaa_eth_bind,
+ .probe = ldpaa_eth_probe,
+ .ops = &ldpaa_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct ldpaa_eth_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+#else
+
static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
phy_interface_t enet_if)
{
@@ -1099,3 +1265,4 @@ err_netdev_init:
return err;
}
+#endif
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h
index 3f9154b5bbcd..e90513e56f9a 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -116,7 +116,13 @@ struct ldpaa_fas {
LDPAA_ETH_FAS_TIDE)
struct ldpaa_eth_priv {
+#ifdef CONFIG_DM_ETH
+ struct phy_device *phy;
+ int phy_mode;
+ bool started;
+#else
struct eth_device *net_dev;
+#endif
uint32_t dpmac_id;
uint16_t dpmac_handle;
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 03/14] drivers: net: fsl-mc: add support for CONFIG_DM_ETH
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH Ioana Ciornei
` (11 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Make any adjustments necessary in order to support DPAA2 devices probed
using CONFIG_DM_ETH. While at it, fixup some styling issues aroung the
switch-case statement.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
drivers/net/fsl-mc/mc.c | 48 ++++++++++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 07bbcc9b2311..fee372968a38 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -174,9 +174,21 @@ enum mc_fixup_type {
};
static int mc_fixup_mac_addr(void *blob, int nodeoffset,
+#ifdef CONFIG_DM_ETH
+ const char *propname, struct udevice *eth_dev,
+#else
const char *propname, struct eth_device *eth_dev,
+#endif
enum mc_fixup_type type)
{
+#ifdef CONFIG_DM_ETH
+ struct eth_pdata *plat = dev_get_platdata(eth_dev);
+ unsigned char *enetaddr = plat->enetaddr;
+ int eth_index = eth_dev->seq;
+#else
+ unsigned char *enetaddr = eth_dev->enetaddr;
+ int eth_index = eth_dev->index;
+#endif
int err = 0, len = 0, size, i;
unsigned char env_enetaddr[ARP_HLEN];
unsigned int enetaddr_32[ARP_HLEN];
@@ -184,23 +196,22 @@ static int mc_fixup_mac_addr(void *blob, int nodeoffset,
switch (type) {
case MC_FIXUP_DPL:
- /* DPL likes its addresses on 32 * ARP_HLEN bits */
- for (i = 0; i < ARP_HLEN; i++)
- enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
- val = enetaddr_32;
- len = sizeof(enetaddr_32);
- break;
-
+ /* DPL likes its addresses on 32 * ARP_HLEN bits */
+ for (i = 0; i < ARP_HLEN; i++)
+ enetaddr_32[i] = cpu_to_fdt32(enetaddr[i]);
+ val = enetaddr_32;
+ len = sizeof(enetaddr_32);
+ break;
case MC_FIXUP_DPC:
- val = eth_dev->enetaddr;
- len = ARP_HLEN;
- break;
+ val = enetaddr;
+ len = ARP_HLEN;
+ break;
}
/* MAC address property present */
if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
/* u-boot MAC addr randomly assigned - leave the present one */
- if (!eth_env_get_enetaddr_by_index("eth", eth_dev->index,
+ if (!eth_env_get_enetaddr_by_index("eth", eth_index,
env_enetaddr))
return err;
} else {
@@ -250,7 +261,11 @@ const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
}
static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+ struct udevice *eth_dev)
+#else
struct eth_device *eth_dev)
+#endif
{
int objoff = fdt_path_offset(blob, "/objects");
int dpmacoff = -1, dpnioff = -1;
@@ -334,7 +349,11 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+ struct udevice *eth_dev)
+#else
struct eth_device *eth_dev)
+#endif
{
int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
int err = 0;
@@ -377,8 +396,13 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
- char ethname[ETH_NAME_LEN];
+#ifdef CONFIG_DM_ETH
+#define ETH_NAME_LEN 20
+ struct udevice *eth_dev;
+#else
struct eth_device *eth_dev;
+#endif
+ char ethname[ETH_NAME_LEN];
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
/* port not enabled */
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (2 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 03/14] drivers: net: fsl-mc: add support for CONFIG_DM_ETH Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-04-15 12:50 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 05/14] board: ls2088ardb: " Ioana Ciornei
` (10 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
DPAA2 Ethernet devices. Compile out any unnecessary setup when
CONFIG_DM_ETH is activated.
Also, force the PCI devices to be enumerated at probe time.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
board/freescale/ls1088a/eth_ls1088ardb.c | 2 ++
board/freescale/ls1088a/ls1088a.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 01f56db0a1bf..f56ce7d9ae8e 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -18,6 +18,7 @@
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
@@ -95,6 +96,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 0bd397a0beb6..225e787c7577 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -801,6 +801,11 @@ int board_init(void)
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 05/14] board: ls2088ardb: transition to DM_ETH
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (3 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 06/14] arm: dts: lx2160a: add external MDIO nodes Ioana Ciornei
` (9 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
DPAA2 Ethernet devices. Compile out any unnecessary setup when
CONFIG_DM_ETH is activated.
Also, force the PCI devices to be enumerated at probe time.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- used the positive logic (ifdef CONFIG_DM_ETH instead of ifndef)
board/freescale/ls2080ardb/eth_ls2080rdb.c | 7 +++++++
board/freescale/ls2080ardb/ls2080ardb.c | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index b0f276e8397c..f0f6ca53cb05 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_eth_init(bd_t *bis)
{
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
@@ -99,6 +100,7 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis);
#endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
@@ -112,7 +114,12 @@ int board_eth_init(bd_t *bis)
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
+
+#ifdef CONFIG_DM_ETH
+ return 0;
+#else
return pci_eth_init(bis);
+#endif
}
#if defined(CONFIG_RESET_PHY_R)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 282aaf47fb88..5e2fc7cc9833 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -244,6 +244,10 @@ int board_init(void)
sec_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 06/14] arm: dts: lx2160a: add external MDIO nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (4 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 05/14] board: ls2088ardb: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 07/14] arm: dts: ls2088a: " Ioana Ciornei
` (8 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Add the External MDIO device nodes found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-lx2160a.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 42ce4379eceb..15f18bc4a5f7 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -363,4 +363,24 @@
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
};
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+ emdio1: mdio at 8b96000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b96000 0x0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+ emdio2: mdio at 8b97000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b97000 0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 07/14] arm: dts: ls2088a: add external MDIO nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (5 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 06/14] arm: dts: lx2160a: add external MDIO nodes Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 08/14] arm: dts: ls1088a: " Ioana Ciornei
` (7 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Add the External MDIO1 device node found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-ls2080a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 99ed33af95b4..7ff854caecd5 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -200,4 +200,19 @@
status = "disabled";
};
+ emdio1: mdio at 8B96000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ emdio2: mdio at 8B97000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 08/14] arm: dts: ls1088a: add external MDIO nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (6 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 07/14] arm: dts: ls2088a: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 09/14] arm: dts: lx2160ardb: add DPMAC and PHY nodes Ioana Ciornei
` (6 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Add the External MDIO1 device node found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-ls1088a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index abc8b21a112e..314961685070 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -197,4 +197,19 @@
method = "smc";
};
+ emdio1: mdio at 8B96000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ emdio2: mdio at 8B97000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 09/14] arm: dts: lx2160ardb: add DPMAC and PHY nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (7 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 08/14] arm: dts: ls1088a: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 10/14] arm: dts: ls2088ardb: " Ioana Ciornei
` (5 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the EMDIO1 node and describe the 2 AR8035 RGMII PHYs and
the 2 AQR107 PHYs. Also, add phy-handles for the dpmacs to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-lx2160a-rdb.dts | 52 ++++++++++++++++++++++++++++++++
arch/arm/dts/fsl-lx2160a.dtsi | 45 +++++++++++++++++++++++++++
2 files changed, 97 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index e542c6992ab8..584744368394 100644
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -21,6 +21,58 @@
};
};
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+ rgmii_phy1: ethernet-phy at 1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+ rgmii_phy2: ethernet-phy at 2 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x2>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+ aquantia_phy1: ethernet-phy at 4 {
+ /* AQR107 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x4>;
+ };
+ aquantia_phy2: ethernet-phy at 5 {
+ /* AQR107 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5>;
+ };
+};
+
&esdhc0 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 15f18bc4a5f7..17ecdc569b37 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -364,6 +364,51 @@
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
};
+ fsl_mc: fsl-mc at 80c000000 {
+ compatible = "fsl,qoriq-mc", "simple-mfd";
+ reg = <0x00000008 0x0c000000 0 0x40>,
+ <0x00000000 0x08340000 0 0x40000>;
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+ dpmacs {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpmac3: dpmac at 3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac at 4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ dpmac17: dpmac at 11 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x11>;
+ status = "disabled";
+ };
+
+ dpmac18: dpmac at 12 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x12>;
+ status = "disabled";
+ };
+ };
+ };
+
/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
emdio1: mdio at 8b96000 {
compatible = "fsl,ls-mdio";
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (8 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 09/14] arm: dts: lx2160ardb: add DPMAC and PHY nodes Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-04-15 13:02 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 11/14] arm: dts: ls1088ardb: " Ioana Ciornei
` (4 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405
and 4 x CS4340). Also, add phy-handles for the dpmacs to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-ls2080a.dtsi | 75 +++++++++++++++++++++--
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++++++++++++++++++++++
2 files changed, 157 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 7ff854caecd5..fb5777e268e4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -50,12 +50,6 @@
interrupts = <0 32 0x1>; /* edge triggered */
};
- fsl_mc: fsl-mc at 80c000000 {
- compatible = "fsl,qoriq-mc";
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- };
-
i2c0: i2c at 2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
@@ -200,6 +194,75 @@
status = "disabled";
};
+ fsl_mc: fsl-mc at 80c000000 {
+ compatible = "fsl,qoriq-mc", "simple-mfd";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+ dpmacs {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpmac1: dpmac at 1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac at 2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ dpmac3: dpmac at 3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac at 4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ dpmac5: dpmac at 5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac at 6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac at 7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac at 8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
+ status = "disabled";
+ };
+ };
+ };
+
emdio1: mdio at 8B96000 {
compatible = "fsl,ls-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 72b2177b70d9..16b9aeec966c 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -21,6 +21,94 @@
};
};
+&dpmac1 {
+ status = "okay";
+ phy-handle = <&mdio1_phy1>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-handle = <&mdio1_phy2>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&mdio1_phy3>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&mdio1_phy4>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&mdio2_phy1>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&mdio2_phy2>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-handle = <&mdio2_phy3>;
+ phy-connection-type = "xfi";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-handle = <&mdio2_phy4>;
+ phy-connection-type = "xfi";
+};
+
+&emdio1 {
+ status = "okay";
+
+ /* CS4340 PHYs */
+ mdio1_phy1: emdio1_phy at 1 {
+ reg = <0x10>;
+ };
+ mdio1_phy2: emdio1_phy at 2 {
+ reg = <0x11>;
+ };
+ mdio1_phy3: emdio1_phy at 3 {
+ reg = <0x12>;
+ };
+ mdio1_phy4: emdio1_phy at 4 {
+ reg = <0x13>;
+ };
+};
+
+&emdio2 {
+ status = "okay";
+
+ /* AQR405 PHYs */
+ mdio2_phy1: emdio2_phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+ mdio2_phy2: emdio2_phy at 2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+ mdio2_phy3: emdio2_phy at 3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ };
+ mdio2_phy4: emdio2_phy at 4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ };
+};
+
&dspi {
bus-num = <0>;
status = "okay";
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 11/14] arm: dts: ls1088ardb: add DPMAC and PHY nodes
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (9 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 10/14] arm: dts: ls2088ardb: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 12/14] configs: ls1088ardb: enable CONFIG_DM_ETH and related Ioana Ciornei
` (3 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the external MDIO nodes and describe the PHYs (8 x
VSC8514, AQR105). Also, add phy-handles for the dpmacs to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
arch/arm/dts/fsl-ls1088a-rdb.dts | 102 +++++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 87 ++++++++++++++++++++++++--
2 files changed, 183 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 0fe351973dc5..46a5780547fe 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -17,6 +17,108 @@
};
};
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-handle = <&mdio2_phy1>;
+ phy-connection-type = "xgmii";
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&mdio1_phy5>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&mdio1_phy6>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&mdio1_phy7>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&mdio1_phy8>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-handle = <&mdio1_phy1>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-handle = <&mdio1_phy2>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac9 {
+ status = "okay";
+ phy-handle = <&mdio1_phy3>;
+ phy-connection-type = "qsgmii";
+};
+
+&dpmac10 {
+ status = "okay";
+ phy-handle = <&mdio1_phy4>;
+ phy-connection-type = "qsgmii";
+};
+
+&emdio1 {
+ status = "okay";
+
+ /* Freescale F104 PHY1 */
+ mdio1_phy1: emdio1_phy at 1 {
+ reg = <0x1c>;
+ };
+ mdio1_phy2: emdio1_phy at 2 {
+ reg = <0x1d>;
+ };
+ mdio1_phy3: emdio1_phy at 3 {
+ reg = <0x1e>;
+ };
+ mdio1_phy4: emdio1_phy at 4 {
+ reg = <0x1f>;
+ };
+
+ /* F104 PHY2 */
+ mdio1_phy5: emdio1_phy at 5 {
+ reg = <0x0c>;
+ };
+ mdio1_phy6: emdio1_phy at 6 {
+ reg = <0x0d>;
+ };
+ mdio1_phy7: emdio1_phy at 7 {
+ reg = <0x0e>;
+ };
+ mdio1_phy8: emdio1_phy at 8 {
+ reg = <0x0f>;
+ };
+};
+
+&emdio2 {
+ status = "okay";
+
+ /* Aquantia AQR105 10G PHY */
+ mdio2_phy1: emdio2_phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>;
+ reg = <0x0>;
+ };
+};
+
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 314961685070..133cacb93e39 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -82,12 +82,6 @@
interrupts = <0 32 0x1>; /* edge triggered */
};
- fsl_mc: fsl-mc at 80c000000 {
- compatible = "fsl,qoriq-mc";
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- };
-
dspi: dspi at 2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
@@ -197,6 +191,87 @@
method = "smc";
};
+ fsl_mc: fsl-mc at 80c000000 {
+ compatible = "fsl,qoriq-mc", "simple-mfd";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+ dpmacs {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpmac1: dpmac at 1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac at 2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ dpmac3: dpmac at 3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac at 4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ dpmac5: dpmac at 5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac at 6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac at 7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac at 8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
+ status = "disabled";
+ };
+
+ dpmac9: dpmac at 9 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x9>;
+ status = "disabled";
+ };
+
+ dpmac10: dpmac at a {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xa>;
+ status = "disabled";
+ };
+ };
+ };
+
emdio1: mdio at 8B96000 {
compatible = "fsl,ls-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 12/14] configs: ls1088ardb: enable CONFIG_DM_ETH and related
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (10 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 11/14] arm: dts: ls1088ardb: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 13/14] configs: ls2088ardb: " Ioana Ciornei
` (2 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS1088ARDB board.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 5 +++++
configs/ls1088ardb_qspi_defconfig | 5 +++++
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 5 +++++
configs/ls1088ardb_sdcard_qspi_defconfig | 5 +++++
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 5 +++++
configs/ls1088ardb_tfa_defconfig | 5 +++++
include/configs/ls1088ardb.h | 2 ++
7 files changed, 32 insertions(+)
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 3f654e2e1d0c..4d98b41ec11f 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -40,8 +41,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 935d76b4bed9..94593984d902 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -22,6 +22,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -43,8 +44,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 562cbdd3abd3..b2a61b76d96f 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -33,6 +33,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -52,8 +53,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 1e6fdceca1e0..728611f6dd52 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -53,8 +54,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 0086039e5241..53641703cb6f 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -47,8 +48,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index a7908e95b5c0..211ae7717104 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -25,6 +25,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -52,8 +53,12 @@ CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index b48efcc119f4..14648272016c 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -522,7 +522,9 @@
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
+#ifndef CONFIG_TARGET_LS1088ARDB
#define CONFIG_PHYLIB
+#endif
#define CONFIG_PHY_VITESSE
#define AQ_PHY_ADDR1 0x00
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 13/14] configs: ls2088ardb: enable CONFIG_DM_ETH and related
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (11 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 12/14] configs: ls1088ardb: enable CONFIG_DM_ETH and related Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 14/14] configs: lx2160ardb: " Ioana Ciornei
2020-03-27 11:14 ` [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS2088ARDB board.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 4 ++++
configs/ls2088ardb_qspi_defconfig | 4 ++++
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 4 ++++
configs/ls2088ardb_tfa_defconfig | 4 ++++
4 files changed, 16 insertions(+)
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index ae4a6820ff62..56e6c21163aa 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -39,8 +40,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 1ad5f3b367e6..5cba149821b0 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -45,8 +46,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index c0d0a99c8ad5..5a4edd88ae0d 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -22,6 +22,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -54,8 +55,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index ccbaaf7a5c6e..670bb5299af9 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -23,6 +23,7 @@ CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -62,8 +63,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 14/14] configs: lx2160ardb: enable CONFIG_DM_ETH and related
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (12 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 13/14] configs: ls2088ardb: " Ioana Ciornei
@ 2020-03-18 14:47 ` Ioana Ciornei
2020-03-27 11:14 ` [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-18 14:47 UTC (permalink / raw)
To: u-boot
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LX2160ARDB board.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 4 ++++
configs/lx2160ardb_tfa_defconfig | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index d1fffb399e99..2aee388e412f 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -48,7 +49,10 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 93f3e200c036..bcd1c594455b 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -52,7 +53,10 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
` (13 preceding siblings ...)
2020-03-18 14:47 ` [PATCH v2 14/14] configs: lx2160ardb: " Ioana Ciornei
@ 2020-03-27 11:14 ` Ioana Ciornei
14 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-03-27 11:14 UTC (permalink / raw)
To: u-boot
> Subject: [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH
>
> This patch set targets to add support for CONFIG_DM_ETH in DPAA2 based
> SoCs. We start by adding a DM MDIO driver for the MDIO interface found on the
> mEMAC. The next two patches start the transition of the ldpaa_eth and fsl-mc
> drivers towards using the 'struct udevice' and probing on DTS nodes.
>
> Any unnecessary configurations made for the DPAA2 ethernet devices are
> compiled out when CONFIG_DM_ETH. This is because any information
> necessary is available in its associated DTS node.
>
> For the moment, only configs of RDB boards are transitioned to
> CONFIG_DM_ETH since its more of a straightforward move than for the QDS
> ones.
>
Hi Priyanka,
Any feedback regarding this series that I can act on?
Ioana
> As an example, the 'dm tree' output for a LS2088ARDB board looks something
> like the following:
>
> => dm tree
> Class Index Probed Driver Name
> -----------------------------------------------------------
> (...)
> simple_bus 0 [ + ] generic_simple_bus |-- fsl-mc at 80c000000
> simple_bus 1 [ + ] generic_simple_bus | `-- dpmacs
> eth 0 [ + ] ldpaa_eth | |-- DPMAC1 at xfi
> eth 1 [ + ] ldpaa_eth | |-- DPMAC2 at xfi
> eth 2 [ + ] ldpaa_eth | |-- DPMAC3 at xfi
> eth 3 [ + ] ldpaa_eth | |-- DPMAC4 at xfi
> eth 4 [ + ] ldpaa_eth | |-- DPMAC5 at xfi
> eth 5 [ + ] ldpaa_eth | |-- DPMAC6 at xfi
> eth 6 [ + ] ldpaa_eth | |-- DPMAC7 at xfi
> eth 7 [ + ] ldpaa_eth | `-- DPMAC8 at xfi
> mdio 0 [ + ] fsl_ls_mdio |-- mdio at 8B96000
> mdio 1 [ + ] fsl_ls_mdio `-- mdio at 8B97000
>
> Changes in v2:
> - used the positive logic (ifdef CONFIG_DM_ETH instead of ifndef)
> - refactor the mdio read/write code for code reuse
>
> Ioana Ciornei (14):
> drivers: net: add Layerscape mEMAC MDIO driver
> drivers: net: ldpaa: add support for probing based on the DTS
> drivers: net: fsl-mc: add support for CONFIG_DM_ETH
> board: ls1088ardb: transition to DM_ETH
> board: ls2088ardb: transition to DM_ETH
> arm: dts: lx2160a: add external MDIO nodes
> arm: dts: ls2088a: add external MDIO nodes
> arm: dts: ls1088a: add external MDIO nodes
> arm: dts: lx2160ardb: add DPMAC and PHY nodes
> arm: dts: ls2088ardb: add DPMAC and PHY nodes
> arm: dts: ls1088ardb: add DPMAC and PHY nodes
> configs: ls1088ardb: enable CONFIG_DM_ETH and related
> configs: ls2088ardb: enable CONFIG_DM_ETH and related
> configs: lx2160ardb: enable CONFIG_DM_ETH and related
>
> arch/arm/dts/fsl-ls1088a-rdb.dts | 102 ++++++++
> arch/arm/dts/fsl-ls1088a.dtsi | 102 +++++++-
> arch/arm/dts/fsl-ls2080a.dtsi | 90 ++++++-
> arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++
> arch/arm/dts/fsl-lx2160a-rdb.dts | 52 ++++
> arch/arm/dts/fsl-lx2160a.dtsi | 65 +++++
> board/freescale/ls1088a/eth_ls1088ardb.c | 2 +
> board/freescale/ls1088a/ls1088a.c | 5 +
> board/freescale/ls2080ardb/eth_ls2080rdb.c | 7 +
> board/freescale/ls2080ardb/ls2080ardb.c | 4 +
> configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 5 +
> configs/ls1088ardb_qspi_defconfig | 5 +
> ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 5 +
> configs/ls1088ardb_sdcard_qspi_defconfig | 5 +
> configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 5 +
> configs/ls1088ardb_tfa_defconfig | 5 +
> configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 4 +
> configs/ls2088ardb_qspi_defconfig | 4 +
> configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 4 +
> configs/ls2088ardb_tfa_defconfig | 4 +
> configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 4 +
> configs/lx2160ardb_tfa_defconfig | 4 +
> drivers/net/Kconfig | 7 +
> drivers/net/Makefile | 1 +
> drivers/net/fsl-mc/mc.c | 48 +++-
> drivers/net/fsl_ls_mdio.c | 146 +++++++++++
> drivers/net/ldpaa_eth/ldpaa_eth.c | 231 +++++++++++++++---
> drivers/net/ldpaa_eth/ldpaa_eth.h | 6 +
> include/configs/ls1088ardb.h | 2 +
> 29 files changed, 956 insertions(+), 56 deletions(-) create mode 100644
> drivers/net/fsl_ls_mdio.c
>
> --
> 2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver
2020-03-18 14:47 ` [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver Ioana Ciornei
@ 2020-04-07 6:28 ` Priyanka Jain
0 siblings, 0 replies; 23+ messages in thread
From: Priyanka Jain @ 2020-04-07 6:28 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Ioana Ciornei
>Sent: Wednesday, March 18, 2020 8:18 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>boot at lists.denx.de
>Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>; Ioana
>Ciornei <ioana.ciornei@nxp.com>
>Subject: [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver
>
>Add a driver for the MDIO interface integrated in the mEMAC (Multi-rate
>Ethernet Media Access Controller) and the Fman 10G Ethernet MACs.
>
>Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>---
>Changes in v2:
> - refactor the mdio read/write code for code reuse
>
> drivers/net/Kconfig | 7 ++
> drivers/net/Makefile | 1 +
> drivers/net/fsl_ls_mdio.c | 146 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/net/fsl_ls_mdio.c
>
>diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index
>4d1013c98466..bc518f218da6 100644
>--- a/drivers/net/Kconfig
>+++ b/drivers/net/Kconfig
>@@ -640,4 +640,11 @@ config MVMDIO
>
> This driver is used by the MVPP2 and MVNETA drivers.
>
>+config FSL_LS_MDIO
>+ bool "NXP Layerscape MDIO interface support"
>+ depends on DM_MDIO
>+ help
>+ This driver supports the MDIO bus found on the Fman 10G Ethernet
>MACs and
>+ on the mEMAC (which supports both Clauses 22 and 45).
>+
> endif # NETDEVICES
>diff --git a/drivers/net/Makefile b/drivers/net/Makefile index
>6e0a68834d97..6d9b8772b1a5 100644
>--- a/drivers/net/Makefile
>+++ b/drivers/net/Makefile
>@@ -83,3 +83,4 @@ obj-y += mscc_eswitch/
> obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
> obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
> obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
>+obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
>diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c new file
>mode 100644 index 000000000000..6d8332d19ae0
>--- /dev/null
>+++ b/drivers/net/fsl_ls_mdio.c
>@@ -0,0 +1,146 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2020 NXP
>+ */
>+
>+#include <common.h>
>+#include <dm.h>
>+#include <errno.h>
>+#include <miiphy.h>
>+#include <asm/io.h>
>+#include <fsl_memac.h>
>+
>+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
>+#define memac_out_32(a, v) out_le32(a, v)
>+#define memac_clrbits_32(a, v) clrbits_le32(a, v)
>+#define memac_setbits_32(a, v) setbits_le32(a, v)
>+#else
>+#define memac_out_32(a, v) out_be32(a, v)
>+#define memac_clrbits_32(a, v) clrbits_be32(a, v)
>+#define memac_setbits_32(a, v) setbits_be32(a, v)
>+#endif
>+
>+static u32 memac_in_32(u32 *reg)
>+{
>+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
>+ return in_le32(reg);
>+#else
>+ return in_be32(reg);
>+#endif
>+}
>+
>+struct fsl_ls_mdio_priv {
>+ void *regs_base;
>+};
>+
>+static u32 fsl_ls_mdio_setup_operation(struct udevice *dev, int addr, int
>devad,
>+ int reg)
>+{
>+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
>+ struct memac_mdio_controller *regs;
>+ u32 mdio_ctl;
>+ u32 c45 = 1;
>+
>+ regs = (struct memac_mdio_controller *)(priv->regs_base);
>+ if (devad == MDIO_DEVAD_NONE) {
>+ c45 = 0; /* clause 22 */
>+ devad = reg & 0x1f;
>+ memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
>+ } else {
>+ memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
>+ }
>+
>+ /* Wait till the bus is free */
>+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
>+ ;
>+
>+ /* Set the Port and Device Addrs */
>+ mdio_ctl = MDIO_CTL_PORT_ADDR(addr) |
>MDIO_CTL_DEV_ADDR(devad);
>+ memac_out_32(®s->mdio_ctl, mdio_ctl);
>+
>+ /* Set the register address */
>+ if (c45)
>+ memac_out_32(®s->mdio_addr, reg & 0xffff);
>+
>+ /* Wait till the bus is free */
>+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
>+ ;
>+
>+ return mdio_ctl;
>+}
>+
>+static int dm_fsl_ls_mdio_read(struct udevice *dev, int addr,
>+ int devad, int reg)
>+{
>+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
>+ struct memac_mdio_controller *regs;
>+ u32 mdio_ctl;
>+
>+ regs = (struct memac_mdio_controller *)(priv->regs_base);
>+ mdio_ctl = fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
>+
>+ /* Initiate the read */
>+ mdio_ctl |= MDIO_CTL_READ;
>+ memac_out_32(®s->mdio_ctl, mdio_ctl);
>+
>+ /* Wait till the MDIO write is complete */
>+ while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
>+ ;
>+
>+ /* Return all Fs if nothing was there */
>+ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
>+ return 0xffff;
>+
>+ return memac_in_32(®s->mdio_data) & 0xffff; }
>+
>+static int dm_fsl_ls_mdio_write(struct udevice *dev, int addr, int devad,
>+ int reg, u16 val)
>+{
>+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
>+ struct memac_mdio_controller *regs;
>+
>+ regs = (struct memac_mdio_controller *)(priv->regs_base);
>+ fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
>+
>+ /* Write the value to the register */
>+ memac_out_32(®s->mdio_data, MDIO_DATA(val));
>+
>+ /* Wait till the MDIO write is complete */
>+ while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
>+ ;
>+
>+ return 0;
>+}
>+
>+static const struct mdio_ops fsl_ls_mdio_ops = {
>+ .read = dm_fsl_ls_mdio_read,
>+ .write = dm_fsl_ls_mdio_write,
>+};
>+
>+static int fsl_ls_mdio_probe(struct udevice *dev) {
>+ struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
>+ struct memac_mdio_controller *regs;
>+
>+ priv->regs_base = dev_read_addr_ptr(dev);
>+ regs = (struct memac_mdio_controller *)(priv->regs_base);
>+
>+ memac_setbits_32(®s->mdio_stat,
>+ MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
>+
>+ return 0;
>+}
>+
>+static const struct udevice_id fsl_ls_mdio_of_ids[] = {
>+ { .compatible = "fsl,ls-mdio" },
>+};
>+
>+U_BOOT_DRIVER(fsl_ls_mdio) = {
>+ .name = "fsl_ls_mdio",
>+ .id = UCLASS_MDIO,
>+ .of_match = fsl_ls_mdio_of_ids,
>+ .probe = fsl_ls_mdio_probe,
>+ .ops = &fsl_ls_mdio_ops,
>+ .priv_auto_alloc_size = sizeof(struct fsl_ls_mdio_priv), };
>--
>2.17.1
Joe,
Kindly help to review/ACK this patch
Thanks
Priyanka
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS
2020-03-18 14:47 ` [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS Ioana Ciornei
@ 2020-04-07 6:28 ` Priyanka Jain
0 siblings, 0 replies; 23+ messages in thread
From: Priyanka Jain @ 2020-04-07 6:28 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Ioana Ciornei
>Sent: Wednesday, March 18, 2020 8:18 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>boot at lists.denx.de
>Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>; Ioana
>Ciornei <ioana.ciornei@nxp.com>
>Subject: [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based
>on the DTS
>
>When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe
>based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible.
>In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver and
>reuse the _open()/_tx()/_stop() functions already inplemented.
>
>For the moment, the ldpaa_eth driver will support both configurations:
>with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence
>now has a matching 'struct udevice' made mutually exclusive based on the
>state of CONFIG_DM_ETH.
>
>Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
>Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>---
>Changes in v2:
> - used the positive logic (ifdef CONFIG_DM_ETH instead of ifndef)
>
> drivers/net/ldpaa_eth/ldpaa_eth.c | 231 +++++++++++++++++++++++++-----
> drivers/net/ldpaa_eth/ldpaa_eth.h | 6 +
> 2 files changed, 205 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
>b/drivers/net/ldpaa_eth/ldpaa_eth.c
>index a3b9c152b256..f589a482b734 100644
>--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
>+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
>@@ -12,6 +12,7 @@
> #include <net.h>
> #include <hwconfig.h>
> #include <phy.h>
>+#include <miiphy.h>
> #include <linux/compat.h>
> #include <fsl-mc/fsl_dpmac.h>
>
>@@ -19,6 +20,19 @@
> #include "ldpaa_eth.h"
>
> #ifdef CONFIG_PHYLIB
>+#ifdef CONFIG_DM_ETH
>+static void init_phy(struct udevice *dev) {
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
>+
>+ priv->phy = dm_eth_phy_connect(dev);
>+
>+ if (!priv->phy)
>+ return;
>+
>+ phy_config(priv->phy);
>+}
>+#else
> static int init_phy(struct eth_device *dev) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; @@ -
>63,6 +77,7 @@ static int init_phy(struct eth_device *dev)
> return ret;
> }
> #endif
>+#endif
>
> #ifdef DEBUG
>
>@@ -128,9 +143,15 @@ static void ldpaa_eth_get_dpni_counter(void)
> }
> }
>
>+#ifdef CONFIG_DM_ETH
>+static void ldpaa_eth_get_dpmac_counter(struct udevice *dev) {
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev); #else
> static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
>+#endif
> int err = 0;
> u64 value;
>
>@@ -263,9 +284,16 @@ error:
> return;
> }
>
>+#ifdef CONFIG_DM_ETH
>+static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev,
>+ int flags, uchar **packetp)
>+{
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev); #else
> static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
>+#endif
> const struct ldpaa_dq *dq;
> const struct dpaa_fd *fd;
> int i = 5, err = 0, status;
>@@ -322,9 +350,15 @@ static int ldpaa_eth_pull_dequeue_rx(struct
>eth_device *dev)
> return err;
> }
>
>+#ifdef CONFIG_DM_ETH
>+static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len) {
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev); #else
> static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
>+#endif
> struct dpaa_fd fd;
> u64 buffer_start;
> int data_offset, err;
>@@ -400,15 +434,32 @@ error:
> return err;
> }
>
>+static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv)
>+{ #ifdef CONFIG_DM_ETH
>+ return priv->phy;
>+#else
>+#ifdef CONFIG_PHYLIB
>+ struct phy_device *phydev = NULL;
>+ int phy_num;
>+
>+ /* start the phy devices one by one and update the dpmac state */
>+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
>+ phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
>+ if (phydev)
>+ return phydev;
>+ }
>+ return NULL;
>+#endif
>+#endif
>+}
>+
> static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
> struct dpmac_link_state *state)
> {
> phy_interface_t enet_if;
>- int phys_detected;
>-#ifdef CONFIG_PHYLIB
> struct phy_device *phydev = NULL;
>- int err, phy_num;
>-#endif
>+ int err;
>
> /* let's start off with maximum capabilities */
> enet_if = wriop_get_enet_if(priv->dpmac_id);
>@@ -420,39 +471,28 @@ static int ldpaa_get_dpmac_state(struct
>ldpaa_eth_priv *priv,
> state->rate = SPEED_1000;
> break;
> }
>- state->up = 1;
>
>- phys_detected = 0;
>-#ifdef CONFIG_PHYLIB
>+ state->up = 1;
> state->options |= DPMAC_LINK_OPT_AUTONEG;
>+ phydev = ldpaa_get_phydev(priv);
>
>- /* start the phy devices one by one and update the dpmac state */
>- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
>- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
>- if (!phydev)
>- continue;
>-
>- phys_detected++;
>+ if (phydev) {
> err = phy_startup(phydev);
> if (err) {
> printf("%s: Could not initialize\n", phydev->dev-
>>name);
> state->up = 0;
>- break;
>- }
>- if (phydev->link) {
>+ } else if (phydev->link) {
> state->rate = min(state->rate, (uint32_t)phydev-
>>speed);
> if (!phydev->duplex)
> state->options |=
>DPMAC_LINK_OPT_HALF_DUPLEX;
> if (!phydev->autoneg)
> state->options &=
>~DPMAC_LINK_OPT_AUTONEG;
> } else {
>- /* break out of loop even if one phy is down */
> state->up = 0;
>- break;
> }
> }
>-#endif
>- if (!phys_detected)
>+
>+ if (!phydev)
> state->options &= ~DPMAC_LINK_OPT_AUTONEG;
>
> if (!state->up) {
>@@ -464,9 +504,16 @@ static int ldpaa_get_dpmac_state(struct
>ldpaa_eth_priv *priv,
> return 0;
> }
>
>+#ifdef CONFIG_DM_ETH
>+static int ldpaa_eth_open(struct udevice *dev) {
>+ struct eth_pdata *plat = dev_get_platdata(dev);
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev); #else
> static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
>+#endif
> struct dpmac_link_state dpmac_link_state = { 0 };
> #ifdef DEBUG
> struct dpni_link_state link_state;
>@@ -474,8 +521,13 @@ static int ldpaa_eth_open(struct eth_device
>*net_dev, bd_t *bd)
> int err = 0;
> struct dpni_queue d_queue;
>
>+#ifdef CONFIG_DM_ETH
>+ if (eth_is_active(dev))
>+ return 0;
>+#else
> if (net_dev->state == ETH_STATE_ACTIVE)
> return 0;
>+#endif
>
> if (get_mc_boot_status() != 0) {
> printf("ERROR (MC is not booted)\n"); @@ -515,8 +567,13
>@@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
> if (err)
> goto err_dpni_bind;
>
>+#ifdef CONFIG_DM_ETH
>+ err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
>+ dflt_dpni->dpni_handle, plat->enetaddr);
>#else
> err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
> dflt_dpni->dpni_handle, net_dev->enetaddr);
>+#endif
> if (err) {
> printf("dpni_add_mac_addr() failed\n");
> return err;
>@@ -589,22 +646,34 @@ err_dpmac_setup:
> return err;
> }
>
>+#ifdef CONFIG_DM_ETH
>+static void ldpaa_eth_stop(struct udevice *dev) {
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev); #else
> static void ldpaa_eth_stop(struct eth_device *net_dev) {
> struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
>- int err = 0;
>-#ifdef CONFIG_PHYLIB
>- struct phy_device *phydev = NULL;
>- int phy_num;
> #endif
>+ struct phy_device *phydev = NULL;
>+ int err = 0;
>
>+#ifdef CONFIG_DM_ETH
>+ if (!eth_is_active(dev))
>+ return;
>+#else
> if ((net_dev->state == ETH_STATE_PASSIVE) ||
> (net_dev->state == ETH_STATE_INIT))
> return;
>+#endif
>
> #ifdef DEBUG
> ldpaa_eth_get_dpni_counter();
>+#ifdef CONFIG_DM_ETH
>+ ldpaa_eth_get_dpmac_counter(dev);
>+#else
> ldpaa_eth_get_dpmac_counter(net_dev);
>+#endif
> #endif
>
> err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, @@ -628,13
>+697,9 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
> if (err < 0)
> printf("dpni_disable() failed\n");
>
>-#ifdef CONFIG_PHYLIB
>- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
>- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
>- if (phydev)
>- phy_shutdown(phydev);
>- }
>-#endif
>+ phydev = ldpaa_get_phydev(priv);
>+ if (phydev)
>+ phy_shutdown(phydev);
>
> /* Free DPBP handle and reset. */
> ldpaa_dpbp_free();
>@@ -1027,6 +1092,107 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv
>*priv)
> return 0;
> }
>
>+#ifdef CONFIG_DM_ETH
>+static int ldpaa_eth_probe(struct udevice *dev) {
>+ struct ofnode_phandle_args phandle;
>+
>+ /* Nothing to do if there is no "phy-handle" in the DTS node */
>+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL,
>+ 0, 0, &phandle)) {
>+ return 0;
>+ }
>+
>+ init_phy(dev);
>+
>+ return 0;
>+}
>+
>+static uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev) {
>+ int port_node = dev_of_offset(dev);
>+
>+ return fdtdec_get_uint(gd->fdt_blob, port_node, "reg", -1); }
>+
>+static const char *ldpaa_eth_get_phy_mode_str(struct udevice *dev) {
>+ int port_node = dev_of_offset(dev);
>+ const char *phy_mode_str;
>+
>+ phy_mode_str = fdt_getprop(gd->fdt_blob, port_node,
>+ "phy-connection-type", NULL);
>+ if (phy_mode_str)
>+ return phy_mode_str;
>+
>+ phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode",
>NULL);
>+ return phy_mode_str;
>+}
>+
>+static int ldpaa_eth_bind(struct udevice *dev) {
>+ const char *phy_mode_str = NULL;
>+ uint32_t dpmac_id;
>+ char eth_name[16];
>+ int phy_mode = -1;
>+
>+ phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
>+ if (phy_mode_str)
>+ phy_mode = phy_get_interface_by_name(phy_mode_str);
>+ if (phy_mode == -1) {
>+ dev_err(dev, "incorrect phy mode\n");
>+ return -EINVAL;
>+ }
>+
>+ dpmac_id = ldpaa_eth_get_dpmac_id(dev);
>+ if (dpmac_id == -1) {
>+ dev_err(dev, "missing reg field from the dpmac node\n");
>+ return -EINVAL;
>+ }
>+
>+ sprintf(eth_name, "DPMAC%d@%s", dpmac_id, phy_mode_str);
>+ device_set_name(dev, eth_name);
>+
>+ return 0;
>+}
>+
>+static int ldpaa_eth_ofdata_to_platdata(struct udevice *dev) {
>+ struct ldpaa_eth_priv *priv = dev_get_priv(dev);
>+ const char *phy_mode_str;
>+
>+ priv->dpmac_id = ldpaa_eth_get_dpmac_id(dev);
>+ phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
>+ priv->phy_mode = phy_get_interface_by_name(phy_mode_str);
>+
>+ return 0;
>+}
>+
>+static const struct eth_ops ldpaa_eth_ops = {
>+ .start = ldpaa_eth_open,
>+ .send = ldpaa_eth_tx,
>+ .recv = ldpaa_eth_pull_dequeue_rx,
>+ .stop = ldpaa_eth_stop,
>+};
>+
>+static const struct udevice_id ldpaa_eth_of_ids[] = {
>+ { .compatible = "fsl,qoriq-mc-dpmac" }, };
>+
>+U_BOOT_DRIVER(ldpaa_eth) = {
>+ .name = "ldpaa_eth",
>+ .id = UCLASS_ETH,
>+ .of_match = ldpaa_eth_of_ids,
>+ .ofdata_to_platdata = ldpaa_eth_ofdata_to_platdata,
>+ .bind = ldpaa_eth_bind,
>+ .probe = ldpaa_eth_probe,
>+ .ops = &ldpaa_eth_ops,
>+ .priv_auto_alloc_size = sizeof(struct ldpaa_eth_priv),
>+ .platdata_auto_alloc_size = sizeof(struct eth_pdata), };
>+
>+#else
>+
> static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
> phy_interface_t enet_if)
> {
>@@ -1099,3 +1265,4 @@ err_netdev_init:
>
> return err;
> }
>+#endif
>diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h
>b/drivers/net/ldpaa_eth/ldpaa_eth.h
>index 3f9154b5bbcd..e90513e56f9a 100644
>--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
>+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
>@@ -116,7 +116,13 @@ struct ldpaa_fas {
> LDPAA_ETH_FAS_TIDE)
>
> struct ldpaa_eth_priv {
>+#ifdef CONFIG_DM_ETH
>+ struct phy_device *phy;
>+ int phy_mode;
>+ bool started;
>+#else
> struct eth_device *net_dev;
>+#endif
> uint32_t dpmac_id;
> uint16_t dpmac_handle;
>
>--
>2.17.1
Joe,
Kindly help to review/ACK this patch
Thanks
Priyanka
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
2020-03-18 14:47 ` [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH Ioana Ciornei
@ 2020-04-15 12:50 ` Priyanka Jain
2020-04-22 13:10 ` Ioana Ciornei
0 siblings, 1 reply; 23+ messages in thread
From: Priyanka Jain @ 2020-04-15 12:50 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Ioana Ciornei <ioana.ciornei@nxp.com>
>Sent: Wednesday, March 18, 2020 8:18 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>boot at lists.denx.de
>Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>; Ioana
>Ciornei <ioana.ciornei@nxp.com>
>Subject: [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
>
>In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
>DPAA2 Ethernet devices. Compile out any unnecessary setup when
>CONFIG_DM_ETH is activated.
>Also, force the PCI devices to be enumerated at probe time.
>
>Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>---
>Changes in v2:
> - none
>
> board/freescale/ls1088a/eth_ls1088ardb.c | 2 ++
> board/freescale/ls1088a/ls1088a.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
>diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c
>b/board/freescale/ls1088a/eth_ls1088ardb.c
>index 01f56db0a1bf..f56ce7d9ae8e 100644
>--- a/board/freescale/ls1088a/eth_ls1088ardb.c
>+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
>@@ -18,6 +18,7 @@
> #include <fsl-mc/fsl_mc.h>
> #include <fsl-mc/ldpaa_wriop.h>
>
>+#ifndef CONFIG_DM_ETH
> int board_eth_init(bd_t *bis)
> {
> #if defined(CONFIG_FSL_MC_ENET)
>@@ -95,6 +96,7 @@ int board_eth_init(bd_t *bis)
>
> return pci_eth_init(bis);
> }
>+#endif
>
> #if defined(CONFIG_RESET_PHY_R)
> void reset_phy(void)
>diff --git a/board/freescale/ls1088a/ls1088a.c
>b/board/freescale/ls1088a/ls1088a.c
>index 0bd397a0beb6..225e787c7577 100644
>--- a/board/freescale/ls1088a/ls1088a.c
>+++ b/board/freescale/ls1088a/ls1088a.c
>@@ -801,6 +801,11 @@ int board_init(void) #ifdef CONFIG_FSL_LS_PPA
> ppa_init();
> #endif
>+
>+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
>+ pci_init();
>+#endif
>+
Ioana,
Can you please confirm that you have tested e1000 cards to be working fine after this kind of changes.
Tested
Priyanka
> return 0;
> }
>
>--
>2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
2020-03-18 14:47 ` [PATCH v2 10/14] arm: dts: ls2088ardb: " Ioana Ciornei
@ 2020-04-15 13:02 ` Priyanka Jain
2020-04-22 13:13 ` Ioana Ciornei
0 siblings, 1 reply; 23+ messages in thread
From: Priyanka Jain @ 2020-04-15 13:02 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Ioana Ciornei <ioana.ciornei@nxp.com>
>Sent: Wednesday, March 18, 2020 8:18 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>boot at lists.denx.de
>Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>; Ioana
>Ciornei <ioana.ciornei@nxp.com>
>Subject: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
>
>In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is
>added but instead of being probed by a dedicated bus driver it will be a
>simple-mfd.
>
>Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405
>and 4 x CS4340). Also, add phy-handles for the dpmacs to their associated
>PHY.
>
>Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>---
>Changes in v2:
> - none
>
> arch/arm/dts/fsl-ls2080a.dtsi | 75 +++++++++++++++++++++--
> arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++++++++++++++++++++++
> 2 files changed, 157 insertions(+), 6 deletions(-)
>
>diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index
>7ff854caecd5..fb5777e268e4 100644
>--- a/arch/arm/dts/fsl-ls2080a.dtsi
>+++ b/arch/arm/dts/fsl-ls2080a.dtsi
>@@ -50,12 +50,6 @@
> interrupts = <0 32 0x1>; /* edge triggered */
> };
>
>- fsl_mc: fsl-mc at 80c000000 {
>- compatible = "fsl,qoriq-mc";
>- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal
>base */
>- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
>- };
>-
> i2c0: i2c at 2000000 {
> status = "disabled";
> compatible = "fsl,vf610-i2c";
>@@ -200,6 +194,75 @@
> status = "disabled";
> };
>
>+ fsl_mc: fsl-mc at 80c000000 {
>+ compatible = "fsl,qoriq-mc", "simple-mfd";
>+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base
>*/
>+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
>+ #address-cells = <3>;
>+ #size-cells = <1>;
>+
>+ /*
>+ * Region type 0x0 - MC portals
>+ * Region type 0x1 - QBMAN portals
>+ */
>+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
>+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
>+
>+ dpmacs {
>+ compatible = "simple-mfd";
>+ #address-cells = <1>;
>+ #size-cells = <0>;
>+
>+ dpmac1: dpmac at 1 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x1>;
>+ status = "disabled";
>+ };
>+
>+ dpmac2: dpmac at 2 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x2>;
>+ status = "disabled";
>+ };
>+
>+ dpmac3: dpmac at 3 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x3>;
>+ status = "disabled";
>+ };
>+
>+ dpmac4: dpmac at 4 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x4>;
>+ status = "disabled";
>+ };
>+
>+ dpmac5: dpmac at 5 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x5>;
>+ status = "disabled";
>+ };
>+
>+ dpmac6: dpmac at 6 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x6>;
>+ status = "disabled";
>+ };
>+
>+ dpmac7: dpmac at 7 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x7>;
>+ status = "disabled";
>+ };
>+
>+ dpmac8: dpmac at 8 {
>+ compatible = "fsl,qoriq-mc-dpmac";
>+ reg = <0x8>;
>+ status = "disabled";
>+ };
>+ };
>+ };
>+
> emdio1: mdio at 8B96000 {
> compatible = "fsl,ls-mdio";
> reg = <0x0 0x8B96000 0x0 0x1000>;
>diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-
>rdb-qspi.dts
>index 72b2177b70d9..16b9aeec966c 100644
>--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
>+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
>@@ -21,6 +21,94 @@
> };
> };
>
>+&dpmac1 {
>+ status = "okay";
>+ phy-handle = <&mdio1_phy1>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac2 {
>+ status = "okay";
>+ phy-handle = <&mdio1_phy2>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac3 {
>+ status = "okay";
>+ phy-handle = <&mdio1_phy3>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac4 {
>+ status = "okay";
>+ phy-handle = <&mdio1_phy4>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac5 {
>+ status = "okay";
>+ phy-handle = <&mdio2_phy1>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac6 {
>+ status = "okay";
>+ phy-handle = <&mdio2_phy2>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac7 {
>+ status = "okay";
>+ phy-handle = <&mdio2_phy3>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&dpmac8 {
>+ status = "okay";
>+ phy-handle = <&mdio2_phy4>;
>+ phy-connection-type = "xfi";
>+};
>+
>+&emdio1 {
>+ status = "okay";
>+
>+ /* CS4340 PHYs */
>+ mdio1_phy1: emdio1_phy at 1 {
>+ reg = <0x10>;
>+ };
>+ mdio1_phy2: emdio1_phy at 2 {
>+ reg = <0x11>;
>+ };
>+ mdio1_phy3: emdio1_phy at 3 {
>+ reg = <0x12>;
>+ };
>+ mdio1_phy4: emdio1_phy at 4 {
>+ reg = <0x13>;
>+ };
>+};
>+
>+&emdio2 {
>+ status = "okay";
>+
>+ /* AQR405 PHYs */
>+ mdio2_phy1: emdio2_phy at 1 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x0>;
>+ };
>+ mdio2_phy2: emdio2_phy at 2 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x1>;
>+ };
>+ mdio2_phy3: emdio2_phy at 3 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x2>;
>+ };
>+ mdio2_phy4: emdio2_phy at 4 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x3>;
>+ };
>+};
>+
> &dspi {
> bus-num = <0>;
> status = "okay";
>--
>2.17.1
Similar changes will be required in ls2080a board files as well which also include fsl-ls2080a.dtsi like fsl-ls2080a-rdb.dts, fsl-ls2080a-qds.dts
Regards
Priyanka
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
2020-04-15 12:50 ` Priyanka Jain
@ 2020-04-22 13:10 ` Ioana Ciornei
0 siblings, 0 replies; 23+ messages in thread
From: Ioana Ciornei @ 2020-04-22 13:10 UTC (permalink / raw)
To: u-boot
> Subject: RE: [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
>
> >-----Original Message-----
> >From: Ioana Ciornei <ioana.ciornei@nxp.com>
> >Sent: Wednesday, March 18, 2020 8:18 PM
> >To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
> >boot at lists.denx.de
> >Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>;
> >Ioana Ciornei <ioana.ciornei@nxp.com>
> >Subject: [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH
> >
> >In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
> >DPAA2 Ethernet devices. Compile out any unnecessary setup when
> >CONFIG_DM_ETH is activated.
> >Also, force the PCI devices to be enumerated at probe time.
> >
> >Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> >---
> >Changes in v2:
> > - none
> >
> > board/freescale/ls1088a/eth_ls1088ardb.c | 2 ++
> > board/freescale/ls1088a/ls1088a.c | 5 +++++
> > 2 files changed, 7 insertions(+)
> >
> >diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c
> >b/board/freescale/ls1088a/eth_ls1088ardb.c
> >index 01f56db0a1bf..f56ce7d9ae8e 100644
> >--- a/board/freescale/ls1088a/eth_ls1088ardb.c
> >+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
> >@@ -18,6 +18,7 @@
> > #include <fsl-mc/fsl_mc.h>
> > #include <fsl-mc/ldpaa_wriop.h>
> >
> >+#ifndef CONFIG_DM_ETH
> > int board_eth_init(bd_t *bis)
> > {
> > #if defined(CONFIG_FSL_MC_ENET)
> >@@ -95,6 +96,7 @@ int board_eth_init(bd_t *bis)
> >
> > return pci_eth_init(bis);
> > }
> >+#endif
> >
> > #if defined(CONFIG_RESET_PHY_R)
> > void reset_phy(void)
> >diff --git a/board/freescale/ls1088a/ls1088a.c
> >b/board/freescale/ls1088a/ls1088a.c
> >index 0bd397a0beb6..225e787c7577 100644
> >--- a/board/freescale/ls1088a/ls1088a.c
> >+++ b/board/freescale/ls1088a/ls1088a.c
> >@@ -801,6 +801,11 @@ int board_init(void) #ifdef CONFIG_FSL_LS_PPA
> > ppa_init();
> > #endif
> >+
> >+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
> >+ pci_init();
> >+#endif
> >+
> Ioana,
> Can you please confirm that you have tested e1000 cards to be working fine
> after this kind of changes.
>
Hi Priyanka,
Yes, I tested e1000 cards and all platforms are working fine.
Regards,
Ioana
> Tested
> Priyanka
> > return 0;
> > }
> >
> >--
> >2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
2020-04-15 13:02 ` Priyanka Jain
@ 2020-04-22 13:13 ` Ioana Ciornei
2020-04-24 8:48 ` Priyanka Jain
0 siblings, 1 reply; 23+ messages in thread
From: Ioana Ciornei @ 2020-04-22 13:13 UTC (permalink / raw)
To: u-boot
> Subject: RE: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
>
> >-----Original Message-----
> >From: Ioana Ciornei <ioana.ciornei@nxp.com>
> >Sent: Wednesday, March 18, 2020 8:18 PM
> >To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
> >boot at lists.denx.de
> >Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>;
> >Ioana Ciornei <ioana.ciornei@nxp.com>
> >Subject: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
> >
> >In order to maintain compatibility with the Linux DTS, the entire
> >fsl-mc node is added but instead of being probed by a dedicated bus
> >driver it will be a simple-mfd.
> >
> >Also, annotate the external MDIO nodes and describe the PHYs (4 x
> >AQR405 and 4 x CS4340). Also, add phy-handles for the dpmacs to their
> >associated PHY.
> >
> >Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> >---
> >Changes in v2:
> > - none
> >
> > arch/arm/dts/fsl-ls2080a.dtsi | 75 +++++++++++++++++++++--
> > arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++++++++++++++++++++++
> > 2 files changed, 157 insertions(+), 6 deletions(-)
> >
> >diff --git a/arch/arm/dts/fsl-ls2080a.dtsi
> >b/arch/arm/dts/fsl-ls2080a.dtsi index
> >7ff854caecd5..fb5777e268e4 100644
> >--- a/arch/arm/dts/fsl-ls2080a.dtsi
> >+++ b/arch/arm/dts/fsl-ls2080a.dtsi
> >@@ -50,12 +50,6 @@
> > interrupts = <0 32 0x1>; /* edge triggered */
> > };
> >
> >- fsl_mc: fsl-mc at 80c000000 {
> >- compatible = "fsl,qoriq-mc";
> >- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal
> >base */
> >- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
> >- };
> >-
> > i2c0: i2c at 2000000 {
> > status = "disabled";
> > compatible = "fsl,vf610-i2c";
> >@@ -200,6 +194,75 @@
> > status = "disabled";
> > };
> >
> >+ fsl_mc: fsl-mc at 80c000000 {
> >+ compatible = "fsl,qoriq-mc", "simple-mfd";
> >+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base
> >*/
> >+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
> >+ #address-cells = <3>;
> >+ #size-cells = <1>;
> >+
> >+ /*
> >+ * Region type 0x0 - MC portals
> >+ * Region type 0x1 - QBMAN portals
> >+ */
> >+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
> >+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
> >+
> >+ dpmacs {
> >+ compatible = "simple-mfd";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+
> >+ dpmac1: dpmac at 1 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x1>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac2: dpmac at 2 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x2>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac3: dpmac at 3 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x3>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac4: dpmac at 4 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac5: dpmac at 5 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x5>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac6: dpmac at 6 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x6>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac7: dpmac at 7 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x7>;
> >+ status = "disabled";
> >+ };
> >+
> >+ dpmac8: dpmac at 8 {
> >+ compatible = "fsl,qoriq-mc-dpmac";
> >+ reg = <0x8>;
> >+ status = "disabled";
> >+ };
> >+ };
> >+ };
> >+
> > emdio1: mdio at 8B96000 {
> > compatible = "fsl,ls-mdio";
> > reg = <0x0 0x8B96000 0x0 0x1000>;
> >diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> >b/arch/arm/dts/fsl-ls2088a- rdb-qspi.dts index
> >72b2177b70d9..16b9aeec966c 100644
> >--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> >+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> >@@ -21,6 +21,94 @@
> > };
> > };
> >
> >+&dpmac1 {
> >+ status = "okay";
> >+ phy-handle = <&mdio1_phy1>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac2 {
> >+ status = "okay";
> >+ phy-handle = <&mdio1_phy2>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac3 {
> >+ status = "okay";
> >+ phy-handle = <&mdio1_phy3>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac4 {
> >+ status = "okay";
> >+ phy-handle = <&mdio1_phy4>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac5 {
> >+ status = "okay";
> >+ phy-handle = <&mdio2_phy1>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac6 {
> >+ status = "okay";
> >+ phy-handle = <&mdio2_phy2>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac7 {
> >+ status = "okay";
> >+ phy-handle = <&mdio2_phy3>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&dpmac8 {
> >+ status = "okay";
> >+ phy-handle = <&mdio2_phy4>;
> >+ phy-connection-type = "xfi";
> >+};
> >+
> >+&emdio1 {
> >+ status = "okay";
> >+
> >+ /* CS4340 PHYs */
> >+ mdio1_phy1: emdio1_phy at 1 {
> >+ reg = <0x10>;
> >+ };
> >+ mdio1_phy2: emdio1_phy at 2 {
> >+ reg = <0x11>;
> >+ };
> >+ mdio1_phy3: emdio1_phy at 3 {
> >+ reg = <0x12>;
> >+ };
> >+ mdio1_phy4: emdio1_phy at 4 {
> >+ reg = <0x13>;
> >+ };
> >+};
> >+
> >+&emdio2 {
> >+ status = "okay";
> >+
> >+ /* AQR405 PHYs */
> >+ mdio2_phy1: emdio2_phy at 1 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+ mdio2_phy2: emdio2_phy at 2 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x1>;
> >+ };
> >+ mdio2_phy3: emdio2_phy at 3 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x2>;
> >+ };
> >+ mdio2_phy4: emdio2_phy at 4 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x3>;
> >+ };
> >+};
> >+
> > &dspi {
> > bus-num = <0>;
> > status = "okay";
> >--
> >2.17.1
> Similar changes will be required in ls2080a board files as well which also include
> fsl-ls2080a.dtsi like fsl-ls2080a-rdb.dts, fsl-ls2080a-qds.dts
The QDS boards are handled in another patch set.
For the LS2080ARDB (fsl-ls2080a-rdb.dts) do you want to submit a separate patch?
Ioana
>
> Regards
> Priyanka
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes
2020-04-22 13:13 ` Ioana Ciornei
@ 2020-04-24 8:48 ` Priyanka Jain
0 siblings, 0 replies; 23+ messages in thread
From: Priyanka Jain @ 2020-04-24 8:48 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Ioana Ciornei
>Sent: Wednesday, April 22, 2020 6:43 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>boot at lists.denx.de
>Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
>Subject: RE: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY
>nodes
>
>> Subject: RE: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY
>> nodes
>>
>> >-----Original Message-----
>> >From: Ioana Ciornei <ioana.ciornei@nxp.com>
>> >Sent: Wednesday, March 18, 2020 8:18 PM
>> >To: Priyanka Jain <priyanka.jain@nxp.com>; joe.hershberger at ni.com; u-
>> >boot at lists.denx.de
>> >Cc: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>;
>> >Ioana Ciornei <ioana.ciornei@nxp.com>
>> >Subject: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY
>> >nodes
>> >
>> >In order to maintain compatibility with the Linux DTS, the entire
>> >fsl-mc node is added but instead of being probed by a dedicated bus
>> >driver it will be a simple-mfd.
>> >
>> >Also, annotate the external MDIO nodes and describe the PHYs (4 x
>> >AQR405 and 4 x CS4340). Also, add phy-handles for the dpmacs to their
>> >associated PHY.
>> >
>> >Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>> >---
>> >Changes in v2:
>> > - none
>> >
>> > arch/arm/dts/fsl-ls2080a.dtsi | 75 +++++++++++++++++++++--
>> > arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88
>> > +++++++++++++++++++++++++++
>> > 2 files changed, 157 insertions(+), 6 deletions(-)
>> >
>> >diff --git a/arch/arm/dts/fsl-ls2080a.dtsi
>> >b/arch/arm/dts/fsl-ls2080a.dtsi index
>> >7ff854caecd5..fb5777e268e4 100644
>> >--- a/arch/arm/dts/fsl-ls2080a.dtsi
>> >+++ b/arch/arm/dts/fsl-ls2080a.dtsi
>> >@@ -50,12 +50,6 @@
>> > interrupts = <0 32 0x1>; /* edge triggered */
>> > };
>> >
>> >- fsl_mc: fsl-mc at 80c000000 {
>> >- compatible = "fsl,qoriq-mc";
>> >- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal
>> >base */
>> >- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
>> >- };
>> >-
>> > i2c0: i2c at 2000000 {
>> > status = "disabled";
>> > compatible = "fsl,vf610-i2c";
>> >@@ -200,6 +194,75 @@
>> > status = "disabled";
>> > };
>> >
>> >+ fsl_mc: fsl-mc at 80c000000 {
>> >+ compatible = "fsl,qoriq-mc", "simple-mfd";
>> >+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base
>> >*/
>> >+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
>> >+ #address-cells = <3>;
>> >+ #size-cells = <1>;
>> >+
>> >+ /*
>> >+ * Region type 0x0 - MC portals
>> >+ * Region type 0x1 - QBMAN portals
>> >+ */
>> >+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
>> >+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
>> >+
>> >+ dpmacs {
>> >+ compatible = "simple-mfd";
>> >+ #address-cells = <1>;
>> >+ #size-cells = <0>;
>> >+
>> >+ dpmac1: dpmac at 1 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x1>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac2: dpmac at 2 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x2>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac3: dpmac at 3 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x3>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac4: dpmac at 4 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x4>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac5: dpmac at 5 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x5>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac6: dpmac at 6 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x6>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac7: dpmac at 7 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x7>;
>> >+ status = "disabled";
>> >+ };
>> >+
>> >+ dpmac8: dpmac at 8 {
>> >+ compatible = "fsl,qoriq-mc-dpmac";
>> >+ reg = <0x8>;
>> >+ status = "disabled";
>> >+ };
>> >+ };
>> >+ };
>> >+
>> > emdio1: mdio at 8B96000 {
>> > compatible = "fsl,ls-mdio";
>> > reg = <0x0 0x8B96000 0x0 0x1000>;
>> >diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
>> >b/arch/arm/dts/fsl-ls2088a- rdb-qspi.dts index
>> >72b2177b70d9..16b9aeec966c 100644
>> >--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
>> >+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
>> >@@ -21,6 +21,94 @@
>> > };
>> > };
>> >
>> >+&dpmac1 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio1_phy1>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac2 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio1_phy2>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac3 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio1_phy3>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac4 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio1_phy4>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac5 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio2_phy1>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac6 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio2_phy2>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac7 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio2_phy3>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&dpmac8 {
>> >+ status = "okay";
>> >+ phy-handle = <&mdio2_phy4>;
>> >+ phy-connection-type = "xfi";
>> >+};
>> >+
>> >+&emdio1 {
>> >+ status = "okay";
>> >+
>> >+ /* CS4340 PHYs */
>> >+ mdio1_phy1: emdio1_phy at 1 {
>> >+ reg = <0x10>;
>> >+ };
>> >+ mdio1_phy2: emdio1_phy at 2 {
>> >+ reg = <0x11>;
>> >+ };
>> >+ mdio1_phy3: emdio1_phy at 3 {
>> >+ reg = <0x12>;
>> >+ };
>> >+ mdio1_phy4: emdio1_phy at 4 {
>> >+ reg = <0x13>;
>> >+ };
>> >+};
>> >+
>> >+&emdio2 {
>> >+ status = "okay";
>> >+
>> >+ /* AQR405 PHYs */
>> >+ mdio2_phy1: emdio2_phy at 1 {
>> >+ compatible = "ethernet-phy-ieee802.3-c45";
>> >+ reg = <0x0>;
>> >+ };
>> >+ mdio2_phy2: emdio2_phy at 2 {
>> >+ compatible = "ethernet-phy-ieee802.3-c45";
>> >+ reg = <0x1>;
>> >+ };
>> >+ mdio2_phy3: emdio2_phy at 3 {
>> >+ compatible = "ethernet-phy-ieee802.3-c45";
>> >+ reg = <0x2>;
>> >+ };
>> >+ mdio2_phy4: emdio2_phy at 4 {
>> >+ compatible = "ethernet-phy-ieee802.3-c45";
>> >+ reg = <0x3>;
>> >+ };
>> >+};
>> >+
>> > &dspi {
>> > bus-num = <0>;
>> > status = "okay";
>> >--
>> >2.17.1
>> Similar changes will be required in ls2080a board files as well which
>> also include fsl-ls2080a.dtsi like fsl-ls2080a-rdb.dts,
>> fsl-ls2080a-qds.dts
>
>The QDS boards are handled in another patch set.
>
>For the LS2080ARDB (fsl-ls2080a-rdb.dts) do you want to submit a separate
>patch?
>
Yes, for LS2080ARDB also, we will need similar changes.
You can send this later on in separate patch
>Ioana
>
Regards
Priyanka
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2020-04-24 8:48 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-18 14:47 [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 01/14] drivers: net: add Layerscape mEMAC MDIO driver Ioana Ciornei
2020-04-07 6:28 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 02/14] drivers: net: ldpaa: add support for probing based on the DTS Ioana Ciornei
2020-04-07 6:28 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 03/14] drivers: net: fsl-mc: add support for CONFIG_DM_ETH Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 04/14] board: ls1088ardb: transition to DM_ETH Ioana Ciornei
2020-04-15 12:50 ` Priyanka Jain
2020-04-22 13:10 ` Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 05/14] board: ls2088ardb: " Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 06/14] arm: dts: lx2160a: add external MDIO nodes Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 07/14] arm: dts: ls2088a: " Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 08/14] arm: dts: ls1088a: " Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 09/14] arm: dts: lx2160ardb: add DPMAC and PHY nodes Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 10/14] arm: dts: ls2088ardb: " Ioana Ciornei
2020-04-15 13:02 ` Priyanka Jain
2020-04-22 13:13 ` Ioana Ciornei
2020-04-24 8:48 ` Priyanka Jain
2020-03-18 14:47 ` [PATCH v2 11/14] arm: dts: ls1088ardb: " Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 12/14] configs: ls1088ardb: enable CONFIG_DM_ETH and related Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 13/14] configs: ls2088ardb: " Ioana Ciornei
2020-03-18 14:47 ` [PATCH v2 14/14] configs: lx2160ardb: " Ioana Ciornei
2020-03-27 11:14 ` [PATCH v2 00/14] net: ldpaa_eth: transition to CONFIG_DM_ETH Ioana Ciornei
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