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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [Why] Replace the way reads and writes are done to the IH ring registers at the vega10_ih. This is due to different IH ring registers offset between Vega10 and Arcturus. [How] mmIH_RING_REG macro is used to calculate the register address first. Then RREG32 and WREG32 macros are used to directly write/read into the register. Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 121 +++++++++++++------------ 1 file changed, 61 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 5bd9bc37fadf..8d41b4c27205 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -51,7 +51,7 @@ static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); */ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); + u32 ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL, RING0)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); @@ -61,12 +61,12 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl); } adev->irq.ih.enabled = true; if (adev->irq.ih1.ring_size) { - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, RB_ENABLE, 1); if (amdgpu_sriov_vf(adev)) { @@ -76,13 +76,13 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1), ih_rb_cntl); } adev->irq.ih1.enabled = true; } if (adev->irq.ih2.ring_size) { - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, RB_ENABLE, 1); if (amdgpu_sriov_vf(adev)) { @@ -92,7 +92,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2), ih_rb_cntl); } adev->irq.ih2.enabled = true; } @@ -107,7 +107,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) */ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); + u32 ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL, RING0)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); @@ -117,17 +117,17 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl); } /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); + WREG32(mmIH_RING_REG(RB_RPTR, RING0), 0); + WREG32(mmIH_RING_REG(RB_WPTR, RING0), 0); adev->irq.ih.enabled = false; adev->irq.ih.rptr = 0; if (adev->irq.ih1.ring_size) { - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, RB_ENABLE, 0); if (amdgpu_sriov_vf(adev)) { @@ -137,17 +137,17 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1), ih_rb_cntl); } /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); + WREG32(mmIH_RING_REG(RB_RPTR_RING1, RING1), 0); + WREG32(mmIH_RING_REG(RB_WPTR_RING1, RING1), 0); adev->irq.ih1.enabled = false; adev->irq.ih1.rptr = 0; } if (adev->irq.ih2.ring_size) { - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2)); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, RB_ENABLE, 0); if (amdgpu_sriov_vf(adev)) { @@ -157,12 +157,12 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) return; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2), ih_rb_cntl); } /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); + WREG32(mmIH_RING_REG(RB_RPTR_RING2, RING2), 0); + WREG32(mmIH_RING_REG(RB_WPTR_RING2, RING2), 0); adev->irq.ih2.enabled = false; adev->irq.ih2.rptr = 0; } @@ -235,10 +235,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ih = &adev->irq.ih; /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); + WREG32(mmIH_RING_REG(RB_BASE, RING0), ih->gpu_addr >> 8); + WREG32(mmIH_RING_REG(RB_BASE_HI, RING0), (ih->gpu_addr >> 40) & 0xff); - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL, RING0)); ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); @@ -248,7 +248,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) return -ETIMEDOUT; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl); } if ((adev->asic_type == CHIP_ARCTURUS && @@ -266,25 +266,25 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) } /* set the writeback address whether it's enabled or not */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, - lower_32_bits(ih->wptr_addr)); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, - upper_32_bits(ih->wptr_addr) & 0xFFFF); + WREG32(mmIH_RING_REG(RB_WPTR_ADDR_LO, RING0), + lower_32_bits(ih->wptr_addr)); + WREG32(mmIH_RING_REG(RB_WPTR_ADDR_HI, RING0), + upper_32_bits(ih->wptr_addr) & 0xFFFF); /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); + WREG32(mmIH_RING_REG(RB_RPTR, RING0), 0); + WREG32(mmIH_RING_REG(RB_WPTR, RING0), 0); - WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, - vega10_ih_doorbell_rptr(ih)); + WREG32(mmIH_RING_REG(DOORBELL_RPTR, RING0), + vega10_ih_doorbell_rptr(ih)); ih = &adev->irq.ih1; if (ih->ring_size) { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, - (ih->gpu_addr >> 40) & 0xff); + WREG32(mmIH_RING_REG(RB_BASE_RING1, RING1), ih->gpu_addr >> 8); + WREG32(mmIH_RING_REG(RB_BASE_HI_RING1, RING1), + (ih->gpu_addr >> 40) & 0xff); - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1)); ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); @@ -297,24 +297,24 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) return -ETIMEDOUT; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1), ih_rb_cntl); } /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); + WREG32(mmIH_RING_REG(RB_RPTR_RING1, RING1), 0); + WREG32(mmIH_RING_REG(RB_WPTR_RING1, RING1), 0); - WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, - vega10_ih_doorbell_rptr(ih)); + WREG32(mmIH_RING_REG(DOORBELL_RPTR_RING1, RING1), + vega10_ih_doorbell_rptr(ih)); } ih = &adev->irq.ih2; if (ih->ring_size) { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, - (ih->gpu_addr >> 40) & 0xff); + WREG32(mmIH_RING_REG(RB_BASE_RING2, RING2), ih->gpu_addr >> 8); + WREG32(mmIH_RING_REG(RB_BASE_HI_RING2, RING2), + (ih->gpu_addr >> 40) & 0xff); - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); + ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2)); ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); if (amdgpu_sriov_vf(adev)) { @@ -324,15 +324,16 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) return -ETIMEDOUT; } } else { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); + WREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2), ih_rb_cntl); } /* set rptr, wptr to 0 */ - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); + WREG32(mmIH_RING_REG(RB_RPTR_RING2, RING2), 0); + WREG32(mmIH_RING_REG(RB_WPTR_RING2, RING2), 0); + + WREG32(mmIH_RING_REG(DOORBELL_RPTR_RING2, RING2), + vega10_ih_doorbell_rptr(ih)); - WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, - vega10_ih_doorbell_rptr(ih)); } tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); @@ -390,11 +391,11 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, /* Double check that the overflow wasn't already cleared. */ if (ih == &adev->irq.ih) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); + reg = mmIH_RING_REG(RB_WPTR, RING0); else if (ih == &adev->irq.ih1) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); + reg = mmIH_RING_REG(RB_WPTR_RING1, RING1); else if (ih == &adev->irq.ih2) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); + reg = mmIH_RING_REG(RB_WPTR_RING2, RING2); else BUG(); @@ -415,11 +416,11 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, ih->rptr = tmp; if (ih == &adev->irq.ih) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); + reg = mmIH_RING_REG(RB_CNTL, RING0); else if (ih == &adev->irq.ih1) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); + reg = mmIH_RING_REG(RB_CNTL_RING1, RING1); else if (ih == &adev->irq.ih2) - reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); + reg = mmIH_RING_REG(RB_CNTL_RING2, RING2); else BUG(); @@ -488,11 +489,11 @@ static void vega10_ih_irq_rearm(struct amdgpu_device *adev, uint32_t i = 0; if (ih == &adev->irq.ih) - reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); + reg_rptr = mmIH_RING_REG(RB_RPTR, RING0); else if (ih == &adev->irq.ih1) - reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); + reg_rptr = mmIH_RING_REG(RB_RPTR_RING1, RING1); else if (ih == &adev->irq.ih2) - reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); + reg_rptr = mmIH_RING_REG(RB_RPTR_RING2, RING2); else return; @@ -524,11 +525,11 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) vega10_ih_irq_rearm(adev, ih); } else if (ih == &adev->irq.ih) { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); + WREG32(mmIH_RING_REG(RB_RPTR, RING0), ih->rptr); } else if (ih == &adev->irq.ih1) { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); + WREG32(mmIH_RING_REG(RB_RPTR_RING1, RING1), ih->rptr); } else if (ih == &adev->irq.ih2) { - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); + WREG32(mmIH_RING_REG(RB_RPTR_RING2, RING2), ih->rptr); } } -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx