From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6430CC4332B for ; Tue, 24 Mar 2020 10:20:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 358C5208C3 for ; Tue, 24 Mar 2020 10:20:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="BDdKQ/eg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727421AbgCXKUt (ORCPT ); Tue, 24 Mar 2020 06:20:49 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:55022 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727347AbgCXKUq (ORCPT ); Tue, 24 Mar 2020 06:20:46 -0400 Received: by mail-wm1-f65.google.com with SMTP id c81so2537781wmd.4 for ; Tue, 24 Mar 2020 03:20:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hou80d0MTLDZlmlJ355AXofbOfe1zM2AnQR9J4KSFMs=; b=BDdKQ/eg8GJU3rw7bt27fdm7JD3LunTPYvS5foLjXlk4+2x7IYUyC7tnZt6YzZhH2r 9uf+TxyolQ+b4d2ef/p/TCQzFfXAof7MK/MNyf1ecfF35Wzp0YGJXE20TnTghPKI4Tgc GamPL4GSpVlSgFzZqzk4KgESYQRvNR3ipm7ci5zm8oT1ImNDZz0c2/Kji2v93/U3iiKI QhgMoCZmRNAper4dB07FIQHCj5k4nF+chUBp4THzOSSXtHZ17q6+H5lbj7QcN1jzt4gT BLzaXw2yw0qAmTxEhoraNq4/z9QdkzP9g6PSxxlcyWn4YYNfdydP6KGuC+232xsszbq7 VIhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hou80d0MTLDZlmlJ355AXofbOfe1zM2AnQR9J4KSFMs=; b=BqCuT2/jBPKbYdeybGBL/g5aEAhl4Bx2ATgvRDSiuhmTeuGIE+7kOL5PXz6IOSNfwt 9EmlPicelxldBioK37A0CLBINP+cXIOzBkh229u5B74v42sWuo140s8yKD7LWzy4guTv pNdy5S9uu0d6mzHNoWBDiB8wA4X7MtmYgtoVbHwSlj7pYb0Ftb0jHZTZkOuSKQ+LA8Xa ewAMMl0B10P8YhuSP/qPWNqPKOEW9CR7m6jfO/qeILKi202Ugk2GS665Y5USdNk1ulR+ CtREdcKP43lWnjxn+Afuc70pz500pjI6ss7am6JMp0p0aEZfMUc35bB2piUze6A2u247 +Y5w== X-Gm-Message-State: ANhLgQ204nerC6/UhmkQYRzXDKfq51sejZcAU4+hcSqlXWEtraPdsENV BjBtNpnKCBePdpGpdKnXhp0ISA== X-Google-Smtp-Source: ADFU+vtln9Fd09Sl/Kyd/Fvp8vW2oxUjrs33nYEZF8jMY4c/JzrfP10IB/KaIRhHlM25wSbaiW9FkA== X-Received: by 2002:a1c:5604:: with SMTP id k4mr4510320wmb.57.1585045244803; Tue, 24 Mar 2020 03:20:44 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5c5f:613e:f775:b6a2]) by smtp.gmail.com with ESMTPSA id h5sm2879527wro.83.2020.03.24.03.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2020 03:20:44 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/13] usb: dwc3: meson-g12a: refactor usb2 phy init Date: Tue, 24 Mar 2020 11:20:22 +0100 Message-Id: <20200324102030.31000-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200324102030.31000-1-narmstrong@baylibre.com> References: <20200324102030.31000-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Refactor the USB2 PHY init code patch to handle the Amlogic GXL/GXM not having the PHY mode control registers in the Glue but in the PHY registers. The Amlogic GXL/GXM will call phy_set_mode() instead of programming the PHY mode control registers, thus add two new callbacks to the SoC match data. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 78 +++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 24a50dde685c..74d07ded8a7e 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -128,11 +128,21 @@ struct dwc3_meson_g12a_drvdata { const char **phy_names; int num_phys; int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); + int (*usb2_init_phy)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); }; static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -140,6 +150,8 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -149,6 +161,8 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; struct dwc3_meson_g12a { @@ -167,8 +181,8 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; -static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, - int i, enum phy_mode mode) +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) regmap_update_bits(priv->u2p_regmap[i], U2P_R0, @@ -177,11 +191,41 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, else regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); + + return 0; +} + +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + int ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); + + ret = priv->drvdata->set_phy_mode(priv, i, mode); + } else + ret = priv->drvdata->set_phy_mode(priv, i, + PHY_MODE_USB_HOST); + + if (ret) + return ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, 0); + + return 0; } static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) { - int i; + int i, ret; if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) priv->otg_phy_mode = PHY_MODE_USB_DEVICE; @@ -195,23 +239,9 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, - U2P_R0_POWER_ON_RESET); - - if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); - - dwc3_meson_g12a_usb2_set_mode(priv, i, - priv->otg_phy_mode); - } else - dwc3_meson_g12a_usb2_set_mode(priv, i, - PHY_MODE_USB_HOST); - - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, 0); + ret = priv->drvdata->usb2_init_phy(priv, i, mode); + if (ret) + return ret; } return 0; @@ -364,7 +394,9 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, priv->otg_phy_mode = mode; - dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, mode); + if (ret) + return ret; dwc3_meson_g12a_usb_otg_apply_mode(priv); @@ -580,7 +612,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - dwc3_meson_g12a_usb_init(priv); + ret = dwc3_meson_g12a_usb_init(priv); + if (ret) + goto err_disable_clks; /* Init PHYs */ for (i = 0 ; i < PHY_COUNT ; ++i) { -- 2.22.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEDEAC43331 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Refactor the USB2 PHY init code patch to handle the Amlogic GXL/GXM not having the PHY mode control registers in the Glue but in the PHY registers. The Amlogic GXL/GXM will call phy_set_mode() instead of programming the PHY mode control registers, thus add two new callbacks to the SoC match data. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 78 +++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 24a50dde685c..74d07ded8a7e 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -128,11 +128,21 @@ struct dwc3_meson_g12a_drvdata { const char **phy_names; int num_phys; int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); + int (*usb2_init_phy)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); }; static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -140,6 +150,8 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -149,6 +161,8 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; struct dwc3_meson_g12a { @@ -167,8 +181,8 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; -static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, - int i, enum phy_mode mode) +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) regmap_update_bits(priv->u2p_regmap[i], U2P_R0, @@ -177,11 +191,41 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, else regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); + + return 0; +} + +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + int ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); + + ret = priv->drvdata->set_phy_mode(priv, i, mode); + } else + ret = priv->drvdata->set_phy_mode(priv, i, + PHY_MODE_USB_HOST); + + if (ret) + return ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, 0); + + return 0; } static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) { - int i; + int i, ret; if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) priv->otg_phy_mode = PHY_MODE_USB_DEVICE; @@ -195,23 +239,9 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, - U2P_R0_POWER_ON_RESET); - - if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); - - dwc3_meson_g12a_usb2_set_mode(priv, i, - priv->otg_phy_mode); - } else - dwc3_meson_g12a_usb2_set_mode(priv, i, - PHY_MODE_USB_HOST); - - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, 0); + ret = priv->drvdata->usb2_init_phy(priv, i, mode); + if (ret) + return ret; } return 0; @@ -364,7 +394,9 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, priv->otg_phy_mode = mode; - dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, mode); + if (ret) + return ret; dwc3_meson_g12a_usb_otg_apply_mode(priv); @@ -580,7 +612,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - dwc3_meson_g12a_usb_init(priv); + ret = dwc3_meson_g12a_usb_init(priv); + if (ret) + goto err_disable_clks; /* Init PHYs */ for (i = 0 ; i < PHY_COUNT ; ++i) { -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DD36C4332B for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Refactor the USB2 PHY init code patch to handle the Amlogic GXL/GXM not having the PHY mode control registers in the Glue but in the PHY registers. The Amlogic GXL/GXM will call phy_set_mode() instead of programming the PHY mode control registers, thus add two new callbacks to the SoC match data. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 78 +++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 24a50dde685c..74d07ded8a7e 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -128,11 +128,21 @@ struct dwc3_meson_g12a_drvdata { const char **phy_names; int num_phys; int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); + int (*usb2_init_phy)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); }; static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); + +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -140,6 +150,8 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -149,6 +161,8 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), .setup_regmaps = dwc3_meson_g12a_setup_regmaps, + .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy, + .set_phy_mode = dwc3_meson_g12a_set_phy_mode, }; struct dwc3_meson_g12a { @@ -167,8 +181,8 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; -static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, - int i, enum phy_mode mode) +static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) regmap_update_bits(priv->u2p_regmap[i], U2P_R0, @@ -177,11 +191,41 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, else regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); + + return 0; +} + +static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + int ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); + + ret = priv->drvdata->set_phy_mode(priv, i, mode); + } else + ret = priv->drvdata->set_phy_mode(priv, i, + PHY_MODE_USB_HOST); + + if (ret) + return ret; + + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, + U2P_R0_POWER_ON_RESET, 0); + + return 0; } static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) { - int i; + int i, ret; if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) priv->otg_phy_mode = PHY_MODE_USB_DEVICE; @@ -195,23 +239,9 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, - U2P_R0_POWER_ON_RESET); - - if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, - U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); - - dwc3_meson_g12a_usb2_set_mode(priv, i, - priv->otg_phy_mode); - } else - dwc3_meson_g12a_usb2_set_mode(priv, i, - PHY_MODE_USB_HOST); - - regmap_update_bits(priv->u2p_regmap[i], U2P_R0, - U2P_R0_POWER_ON_RESET, 0); + ret = priv->drvdata->usb2_init_phy(priv, i, mode); + if (ret) + return ret; } return 0; @@ -364,7 +394,9 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, priv->otg_phy_mode = mode; - dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, mode); + if (ret) + return ret; dwc3_meson_g12a_usb_otg_apply_mode(priv); @@ -580,7 +612,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - dwc3_meson_g12a_usb_init(priv); + ret = dwc3_meson_g12a_usb_init(priv); + if (ret) + goto err_disable_clks; /* Init PHYs */ for (i = 0 ; i < PHY_COUNT ; ++i) { -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic