From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62F2FC2D0E9 for ; Mon, 30 Mar 2020 11:34:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2FFD120748 for ; Mon, 30 Mar 2020 11:34:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729893AbgC3Le5 (ORCPT ); Mon, 30 Mar 2020 07:34:57 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:59054 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729809AbgC3Ley (ORCPT ); Mon, 30 Mar 2020 07:34:54 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 128DB29260A From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com, linux-rockchip@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@collabora.com, Andrzej Hajda , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Fabio Estevam , Emil Velikov , Sjoerd Simons , Martyn Welch Subject: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver Date: Mon, 30 Mar 2020 14:35:41 +0300 Message-Id: <20200330113542.181752-5-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330113542.181752-1-adrian.ratiu@collabora.com> References: <20200330113542.181752-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for the Synopsis DesignWare MIPI DSI v1.01 host controller which is embedded in i.MX 6 SoCs. Based on following patches, but updated/extended to work with existing support found in the kernel: - drm: imx: Support Synopsys DesignWare MIPI DSI host controller Signed-off-by: Liu Ying - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller Signed-off-by: Liu Ying Cc: Fabio Estevam Reviewed-by: Emil Velikov Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Signed-off-by: Adrian Ratiu --- Changes since v4: - Split off driver-specific configuration of phy timings due to new upstream API. - Move regmap infrastructure logic to separate commit (Ezequiel) - Move dsi v1.01 layout addition to a separate commit (Ezequiel) - Minor warnings and driver name fixes Changes since v3: - Renamed platform driver to reflect it's i.MX6 only. (Fabio) Changes since v2: - Fixed commit tags. (Emil) Changes since v1: - Moved register definitions & regmap initialization into bridge module. Platform drivers get the regmap via plat_data after calling the bridge probe. (Emil) --- drivers/gpu/drm/imx/Kconfig | 7 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +++++++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig index 207bf7409dfb..b49e70e7f0fd 100644 --- a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,10 @@ config DRM_IMX_HDMI depends on DRM_IMX help Choose this if you want to use HDMI on i.MX6. + +config DRM_IMX6_MIPI_DSI + tristate "Freescale i.MX6 DRM MIPI DSI" + select DRM_DW_MIPI_DSI + depends on DRM_IMX + help + Choose this if you want to use MIPI DSI on i.MX6. diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile index 21cdcc2faabc..9a7843c59347 100644 --- a/drivers/gpu/drm/imx/Makefile +++ b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 index 000000000000..56b17d8670a2 --- /dev/null +++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm driver - MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-drm.h" + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUP BIT(0) + +#define DSI_PHY_IF_CTRL 0x5c +#define PHY_IF_CTRL_RESET 0x0 + +#define DSI_PHY_TST_CTRL0 0x64 +#define PHY_TESTCLK BIT(1) +#define PHY_UNTESTCLK 0 +#define PHY_TESTCLR BIT(0) +#define PHY_UNTESTCLR 0 + +#define DSI_PHY_TST_CTRL1 0x68 +#define PHY_TESTEN BIT(16) +#define PHY_UNTESTEN 0 +#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) +#define PHY_TESTDIN(n) (((n) & 0xff) << 0) + +struct imx_mipi_dsi { + struct drm_encoder encoder; + struct device *dev; + struct regmap *mux_sel; + struct dw_mipi_dsi *mipi_dsi; + struct clk *pllref_clk; + + void __iomem *base; + unsigned int lane_mbps; +}; + +struct dphy_pll_testdin_map { + unsigned int max_mbps; + u8 testdin; +}; + +/* The table is based on 27MHz DPHY pll reference clock. */ +static const struct dphy_pll_testdin_map dptdin_map[] = { + {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06}, + {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28}, + {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c}, + {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10}, + {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14}, + {900, 0x34}, {950, 0x54}, {1000, 0x74} +}; + +static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc) +{ + return container_of(enc, struct imx_mipi_dsi, encoder); +} + +static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di) +{ + regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3, + IMX6Q_GPR3_MIPI_MUX_CTL_MASK, + ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT); +} + +static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn) +{ + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); + + /* The following values are taken from dw_hdmi_imx_atomic_check */ + imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + imx_crtc_state->di_hsync_pin = 2; + imx_crtc_state->di_vsync_pin = 3; + + return 0; +} + +static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_mipi_dsi *dsi = enc_to_dsi(encoder); + int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder); + + imx_mipi_dsi_set_ipu_di_mux(dsi, mux); +} + +static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder) +{ +} + +static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = { + .mode_fixup = imx_mipi_dsi_encoder_mode_fixup, + .commit = imx_mipi_dsi_encoder_commit, + .disable = imx_mipi_dsi_encoder_disable, + .atomic_check = imx_mipi_dsi_encoder_atomic_check, +}; + +static int imx_mipi_dsi_register(struct drm_device *drm, + struct imx_mipi_dsi *dsi) +{ + int ret; + + ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node); + if (ret) + return ret; + + drm_encoder_helper_add(&dsi->encoder, + &imx_mipi_dsi_encoder_helpers); + drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs, + DRM_MODE_ENCODER_DSI, NULL); + return 0; +} + +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data, + const struct drm_display_mode *mode) +{ + /* + * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG + * register is 11-bit. + */ + if (mode->hdisplay > 0x7ff) + return MODE_BAD_HVALUE; + + /* + * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG + * register is 11-bit. + */ + if (mode->vdisplay > 0x7ff) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + + +static unsigned int max_mbps_to_testdin(unsigned int max_mbps) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) + if (dptdin_map[i].max_mbps == max_mbps) + return dptdin_map[i].testdin; + + return -EINVAL; +} + +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val) +{ + writel(val, dsi->base + reg); +} + +static int imx_mipi_dsi_phy_init(void *priv_data) +{ + struct imx_mipi_dsi *dsi = priv_data; + int testdin; + + testdin = max_mbps_to_testdin(dsi->lane_mbps); + if (testdin < 0) { + dev_err(dsi->dev, + "failed to get testdin for %dmbps lane clock\n", + dsi->lane_mbps); + return testdin; + } + + dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET); + dsi_write(dsi, DSI_PWR_UP, POWERUP); + + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(0x44)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(testdin)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + + return 0; +} + +static int imx_mipi_dsi_get_lane_mbps(void *priv_data, + const struct drm_display_mode *mode, + unsigned long mode_flags, u32 lanes, + u32 format, unsigned int *lane_mbps) +{ + struct imx_mipi_dsi *dsi = priv_data; + int bpp; + unsigned int i, target_mbps, mpclk; + unsigned long pllref; + + bpp = mipi_dsi_pixel_format_to_bpp(format); + if (bpp < 0) { + dev_err(dsi->dev, "failed to get bpp for pixel format %d\n", + format); + return bpp; + } + + pllref = clk_get_rate(dsi->pllref_clk); + if (pllref != 27000000) + dev_warn(dsi->dev, "expect 27MHz DPHY pll reference clock\n"); + + mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); + if (mpclk) { + /* take 1/0.7 blanking overhead into consideration */ + target_mbps = (mpclk * (bpp / lanes) * 10) / 7; + } else { + dev_dbg(dsi->dev, "use default 1Gbps DPHY pll clock\n"); + target_mbps = 1000; + } + + dev_dbg(dsi->dev, "target DPHY pll clock frequency is %uMbps\n", + target_mbps); + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) { + if (target_mbps < dptdin_map[i].max_mbps) { + *lane_mbps = dptdin_map[i].max_mbps; + dsi->lane_mbps = *lane_mbps; + dev_dbg(dsi->dev, + "real DPHY pll clock frequency is %uMbps\n", + *lane_mbps); + return 0; + } + } + + dev_err(dsi->dev, "DPHY clock frequency %uMbps is out of range\n", + target_mbps); + + return -EINVAL; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + timing->clk_hs2lp = 0x40; + timing->clk_lp2hs = 0x40; + timing->data_hs2lp = 0x40; + timing->data_lp2hs = 0x40; + + return 0; +} + +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = { + .init = imx_mipi_dsi_phy_init, + .get_lane_mbps = imx_mipi_dsi_get_lane_mbps, + .get_timing = dw_mipi_dsi_phy_get_timing, +}; + +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = { + .max_data_lanes = 2, + .mode_valid = imx_mipi_dsi_mode_valid, + .phy_ops = &dw_mipi_dsi_imx6_phy_ops, +}; + +static const struct of_device_id imx_dsi_dt_ids[] = { + { + .compatible = "fsl,imx6q-mipi-dsi", + .data = &imx6q_mipi_dsi_drv_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids); + +static int imx_mipi_dsi_bind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + struct drm_device *drm = data; + int ret; + + ret = imx_mipi_dsi_register(drm, dsi); + if (ret) + return ret; + + ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder); + if (ret) + return ret; + + return 0; +} + +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + + return dw_mipi_dsi_unbind(dsi->mipi_dsi); +} + +static const struct component_ops imx_mipi_dsi_ops = { + .bind = imx_mipi_dsi_bind, + .unbind = imx_mipi_dsi_unbind, +}; + +static int imx_mipi_dsi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev); + struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data*) of_id->data; + struct imx_mipi_dsi *dsi; + struct resource *res; + int ret; + + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + dsi->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dsi->base = devm_ioremap_resource(dev, res); + if (IS_ERR(dsi->base)) { + DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); + return PTR_ERR(dsi->base); + } + + dsi->pllref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(dsi->pllref_clk)) { + ret = PTR_ERR(dsi->pllref_clk); + dev_dbg(dev, "%s: Unable to get pll reference clock: %d\n", + __func__, ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pllref_clk); + if (ret) { + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); + return ret; + } + + dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); + if (IS_ERR(dsi->mux_sel)) { + ret = PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s: Failed to get GPR regmap: %d\n", + __func__, ret); + return ret; + } + + dev_set_drvdata(dev, dsi); + + imx6q_mipi_dsi_drv_data.base = dsi->base; + imx6q_mipi_dsi_drv_data.priv_data = dsi; + + dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata); + if (IS_ERR(dsi->mipi_dsi)) { + ret = PTR_ERR(dsi->mipi_dsi); + dev_dbg(dev, "%s: Unable to probe DW DSI host device: %d\n", + __func__, ret); + return -ENODEV; + } + + return component_add(&pdev->dev, &imx_mipi_dsi_ops); +} + +static int imx_mipi_dsi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_mipi_dsi_ops); + return 0; +} + +static struct platform_driver imx_mipi_dsi_driver = { + .probe = imx_mipi_dsi_probe, + .remove = imx_mipi_dsi_remove, + .driver = { + .of_match_table = imx_dsi_dt_ids, + .name = "dw-mipi-dsi-imx6", + }, +}; +module_platform_driver(imx_mipi_dsi_driver); + +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver"); +MODULE_AUTHOR("Liu Ying "); +MODULE_LICENSE("GPL"); -- 2.26.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 384F4C43331 for ; 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bh=cZhmYjt/OiJqQOA/JtGxJ+bSrE35TVgezXEAVpovGfU=; b=BC7DG9YMGup+SE J16wk8wzLt1R2t32kA/83NrEHbUkNxRc1pjkBTFPf4dF6iFDYrXF27kh0XSA8NkMxT1jcHr0er94J Kabx0FAJKo+4gAssb4JzDxx8NzPDeJhXm03M1yo3EfHTqiLzZhTG/deFZ6rvf+xFV6MuPzQART/l+ 0JoXQbyOiZK+8RZSdj/ORvuznX3wftu8wYj1/ngHwuTnhZRnMZwLgMhPWh+33vTf2lPKSt7p9zBfm jbzptX2Q/gHfKmrBZwhdBh2IJvU/3/MwDABTHZ8ogRW3pv4KNmrZbdHkHzbGk7Nrd1NxizsyloFfr bSZmTXSbTUWqrsCiuzpw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jIsil-0001q9-O1; Mon, 30 Mar 2020 11:36:47 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jIsh0-0007TS-UB; Mon, 30 Mar 2020 11:35:01 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 128DB29260A From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver Date: Mon, 30 Mar 2020 14:35:41 +0300 Message-Id: <20200330113542.181752-5-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330113542.181752-1-adrian.ratiu@collabora.com> References: <20200330113542.181752-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200330_043459_279473_4923ED2F X-CRM114-Status: GOOD ( 20.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , Sjoerd Simons , Andrzej Hajda , Martyn Welch , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Emil Velikov , linux-rockchip@lists.infradead.org, linux-imx@nxp.com, kernel@collabora.com, Fabio Estevam , linux-stm32@st-md-mailman.stormreply.com, Laurent Pinchart Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds support for the Synopsis DesignWare MIPI DSI v1.01 host controller which is embedded in i.MX 6 SoCs. Based on following patches, but updated/extended to work with existing support found in the kernel: - drm: imx: Support Synopsys DesignWare MIPI DSI host controller Signed-off-by: Liu Ying - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller Signed-off-by: Liu Ying Cc: Fabio Estevam Reviewed-by: Emil Velikov Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Signed-off-by: Adrian Ratiu --- Changes since v4: - Split off driver-specific configuration of phy timings due to new upstream API. - Move regmap infrastructure logic to separate commit (Ezequiel) - Move dsi v1.01 layout addition to a separate commit (Ezequiel) - Minor warnings and driver name fixes Changes since v3: - Renamed platform driver to reflect it's i.MX6 only. (Fabio) Changes since v2: - Fixed commit tags. (Emil) Changes since v1: - Moved register definitions & regmap initialization into bridge module. Platform drivers get the regmap via plat_data after calling the bridge probe. (Emil) --- drivers/gpu/drm/imx/Kconfig | 7 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +++++++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig index 207bf7409dfb..b49e70e7f0fd 100644 --- a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,10 @@ config DRM_IMX_HDMI depends on DRM_IMX help Choose this if you want to use HDMI on i.MX6. + +config DRM_IMX6_MIPI_DSI + tristate "Freescale i.MX6 DRM MIPI DSI" + select DRM_DW_MIPI_DSI + depends on DRM_IMX + help + Choose this if you want to use MIPI DSI on i.MX6. diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile index 21cdcc2faabc..9a7843c59347 100644 --- a/drivers/gpu/drm/imx/Makefile +++ b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 index 000000000000..56b17d8670a2 --- /dev/null +++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm driver - MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-drm.h" + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUP BIT(0) + +#define DSI_PHY_IF_CTRL 0x5c +#define PHY_IF_CTRL_RESET 0x0 + +#define DSI_PHY_TST_CTRL0 0x64 +#define PHY_TESTCLK BIT(1) +#define PHY_UNTESTCLK 0 +#define PHY_TESTCLR BIT(0) +#define PHY_UNTESTCLR 0 + +#define DSI_PHY_TST_CTRL1 0x68 +#define PHY_TESTEN BIT(16) +#define PHY_UNTESTEN 0 +#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) +#define PHY_TESTDIN(n) (((n) & 0xff) << 0) + +struct imx_mipi_dsi { + struct drm_encoder encoder; + struct device *dev; + struct regmap *mux_sel; + struct dw_mipi_dsi *mipi_dsi; + struct clk *pllref_clk; + + void __iomem *base; + unsigned int lane_mbps; +}; + +struct dphy_pll_testdin_map { + unsigned int max_mbps; + u8 testdin; +}; + +/* The table is based on 27MHz DPHY pll reference clock. */ +static const struct dphy_pll_testdin_map dptdin_map[] = { + {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06}, + {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28}, + {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c}, + {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10}, + {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14}, + {900, 0x34}, {950, 0x54}, {1000, 0x74} +}; + +static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc) +{ + return container_of(enc, struct imx_mipi_dsi, encoder); +} + +static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di) +{ + regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3, + IMX6Q_GPR3_MIPI_MUX_CTL_MASK, + ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT); +} + +static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn) +{ + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); + + /* The following values are taken from dw_hdmi_imx_atomic_check */ + imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + imx_crtc_state->di_hsync_pin = 2; + imx_crtc_state->di_vsync_pin = 3; + + return 0; +} + +static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_mipi_dsi *dsi = enc_to_dsi(encoder); + int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder); + + imx_mipi_dsi_set_ipu_di_mux(dsi, mux); +} + +static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder) +{ +} + +static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = { + .mode_fixup = imx_mipi_dsi_encoder_mode_fixup, + .commit = imx_mipi_dsi_encoder_commit, + .disable = imx_mipi_dsi_encoder_disable, + .atomic_check = imx_mipi_dsi_encoder_atomic_check, +}; + +static int imx_mipi_dsi_register(struct drm_device *drm, + struct imx_mipi_dsi *dsi) +{ + int ret; + + ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node); + if (ret) + return ret; + + drm_encoder_helper_add(&dsi->encoder, + &imx_mipi_dsi_encoder_helpers); + drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs, + DRM_MODE_ENCODER_DSI, NULL); + return 0; +} + +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data, + const struct drm_display_mode *mode) +{ + /* + * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG + * register is 11-bit. + */ + if (mode->hdisplay > 0x7ff) + return MODE_BAD_HVALUE; + + /* + * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG + * register is 11-bit. + */ + if (mode->vdisplay > 0x7ff) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + + +static unsigned int max_mbps_to_testdin(unsigned int max_mbps) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) + if (dptdin_map[i].max_mbps == max_mbps) + return dptdin_map[i].testdin; + + return -EINVAL; +} + +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val) +{ + writel(val, dsi->base + reg); +} + +static int imx_mipi_dsi_phy_init(void *priv_data) +{ + struct imx_mipi_dsi *dsi = priv_data; + int testdin; + + testdin = max_mbps_to_testdin(dsi->lane_mbps); + if (testdin < 0) { + dev_err(dsi->dev, + "failed to get testdin for %dmbps lane clock\n", + dsi->lane_mbps); + return testdin; + } + + dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET); + dsi_write(dsi, DSI_PWR_UP, POWERUP); + + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(0x44)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(testdin)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + + return 0; +} + +static int imx_mipi_dsi_get_lane_mbps(void *priv_data, + const struct drm_display_mode *mode, + unsigned long mode_flags, u32 lanes, + u32 format, unsigned int *lane_mbps) +{ + struct imx_mipi_dsi *dsi = priv_data; + int bpp; + unsigned int i, target_mbps, mpclk; + unsigned long pllref; + + bpp = mipi_dsi_pixel_format_to_bpp(format); + if (bpp < 0) { + dev_err(dsi->dev, "failed to get bpp for pixel format %d\n", + format); + return bpp; + } + + pllref = clk_get_rate(dsi->pllref_clk); + if (pllref != 27000000) + dev_warn(dsi->dev, "expect 27MHz DPHY pll reference clock\n"); + + mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); + if (mpclk) { + /* take 1/0.7 blanking overhead into consideration */ + target_mbps = (mpclk * (bpp / lanes) * 10) / 7; + } else { + dev_dbg(dsi->dev, "use default 1Gbps DPHY pll clock\n"); + target_mbps = 1000; + } + + dev_dbg(dsi->dev, "target DPHY pll clock frequency is %uMbps\n", + target_mbps); + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) { + if (target_mbps < dptdin_map[i].max_mbps) { + *lane_mbps = dptdin_map[i].max_mbps; + dsi->lane_mbps = *lane_mbps; + dev_dbg(dsi->dev, + "real DPHY pll clock frequency is %uMbps\n", + *lane_mbps); + return 0; + } + } + + dev_err(dsi->dev, "DPHY clock frequency %uMbps is out of range\n", + target_mbps); + + return -EINVAL; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + timing->clk_hs2lp = 0x40; + timing->clk_lp2hs = 0x40; + timing->data_hs2lp = 0x40; + timing->data_lp2hs = 0x40; + + return 0; +} + +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = { + .init = imx_mipi_dsi_phy_init, + .get_lane_mbps = imx_mipi_dsi_get_lane_mbps, + .get_timing = dw_mipi_dsi_phy_get_timing, +}; + +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = { + .max_data_lanes = 2, + .mode_valid = imx_mipi_dsi_mode_valid, + .phy_ops = &dw_mipi_dsi_imx6_phy_ops, +}; + +static const struct of_device_id imx_dsi_dt_ids[] = { + { + .compatible = "fsl,imx6q-mipi-dsi", + .data = &imx6q_mipi_dsi_drv_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids); + +static int imx_mipi_dsi_bind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + struct drm_device *drm = data; + int ret; + + ret = imx_mipi_dsi_register(drm, dsi); + if (ret) + return ret; + + ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder); + if (ret) + return ret; + + return 0; +} + +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + + return dw_mipi_dsi_unbind(dsi->mipi_dsi); +} + +static const struct component_ops imx_mipi_dsi_ops = { + .bind = imx_mipi_dsi_bind, + .unbind = imx_mipi_dsi_unbind, +}; + +static int imx_mipi_dsi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev); + struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data*) of_id->data; + struct imx_mipi_dsi *dsi; + struct resource *res; + int ret; + + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + dsi->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dsi->base = devm_ioremap_resource(dev, res); + if (IS_ERR(dsi->base)) { + DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); + return PTR_ERR(dsi->base); + } + + dsi->pllref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(dsi->pllref_clk)) { + ret = PTR_ERR(dsi->pllref_clk); + dev_dbg(dev, "%s: Unable to get pll reference clock: %d\n", + __func__, ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pllref_clk); + if (ret) { + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); + return ret; + } + + dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); + if (IS_ERR(dsi->mux_sel)) { + ret = PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s: Failed to get GPR regmap: %d\n", + __func__, ret); + return ret; + } + + dev_set_drvdata(dev, dsi); + + imx6q_mipi_dsi_drv_data.base = dsi->base; + imx6q_mipi_dsi_drv_data.priv_data = dsi; + + dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata); + if (IS_ERR(dsi->mipi_dsi)) { + ret = PTR_ERR(dsi->mipi_dsi); + dev_dbg(dev, "%s: Unable to probe DW DSI host device: %d\n", + __func__, ret); + return -ENODEV; + } + + return component_add(&pdev->dev, &imx_mipi_dsi_ops); +} + +static int imx_mipi_dsi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_mipi_dsi_ops); + return 0; +} + +static struct platform_driver imx_mipi_dsi_driver = { + .probe = imx_mipi_dsi_probe, + .remove = imx_mipi_dsi_remove, + .driver = { + .of_match_table = imx_dsi_dt_ids, + .name = "dw-mipi-dsi-imx6", + }, +}; +module_platform_driver(imx_mipi_dsi_driver); + +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver"); +MODULE_AUTHOR("Liu Ying "); +MODULE_LICENSE("GPL"); -- 2.26.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DC51C2D0F3 for ; Mon, 30 Mar 2020 11:35:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A92B2073B for ; Mon, 30 Mar 2020 11:35:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A92B2073B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36A1A6E25D; Mon, 30 Mar 2020 11:35:06 +0000 (UTC) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3BC86E255 for ; Mon, 30 Mar 2020 11:34:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 128DB29260A From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver Date: Mon, 30 Mar 2020 14:35:41 +0300 Message-Id: <20200330113542.181752-5-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330113542.181752-1-adrian.ratiu@collabora.com> References: <20200330113542.181752-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , Sjoerd Simons , Andrzej Hajda , Martyn Welch , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Emil Velikov , linux-rockchip@lists.infradead.org, linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Laurent Pinchart Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds support for the Synopsis DesignWare MIPI DSI v1.01 host controller which is embedded in i.MX 6 SoCs. Based on following patches, but updated/extended to work with existing support found in the kernel: - drm: imx: Support Synopsys DesignWare MIPI DSI host controller Signed-off-by: Liu Ying - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller Signed-off-by: Liu Ying Cc: Fabio Estevam Reviewed-by: Emil Velikov Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Signed-off-by: Adrian Ratiu --- Changes since v4: - Split off driver-specific configuration of phy timings due to new upstream API. - Move regmap infrastructure logic to separate commit (Ezequiel) - Move dsi v1.01 layout addition to a separate commit (Ezequiel) - Minor warnings and driver name fixes Changes since v3: - Renamed platform driver to reflect it's i.MX6 only. (Fabio) Changes since v2: - Fixed commit tags. (Emil) Changes since v1: - Moved register definitions & regmap initialization into bridge module. Platform drivers get the regmap via plat_data after calling the bridge probe. (Emil) --- drivers/gpu/drm/imx/Kconfig | 7 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +++++++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig index 207bf7409dfb..b49e70e7f0fd 100644 --- a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,10 @@ config DRM_IMX_HDMI depends on DRM_IMX help Choose this if you want to use HDMI on i.MX6. + +config DRM_IMX6_MIPI_DSI + tristate "Freescale i.MX6 DRM MIPI DSI" + select DRM_DW_MIPI_DSI + depends on DRM_IMX + help + Choose this if you want to use MIPI DSI on i.MX6. diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile index 21cdcc2faabc..9a7843c59347 100644 --- a/drivers/gpu/drm/imx/Makefile +++ b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 index 000000000000..56b17d8670a2 --- /dev/null +++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm driver - MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-drm.h" + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUP BIT(0) + +#define DSI_PHY_IF_CTRL 0x5c +#define PHY_IF_CTRL_RESET 0x0 + +#define DSI_PHY_TST_CTRL0 0x64 +#define PHY_TESTCLK BIT(1) +#define PHY_UNTESTCLK 0 +#define PHY_TESTCLR BIT(0) +#define PHY_UNTESTCLR 0 + +#define DSI_PHY_TST_CTRL1 0x68 +#define PHY_TESTEN BIT(16) +#define PHY_UNTESTEN 0 +#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) +#define PHY_TESTDIN(n) (((n) & 0xff) << 0) + +struct imx_mipi_dsi { + struct drm_encoder encoder; + struct device *dev; + struct regmap *mux_sel; + struct dw_mipi_dsi *mipi_dsi; + struct clk *pllref_clk; + + void __iomem *base; + unsigned int lane_mbps; +}; + +struct dphy_pll_testdin_map { + unsigned int max_mbps; + u8 testdin; +}; + +/* The table is based on 27MHz DPHY pll reference clock. */ +static const struct dphy_pll_testdin_map dptdin_map[] = { + {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06}, + {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28}, + {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c}, + {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10}, + {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14}, + {900, 0x34}, {950, 0x54}, {1000, 0x74} +}; + +static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc) +{ + return container_of(enc, struct imx_mipi_dsi, encoder); +} + +static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di) +{ + regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3, + IMX6Q_GPR3_MIPI_MUX_CTL_MASK, + ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT); +} + +static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn) +{ + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); + + /* The following values are taken from dw_hdmi_imx_atomic_check */ + imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + imx_crtc_state->di_hsync_pin = 2; + imx_crtc_state->di_vsync_pin = 3; + + return 0; +} + +static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_mipi_dsi *dsi = enc_to_dsi(encoder); + int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder); + + imx_mipi_dsi_set_ipu_di_mux(dsi, mux); +} + +static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder) +{ +} + +static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = { + .mode_fixup = imx_mipi_dsi_encoder_mode_fixup, + .commit = imx_mipi_dsi_encoder_commit, + .disable = imx_mipi_dsi_encoder_disable, + .atomic_check = imx_mipi_dsi_encoder_atomic_check, +}; + +static int imx_mipi_dsi_register(struct drm_device *drm, + struct imx_mipi_dsi *dsi) +{ + int ret; + + ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node); + if (ret) + return ret; + + drm_encoder_helper_add(&dsi->encoder, + &imx_mipi_dsi_encoder_helpers); + drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs, + DRM_MODE_ENCODER_DSI, NULL); + return 0; +} + +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data, + const struct drm_display_mode *mode) +{ + /* + * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG + * register is 11-bit. + */ + if (mode->hdisplay > 0x7ff) + return MODE_BAD_HVALUE; + + /* + * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG + * register is 11-bit. + */ + if (mode->vdisplay > 0x7ff) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + + +static unsigned int max_mbps_to_testdin(unsigned int max_mbps) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) + if (dptdin_map[i].max_mbps == max_mbps) + return dptdin_map[i].testdin; + + return -EINVAL; +} + +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val) +{ + writel(val, dsi->base + reg); +} + +static int imx_mipi_dsi_phy_init(void *priv_data) +{ + struct imx_mipi_dsi *dsi = priv_data; + int testdin; + + testdin = max_mbps_to_testdin(dsi->lane_mbps); + if (testdin < 0) { + dev_err(dsi->dev, + "failed to get testdin for %dmbps lane clock\n", + dsi->lane_mbps); + return testdin; + } + + dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET); + dsi_write(dsi, DSI_PWR_UP, POWERUP); + + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(0x44)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | + PHY_TESTDIN(testdin)); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); + + return 0; +} + +static int imx_mipi_dsi_get_lane_mbps(void *priv_data, + const struct drm_display_mode *mode, + unsigned long mode_flags, u32 lanes, + u32 format, unsigned int *lane_mbps) +{ + struct imx_mipi_dsi *dsi = priv_data; + int bpp; + unsigned int i, target_mbps, mpclk; + unsigned long pllref; + + bpp = mipi_dsi_pixel_format_to_bpp(format); + if (bpp < 0) { + dev_err(dsi->dev, "failed to get bpp for pixel format %d\n", + format); + return bpp; + } + + pllref = clk_get_rate(dsi->pllref_clk); + if (pllref != 27000000) + dev_warn(dsi->dev, "expect 27MHz DPHY pll reference clock\n"); + + mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); + if (mpclk) { + /* take 1/0.7 blanking overhead into consideration */ + target_mbps = (mpclk * (bpp / lanes) * 10) / 7; + } else { + dev_dbg(dsi->dev, "use default 1Gbps DPHY pll clock\n"); + target_mbps = 1000; + } + + dev_dbg(dsi->dev, "target DPHY pll clock frequency is %uMbps\n", + target_mbps); + + for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) { + if (target_mbps < dptdin_map[i].max_mbps) { + *lane_mbps = dptdin_map[i].max_mbps; + dsi->lane_mbps = *lane_mbps; + dev_dbg(dsi->dev, + "real DPHY pll clock frequency is %uMbps\n", + *lane_mbps); + return 0; + } + } + + dev_err(dsi->dev, "DPHY clock frequency %uMbps is out of range\n", + target_mbps); + + return -EINVAL; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + timing->clk_hs2lp = 0x40; + timing->clk_lp2hs = 0x40; + timing->data_hs2lp = 0x40; + timing->data_lp2hs = 0x40; + + return 0; +} + +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = { + .init = imx_mipi_dsi_phy_init, + .get_lane_mbps = imx_mipi_dsi_get_lane_mbps, + .get_timing = dw_mipi_dsi_phy_get_timing, +}; + +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = { + .max_data_lanes = 2, + .mode_valid = imx_mipi_dsi_mode_valid, + .phy_ops = &dw_mipi_dsi_imx6_phy_ops, +}; + +static const struct of_device_id imx_dsi_dt_ids[] = { + { + .compatible = "fsl,imx6q-mipi-dsi", + .data = &imx6q_mipi_dsi_drv_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids); + +static int imx_mipi_dsi_bind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + struct drm_device *drm = data; + int ret; + + ret = imx_mipi_dsi_register(drm, dsi); + if (ret) + return ret; + + ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder); + if (ret) + return ret; + + return 0; +} + +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_mipi_dsi *dsi = dev_get_drvdata(dev); + + return dw_mipi_dsi_unbind(dsi->mipi_dsi); +} + +static const struct component_ops imx_mipi_dsi_ops = { + .bind = imx_mipi_dsi_bind, + .unbind = imx_mipi_dsi_unbind, +}; + +static int imx_mipi_dsi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev); + struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data*) of_id->data; + struct imx_mipi_dsi *dsi; + struct resource *res; + int ret; + + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + dsi->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dsi->base = devm_ioremap_resource(dev, res); + if (IS_ERR(dsi->base)) { + DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); + return PTR_ERR(dsi->base); + } + + dsi->pllref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(dsi->pllref_clk)) { + ret = PTR_ERR(dsi->pllref_clk); + dev_dbg(dev, "%s: Unable to get pll reference clock: %d\n", + __func__, ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pllref_clk); + if (ret) { + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); + return ret; + } + + dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); + if (IS_ERR(dsi->mux_sel)) { + ret = PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s: Failed to get GPR regmap: %d\n", + __func__, ret); + return ret; + } + + dev_set_drvdata(dev, dsi); + + imx6q_mipi_dsi_drv_data.base = dsi->base; + imx6q_mipi_dsi_drv_data.priv_data = dsi; + + dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata); + if (IS_ERR(dsi->mipi_dsi)) { + ret = PTR_ERR(dsi->mipi_dsi); + dev_dbg(dev, "%s: Unable to probe DW DSI host device: %d\n", + __func__, ret); + return -ENODEV; + } + + return component_add(&pdev->dev, &imx_mipi_dsi_ops); +} + +static int imx_mipi_dsi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_mipi_dsi_ops); + return 0; +} + +static struct platform_driver imx_mipi_dsi_driver = { + .probe = imx_mipi_dsi_probe, + .remove = imx_mipi_dsi_remove, + .driver = { + .of_match_table = imx_dsi_dt_ids, + .name = "dw-mipi-dsi-imx6", + }, +}; +module_platform_driver(imx_mipi_dsi_driver); + +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver"); +MODULE_AUTHOR("Liu Ying "); +MODULE_LICENSE("GPL"); -- 2.26.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel