From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A6E7C43331 for ; Wed, 1 Apr 2020 07:56:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 39DA320714 for ; Wed, 1 Apr 2020 07:56:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 39DA320714 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C68F689DB2; Wed, 1 Apr 2020 07:56:20 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD7AA89D66 for ; Wed, 1 Apr 2020 07:56:19 +0000 (UTC) IronPort-SDR: 7yoVF28XxDX6c5jUlOAPyWt9cf7X7uSOcGMUDSb0Q19zgoWQvfqbtl7iNLQLPlzYoUQ3Aez9Wy kaxvQvVIijbA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2020 00:56:19 -0700 IronPort-SDR: MrVr/4n3qeGWAHHKUo1N/4FlWvowq1gkooC2g5ghCfLeVMcTpw53MwEUjnditKKN7MB1+w6hqv NX+WjqO9XVgw== X-IronPort-AV: E=Sophos;i="5.72,330,1580803200"; d="scan'208";a="395864331" Received: from unknown (HELO intel.com) ([10.237.72.89]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2020 00:56:18 -0700 Date: Wed, 1 Apr 2020 10:52:32 +0300 From: "Lisovskiy, Stanislav" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Message-ID: <20200401075232.GA1131@intel.com> References: <20200225171125.28885-1-ville.syrjala@linux.intel.com> <20200225171125.28885-6-ville.syrjala@linux.intel.com> <587c8ad3b5fc69b2ec0d4fcae302d4e8c959ba82.camel@intel.com> <20200302145037.GK13686@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200302145037.GK13686@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH v2 05/20] drm/i915: Make skl_compute_dbuf_slices() behave consistently for all platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Mar 02, 2020 at 04:50:37PM +0200, Ville Syrj=E4l=E4 wrote: > On Tue, Feb 25, 2020 at 05:30:57PM +0000, Lisovskiy, Stanislav wrote: > > On Tue, 2020-02-25 at 19:11 +0200, Ville Syrjala wrote: > > > From: Ville Syrj=E4l=E4 > > > = > > > Currently skl_compute_dbuf_slices() returns 0 for any inactive pipe > > > on > > > icl+, but returns BIT(S1) on pre-icl for any pipe (whether it's > > > active or > > > not). Let's make the behaviour consistent and always return 0 for any > > > inactive pipe. > > > = > > > Cc: Stanislav Lisovskiy > > > Signed-off-by: Ville Syrj=E4l=E4 > > > --- > > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > = > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index a2e78969c0df..640f4c4fd508 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4408,7 +4408,7 @@ static u8 skl_compute_dbuf_slices(const struct > > > intel_crtc_state *crtc_state, > > > * For anything else just return one slice yet. > > > * Should be extended for other platforms. > > > */ > > > - return BIT(DBUF_S1); > > > + return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0; > > = > > I think the initial idea was this won't be even called if there = > > are no active pipes at all - skl_ddb_get_pipe_allocation_limits would > > bail out immediately. If there were some active pipes - then we will > > have to use slice S1 anyway - because there were simply no other slices > > available. If some pipes were inactive - they are currently skipped by > > !crtc_state->hw.active check - so I would just keep it simple and don't > > call this function for non-active pipes at all. > = > That's just going to make the caller more messy by forcing it to > check for active_pipes 0 vs. not. Ie. we'd be splitting the > responsibility of computing the dbuf slices for this pipe between > skl_compute_dbuf_slices() and its caller. Not a good idea IMO. Let's ramp it up. As I understood from your comments we still need dbuf_sta= te. I would anyway add another table for handling this in some unified manner a= t least, however don't want to spend another couple of month discussing that :) Reviewed-by: Stanislav Lisovskiy > = > -- = > Ville Syrj=E4l=E4 > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx