From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 2 Apr 2020 18:10:31 -0400 Subject: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function In-Reply-To: <2a2c9b8d-dfee-c4ff-8602-119f8d2dbe60@denx.de> References: <7fa85609-d547-1784-d00a-2812cb6d8ea4@denx.de> <20200402205414.GU27133@bill-the-cat> <2a2c9b8d-dfee-c4ff-8602-119f8d2dbe60@denx.de> Message-ID: <20200402221031.GV27133@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Apr 02, 2020 at 11:07:31PM +0200, Marek Vasut wrote: > On 4/2/20 10:54 PM, Tom Rini wrote: > [...] > > >>>>>> I'm not sure it definitely should be changed. But I'll do a patch and > >>>>>> see how it looks. > >>>>> > >>>>> Do I understand it correctly that the patch > >>>>> 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks > >>>>> SoCFPGA ? Then I would say this is a release blocker ? > >>>> Yes. A10 SPL won't boot at all. It crashes during the clock manager setup. > >>> > >>> This came in right at the beginning of the cycle. I thought the > >>> purpose of the 3-month cycle was to allow time to test? > >> > >> It was ... altera ? > > > > Sorry, I'm missing how that's an answer to the question. This came in > > basically right at the start of the merge window. > > I don't have an A10 available right now, so what can I do ? Ah, so the answer is "I can't test this platform myself". That's what then, thanks. -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: