From: Yubo Miao <miaoyubo@huawei.com>
To: <peter.maydell@linaro.org>, <shannon.zhaosl@gmail.com>,
<lersek@redhat.com>
Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org,
xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com
Subject: [PATCH v6 6/8] unit-test: The files changed.
Date: Wed, 8 Apr 2020 20:58:14 +0800 [thread overview]
Message-ID: <20200408125816.955-7-miaoyubo@huawei.com> (raw)
In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com>
From: miaoyubo <miaoyubo@huawei.com>
The unit-test is seperated into three patches:
1. The files changed and list in bios-tables-test-allowed-diff.h
2. The unit-test
3. The binary file and clear bios-tables-test-allowed-diff.h
The ASL diff would also be listed.
Sice there are 1000+lines diff, some changes would be omitted.
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014BB (5307)
+ * Length 0x00001E7A (7802)
* Revision 0x02
- * Checksum 0xD1
+ * Checksum 0x57
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
+ Device (PC80)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, 0x80) // _BBN: BIOS Bus Number
+ Name (_UID, 0x80) // _UID: Unique ID
+ Name (_STR, Unicode ("pxb Device")) // _STR: Description String
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
Packages are omitted.
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ }
+ })
+ Device (GSI0)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
GSI1,2,3 are omitted.
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PC80._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PC80._OSC.CDW3 */
+ CTRL &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PC80.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
DSM is are omitted
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
- 0x00FF, // Range Maximum
+ 0x007F, // Range Maximum
0x0000, // Translation Offset
- 0x0100, // Length
+ 0x0080, // Length
Signed-off-by: miaoyubo <miaoyubo@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..90c53925fc 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/DSDT.pxb",
--
2.19.1
next prev parent reply other threads:[~2020-04-08 12:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 12:58 [PATCH v6 0/8] pci_expander_brdige:acpi:Support pxb-pcie for ARM Yubo Miao
2020-04-08 12:58 ` [PATCH v6 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Yubo Miao
2020-04-08 12:58 ` [PATCH v6 2/8] fw_cfg: Write the extra roots into the fw_cfg Yubo Miao
2020-05-04 14:02 ` Michael S. Tsirkin
2020-05-08 12:50 ` miaoyubo
2020-04-08 12:58 ` [PATCH v6 3/8] acpi: Extract crs build form acpi_build.c Yubo Miao
2020-04-08 12:58 ` [PATCH v6 4/8] acpi: Refactor the source of host bridge and build tables for pxb Yubo Miao
2020-05-04 14:00 ` Michael S. Tsirkin
2020-05-08 13:12 ` miaoyubo
2020-04-08 12:58 ` [PATCH v6 5/8] acpi: Align the size to 128k Yubo Miao
2020-05-04 14:03 ` Michael S. Tsirkin
2020-05-08 13:17 ` miaoyubo
2020-04-08 12:58 ` Yubo Miao [this message]
2020-04-08 12:58 ` [PATCH v6 7/8] unit-test: Add testcase for pxb Yubo Miao
2020-04-08 12:58 ` [PATCH v6 8/8] unit-test: Add the binary file and clear diff.h Yubo Miao
2020-04-08 13:11 ` [PATCH v6 0/8] pci_expander_brdige:acpi:Support pxb-pcie for ARM no-reply
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