[RESEND PATCH v3 0/7] x86: Improve support for chain-loading U-Boot

[RESEND PATCH v3 0/7] x86: Improve support for chain-loading U-Boot

[Simon Glass]

This little series adds a few checks into the code to allow better
operation when booting a build from a previous-state loader such as
coreboot.

At present we have a 'coreboot' target but this runs very different code
from the bare-metal targets, such as coral. There is very little in common
between them.

It is useful to be able to boot the same U-Boot on a device, with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.

This series allows U-Boot to detect that it ran from coreboot and
automatically do the right thing.

This series makes the most important changes to allow the same u-boot.bin
for coral to boot after coreboot (by itself) or bare metal (via TPL->SPL).

Changes in v3:
- Add a new patch with a gd flag for chain loading
- Add new patch to detect running from coreboot

Changes in v2:
- Drop the other check in interrupt_init() which is not needed now
- Drop patch 'dm: Avoid initing built-in devices when chain loading'

Simon Glass (7):
  x86: fsp: Allow skipping init code when chain loading
  x86: apl: Skip init code when chain loading
  x86: cpu: Skip init code when chain loading
  pci: Avoid auto-config when chain loading
  board: Add a gd flag for chain loading
  x86: Add a way to detect running from coreboot
  x86: Use the existing stack when chain-loading

 arch/x86/cpu/apollolake/fsp_s.c   |  2 ++
 arch/x86/cpu/cpu.c                |  4 +++-
 arch/x86/cpu/i386/cpu.c           | 15 +++++++++++++++
 arch/x86/cpu/i386/interrupt.c     |  6 ++++--
 arch/x86/cpu/start_from_spl.S     | 16 ++++++++++++++--
 arch/x86/include/asm/u-boot-x86.h |  7 +++++++
 arch/x86/lib/fsp/fsp_dram.c       |  8 ++++++++
 arch/x86/lib/fsp/fsp_graphics.c   |  3 +++
 arch/x86/lib/fsp2/fsp_dram.c      | 10 ++++++++++
 arch/x86/lib/fsp2/fsp_init.c      |  2 +-
 arch/x86/lib/init_helpers.c       |  3 +++
 drivers/pci/pci-uclass.c          |  4 ++--
 include/asm-generic/global_data.h |  1 +
 include/init.h                    |  2 +-
 14 files changed, 74 insertions(+), 9 deletions(-)

-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 1/7] x86: fsp: Allow skipping init code when chain loading

[Simon Glass]

It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.

When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.

Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/fsp/fsp_dram.c     |  8 ++++++++
 arch/x86/lib/fsp/fsp_graphics.c |  3 +++
 arch/x86/lib/fsp2/fsp_dram.c    | 10 ++++++++++
 arch/x86/lib/fsp2/fsp_init.c    |  2 +-
 4 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 9ce0ddf0d3d..15e82de2fe1 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -44,6 +44,14 @@ int dram_init_banksize(void)
 	phys_addr_t low_end;
 	uint bank;
 
+	if (!ll_boot_init()) {
+		gd->bd->bi_dram[0].start = 0;
+		gd->bd->bi_dram[0].size = gd->ram_size;
+
+		mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
+		return 0;
+	}
+
 	low_end = 0;
 	for (bank = 1, hdr = gd->arch.hob_list;
 	     bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 226c7e66b3f..98b762209f9 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -78,6 +78,9 @@ static int fsp_video_probe(struct udevice *dev)
 	struct vesa_mode_info *vesa = &mode_info.vesa;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
+
 	printf("Video: ");
 
 	/* Initialize vesa_mode_info structure */
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index 90a238a2245..74835eebcea 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -12,11 +12,18 @@
 #include <asm/fsp/fsp_support.h>
 #include <asm/fsp2/fsp_api.h>
 #include <asm/fsp2/fsp_internal.h>
+#include <linux/sizes.h>
 
 int dram_init(void)
 {
 	int ret;
 
+	if (!ll_boot_init()) {
+		/* Use a small and safe amount of 1GB */
+		gd->ram_size = SZ_1G;
+
+		return 0;
+	}
 	if (spl_phase() == PHASE_SPL) {
 #ifdef CONFIG_HAVE_ACPI_RESUME
 		bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
@@ -68,6 +75,9 @@ int dram_init(void)
 
 ulong board_get_usable_ram_top(ulong total_size)
 {
+	if (!ll_boot_init())
+		return gd->ram_size;
+
 #if CONFIG_IS_ENABLED(HANDOFF)
 	struct spl_handoff *ho = gd->spl_handoff;
 
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index da9bd6b45cf..c7dc2ea2578 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -23,7 +23,7 @@ int arch_cpu_init_dm(void)
 	int ret;
 
 	/* Make sure pads are set up early in U-Boot */
-	if (spl_phase() != PHASE_BOARD_F)
+	if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
 		return 0;
 
 	/* Probe all pinctrl devices to set up the pads */
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 2/7] x86: apl: Skip init code when chain loading

[Simon Glass]

When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/apollolake/fsp_s.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c6..5d252b11116 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -566,6 +566,8 @@ int arch_fsp_init_r(void)
 	struct udevice *dev, *itss;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
 	/*
 	 * This must be called before any devices are probed. Put any probing
 	 * into arch_fsps_preinit() above.
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 3/7] x86: cpu: Skip init code when chain loading

[Simon Glass]

When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- Drop the other check in interrupt_init() which is not needed now

 arch/x86/cpu/cpu.c            | 4 +++-
 arch/x86/cpu/i386/interrupt.c | 6 ++++--
 arch/x86/lib/init_helpers.c   | 3 +++
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index dae06949cc6..3db035c2c0e 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -239,8 +239,10 @@ int cpu_init_r(void)
 	struct udevice *dev;
 	int ret;
 
-	if (!ll_boot_init())
+	if (!ll_boot_init()) {
+		uclass_first_device(UCLASS_PCI, &dev);
 		return 0;
+	}
 
 	ret = x86_init_cpus();
 	if (ret)
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 4c7e9ea2151..e67a116ac1a 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -264,6 +264,9 @@ int interrupt_init(void)
 	struct udevice *dev;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
+
 	/* Try to set up the interrupt router, but don't require one */
 	ret = irq_first_device_type(X86_IRQT_BASE, &dev);
 	if (ret && ret != -ENODEV)
@@ -295,8 +298,7 @@ int interrupt_init(void)
 	 * TODO(sjg at chromium.org): But we don't handle these correctly when
 	 * booted from EFI.
 	 */
-	if (ll_boot_init())
-		enable_interrupts();
+	enable_interrupts();
 #endif
 
 	return 0;
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 5bb55e256fb..d906b528b35 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -30,6 +30,9 @@ int init_cache_f_r(void)
 			return ret;
 	}
 
+	if (!ll_boot_init())
+		return 0;
+
 	/* Initialise the CPU cache(s) */
 	return init_cache();
 }
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 4/7] pci: Avoid auto-config when chain loading

[Simon Glass]

When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- Drop patch 'dm: Avoid initing built-in devices when chain loading'

 drivers/pci/pci-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e2882e3b634..94733662b12 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1007,7 +1007,7 @@ static int pci_uclass_post_probe(struct udevice *bus)
 	if (ret)
 		return ret;
 
-	if (CONFIG_IS_ENABLED(PCI_PNP) &&
+	if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
 	    (!hose->skip_auto_config_until_reloc ||
 	     (gd->flags & GD_FLG_RELOC))) {
 		ret = pci_auto_config_devices(bus);
@@ -1029,7 +1029,7 @@ static int pci_uclass_post_probe(struct udevice *bus)
 	 * Note we only call this 1) after U-Boot is relocated, and 2)
 	 * root bus has finished probing.
 	 */
-	if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
+	if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
 		ret = fsp_init_phase_pci();
 		if (ret)
 			return ret;
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 5/7] board: Add a gd flag for chain loading

[Simon Glass]

When U-Boot is run from another boot loader, much of the low-level init
needs to be skipped.

Add a flag for this and adjust ll_boot_init() to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add a new patch with a gd flag for chain loading

Changes in v2: None

 include/asm-generic/global_data.h | 1 +
 include/init.h                    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 5d027329fe0..3dc51e49ef7 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -166,5 +166,6 @@ typedef struct global_data {
 #define GD_FLG_SPL_EARLY_INIT	0x04000 /* Early SPL init is done	   */
 #define GD_FLG_LOG_READY	0x08000 /* Log system is ready for use	   */
 #define GD_FLG_WDT_READY	0x10000 /* Watchdog is ready for use	   */
+#define GD_FLG_NO_LL_INIT	0x20000	/* Don't perform low-level init	   */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/init.h b/include/init.h
index 2a33a3fd1e4..64fdf124916 100644
--- a/include/init.h
+++ b/include/init.h
@@ -20,7 +20,7 @@ struct global_data;
 #ifdef CONFIG_EFI_STUB
 #define ll_boot_init()	false
 #else
-#define ll_boot_init()	true
+#define ll_boot_init()	(!(gd->flags & GD_FLG_NO_LL_INIT))
 #endif
 
 /*
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 6/7] x86: Add a way to detect running from coreboot

[Simon Glass]

If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add new patch to detect running from coreboot

Changes in v2: None

 arch/x86/cpu/i386/cpu.c           | 15 +++++++++++++++
 arch/x86/include/asm/u-boot-x86.h |  7 +++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c8da7f10e9b..e43444c090b 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -447,10 +447,25 @@ int x86_cpu_init_f(void)
 	return 0;
 }
 
+bool x86_detect_coreboot(void)
+{
+	u32 *ptr, *end;
+
+	/* We look for LBIO in the first 4K of RAM */
+	for (ptr = NULL, end = ptr + 0x400; ptr < end; ptr += 4) {
+		if (*ptr == 0x4f49424c) /* "LBIO" */
+			return true;
+	}
+
+	return false;
+}
+
 int x86_cpu_reinit_f(void)
 {
 	setup_identity();
 	setup_pci_ram_top();
+	if (x86_detect_coreboot())
+		gd->flags |= GD_FLG_NO_LL_INIT;
 
 	return 0;
 }
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 3e5d56d0757..654880f91cb 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -43,6 +43,13 @@ int x86_cpu_reinit_f(void);
  */
 int x86_cpu_init_tpl(void);
 
+/**
+ * x86_detect_coreboot() - See if U-Boot is being started from coreboot
+ *
+ * @return true if coreboot is running, false if U-Boot is running 'bare-metal'
+ */
+bool x86_detect_coreboot(void);
+
 int cpu_init_f(void);
 void setup_gdt(struct global_data *id, u64 *gdt_addr);
 /*
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 7/7] x86: Use the existing stack when chain-loading

[Simon Glass]

With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.

When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:

   cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
	-f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \
	-c lzma -l 0x1110000 -e 0x1110000

In this case U-Boot is run from coreboot (actually Depthcharge, its
payload) so we cannot access CAR. Use the existing stack instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/start_from_spl.S | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/start_from_spl.S b/arch/x86/cpu/start_from_spl.S
index 22cab2dd6ce..75c328fd7a8 100644
--- a/arch/x86/cpu/start_from_spl.S
+++ b/arch/x86/cpu/start_from_spl.S
@@ -14,18 +14,30 @@
 .globl _start
 .type _start, @function
 _start:
-	/* Set up memory using the existing stack */
+	/*
+	 * If running from coreboot, CAR is no-longer available. Use the
+	 * existing stack, which is large enough.
+	 */
+	call	x86_detect_coreboot
+	cmp	$0, %eax
+	jne	use_existing_stack
+
 	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax
 #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
 	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax
 #endif
+	jmp	2f
 	/*
-	 * We don't subject CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
+	 * We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
 	 * already set up. This has the happy side-effect of putting gd in a
 	 * new place separate from SPL, so the memset() in
 	 * board_init_f_init_reserve() does not cause any problems (otherwise
 	 * it would zero out the gd and crash)
 	 */
+	/* Set up memory using the existing stack */
+use_existing_stack:
+	mov	%esp, %eax
+2:
 	call	board_init_f_alloc_reserve
 	mov	%eax, %esp
 
-- 
2.26.0.292.g33ef6b2f38-goog

[RESEND PATCH v3 6/7] x86: Add a way to detect running from coreboot

[Bin Meng]

Hi Simon,

On Thu, Apr 9, 2020 at 2:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> If U-Boot is running from coreboot we need to skip low-level init. Add
> an way to detect this and to set the gd flag.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add new patch to detect running from coreboot
>
> Changes in v2: None
>
>  arch/x86/cpu/i386/cpu.c           | 15 +++++++++++++++
>  arch/x86/include/asm/u-boot-x86.h |  7 +++++++
>  2 files changed, 22 insertions(+)
>
> diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
> index c8da7f10e9b..e43444c090b 100644
> --- a/arch/x86/cpu/i386/cpu.c
> +++ b/arch/x86/cpu/i386/cpu.c
> @@ -447,10 +447,25 @@ int x86_cpu_init_f(void)
>         return 0;
>  }
>
> +bool x86_detect_coreboot(void)
> +{
> +       u32 *ptr, *end;
> +
> +       /* We look for LBIO in the first 4K of RAM */
> +       for (ptr = NULL, end = ptr + 0x400; ptr < end; ptr += 4) {

The logic here is not exactly the same as cb_parse_header(). I believe
we should be consistent.

> +               if (*ptr == 0x4f49424c) /* "LBIO" */
> +                       return true;
> +       }
> +
> +       return false;
> +}
> +
>  int x86_cpu_reinit_f(void)
>  {
>         setup_identity();
>         setup_pci_ram_top();
> +       if (x86_detect_coreboot())
> +               gd->flags |= GD_FLG_NO_LL_INIT;
>
>         return 0;
>  }
> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
> index 3e5d56d0757..654880f91cb 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -43,6 +43,13 @@ int x86_cpu_reinit_f(void);
>   */
>  int x86_cpu_init_tpl(void);
>
> +/**
> + * x86_detect_coreboot() - See if U-Boot is being started from coreboot
> + *
> + * @return true if coreboot is running, false if U-Boot is running 'bare-metal'
> + */
> +bool x86_detect_coreboot(void);
> +
>  int cpu_init_f(void);
>  void setup_gdt(struct global_data *id, u64 *gdt_addr);
>  /*
> --

Regards,
Bin

[RESEND PATCH v3 5/7] board: Add a gd flag for chain loading

[Bin Meng]

Hi Simon,

On Thu, Apr 9, 2020 at 2:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> When U-Boot is run from another boot loader, much of the low-level init
> needs to be skipped.
>
> Add a flag for this and adjust ll_boot_init() to use it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add a new patch with a gd flag for chain loading
>
> Changes in v2: None
>
>  include/asm-generic/global_data.h | 1 +
>  include/init.h                    | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
> index 5d027329fe0..3dc51e49ef7 100644
> --- a/include/asm-generic/global_data.h
> +++ b/include/asm-generic/global_data.h
> @@ -166,5 +166,6 @@ typedef struct global_data {
>  #define GD_FLG_SPL_EARLY_INIT  0x04000 /* Early SPL init is done          */
>  #define GD_FLG_LOG_READY       0x08000 /* Log system is ready for use     */
>  #define GD_FLG_WDT_READY       0x10000 /* Watchdog is ready for use       */
> +#define GD_FLG_NO_LL_INIT      0x20000 /* Don't perform low-level init    */

How about GD_FLG_SKIP_LL_INIT ?

>
>  #endif /* __ASM_GENERIC_GBL_DATA_H */
> diff --git a/include/init.h b/include/init.h
> index 2a33a3fd1e4..64fdf124916 100644
> --- a/include/init.h
> +++ b/include/init.h
> @@ -20,7 +20,7 @@ struct global_data;
>  #ifdef CONFIG_EFI_STUB
>  #define ll_boot_init() false
>  #else
> -#define ll_boot_init() true
> +#define ll_boot_init() (!(gd->flags & GD_FLG_NO_LL_INIT))
>  #endif

Regards,
Bin

[RESEND PATCH v3 0/7] x86: Improve support for chain-loading U-Boot

[Bin Meng]

Hi Simon,

On Thu, Apr 9, 2020 at 2:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This little series adds a few checks into the code to allow better
> operation when booting a build from a previous-state loader such as
> coreboot.
>
> At present we have a 'coreboot' target but this runs very different code
> from the bare-metal targets, such as coral. There is very little in common
> between them.
>
> It is useful to be able to boot the same U-Boot on a device, with or
> without a first-stage bootloader. For example, with chromebook_coral, it
> is helpful for testing to be able to boot the same U-Boot (complete with
> FSP) on bare metal and from coreboot. It allows checking of things like
> CPU speed, comparing registers, ACPI tables and the like.
>
> This series allows U-Boot to detect that it ran from coreboot and
> automatically do the right thing.
>
> This series makes the most important changes to allow the same u-boot.bin
> for coral to boot after coreboot (by itself) or bare metal (via TPL->SPL).
>
> Changes in v3:
> - Add a new patch with a gd flag for chain loading
> - Add new patch to detect running from coreboot

Sorry it took me some time to have a look at this series. I have some
comments against 5 & 6.

Could you please update doc/arch/x86.rst for the purpose and usage of
the chain loading?

Regards,
Bin

[RESEND PATCH v3 5/7] board: Add a gd flag for chain loading

[Bin Meng]

Hi Simon,


On Thu, Apr 23, 2020 at 7:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Thu, Apr 9, 2020 at 2:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > When U-Boot is run from another boot loader, much of the low-level init
> > needs to be skipped.
> >
> > Add a flag for this and adjust ll_boot_init() to use it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3:
> > - Add a new patch with a gd flag for chain loading
> >
> > Changes in v2: None
> >
> >  include/asm-generic/global_data.h | 1 +
> >  include/init.h                    | 2 +-
> >  2 files changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
> > index 5d027329fe0..3dc51e49ef7 100644
> > --- a/include/asm-generic/global_data.h
> > +++ b/include/asm-generic/global_data.h
> > @@ -166,5 +166,6 @@ typedef struct global_data {
> >  #define GD_FLG_SPL_EARLY_INIT  0x04000 /* Early SPL init is done          */
> >  #define GD_FLG_LOG_READY       0x08000 /* Log system is ready for use     */
> >  #define GD_FLG_WDT_READY       0x10000 /* Watchdog is ready for use       */
> > +#define GD_FLG_NO_LL_INIT      0x20000 /* Don't perform low-level init    */
>
> How about GD_FLG_SKIP_LL_INIT ?

Just noticed that there is an ad-hoc config macro (not converted to
Kconfig yet) CONFIG_SKIP_LOWLEVEL_INIT.

I suspect we can do some clean up and consolidation here ?

>
> >
> >  #endif /* __ASM_GENERIC_GBL_DATA_H */
> > diff --git a/include/init.h b/include/init.h
> > index 2a33a3fd1e4..64fdf124916 100644
> > --- a/include/init.h
> > +++ b/include/init.h
> > @@ -20,7 +20,7 @@ struct global_data;
> >  #ifdef CONFIG_EFI_STUB
> >  #define ll_boot_init() false
> >  #else
> > -#define ll_boot_init() true
> > +#define ll_boot_init() (!(gd->flags & GD_FLG_NO_LL_INIT))
> >  #endif

Regards,
Bin

[RESEND PATCH v3 5/7] board: Add a gd flag for chain loading

[Simon Glass]

Hi Bin,

On Thu, 23 Apr 2020 at 08:00, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
>
> On Thu, Apr 23, 2020 at 7:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Thu, Apr 9, 2020 at 2:58 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > When U-Boot is run from another boot loader, much of the low-level init
> > > needs to be skipped.
> > >
> > > Add a flag for this and adjust ll_boot_init() to use it.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > Changes in v3:
> > > - Add a new patch with a gd flag for chain loading
> > >
> > > Changes in v2: None
> > >
> > >  include/asm-generic/global_data.h | 1 +
> > >  include/init.h                    | 2 +-
> > >  2 files changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
> > > index 5d027329fe0..3dc51e49ef7 100644
> > > --- a/include/asm-generic/global_data.h
> > > +++ b/include/asm-generic/global_data.h
> > > @@ -166,5 +166,6 @@ typedef struct global_data {
> > >  #define GD_FLG_SPL_EARLY_INIT  0x04000 /* Early SPL init is done          */
> > >  #define GD_FLG_LOG_READY       0x08000 /* Log system is ready for use     */
> > >  #define GD_FLG_WDT_READY       0x10000 /* Watchdog is ready for use       */
> > > +#define GD_FLG_NO_LL_INIT      0x20000 /* Don't perform low-level init    */
> >
> > How about GD_FLG_SKIP_LL_INIT ?
>
> Just noticed that there is an ad-hoc config macro (not converted to
> Kconfig yet) CONFIG_SKIP_LOWLEVEL_INIT.

OK

>
> I suspect we can do some clean up and consolidation here ?

Yes this is quite similar. I agree some clean-up could be done here.
But that option has many build-time effects. I suspect it would be
possible to remove those and do it all at runtime, but it would be a
fair bit of work to do it for all these boards.

[..]

Regards,
Simon