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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id r3sm12797798wrm.35.2020.04.12.14.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2020 14:29:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.0? 3/3] hw/openrisc/pic_cpu: Use qdev gpio rather than qemu_allocate_irqs() Date: Sun, 12 Apr 2020 23:29:43 +0200 Message-Id: <20200412212943.4117-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200412212943.4117-1-f4bug@amsat.org> References: <20200412212943.4117-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Stafford Horne , John Snow , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Switch to using the qdev gpio API which is preferred over qemu_allocate_irqs(). Doing so we also stop leaking the allocated memory. One step to eventually deprecate and remove qemu_allocate_irqs() one day. Patch created mechanically using spatch with this script inspired from commit d6ef883d9d7: @@ typedef qemu_irq; identifier irqs, handler; expression opaque, count, i; @@ - qemu_irq *irqs; ... - irqs = qemu_allocate_irqs(handler, opaque, count); + qdev_init_gpio_in(DEVICE(opaque), handler, count); <+... - irqs[i] + qdev_get_gpio_in(DEVICE(opaque), i) ...+> ?- g_free(irqs); Inspired-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/openrisc/pic_cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index 36f9350830..4b0c92f842 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -52,10 +52,9 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) void cpu_openrisc_pic_init(OpenRISCCPU *cpu) { int i; - qemu_irq *qi; - qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS); + qdev_init_gpio_in(DEVICE(cpu), openrisc_pic_cpu_handler, NR_IRQS); for (i = 0; i < NR_IRQS; i++) { - cpu->env.irq[i] = qi[i]; + cpu->env.irq[i] = qdev_get_gpio_in(DEVICE(cpu), i); } } -- 2.21.1