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* [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+
@ 2020-04-14 20:57 Matt Roper
  2020-04-14 22:28 ` Souza, Jose
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Matt Roper @ 2020-04-14 20:57 UTC (permalink / raw)
  To: intel-gfx

AUX power wells sometimes need additional handling besides just
programming the specific power well registers:
 * Type-C PHY's also require additional Type-C register programming
 * ICL combo PHY's require additional workarounds
 * TGL & EHL combo PHY's can be treated like any other power well

Today we have dedicated aux ops for the ICL combo PHY and Type-C cases.
This works fine, but means that when a new platform shows up with
identical general power well handling, but different types of PHYs on
its outputs, we have to define an entire new power well table for that
platform and can't just re-use the table from the earlier platform -- as
an example, see ehl_power_wells[], which is a subset of
icl_power_wells[], *except* that we need to specify different AUX ops
for the third display.

If we instead create a single set of top-level aux ops that will check
the PHY type and then dispatch to the appropriate handlers, we can get
more reuse out of our power well definitions.  This allows us to
immediately eliminate ehl_power_wells[] and simply reuse the ICL table;
if future platforms follow the same general power well assignments as
either ICL or TGL, we'll be able to re-use those tables in the same way.

Note that I've only changed ICL+ platforms over to using the new icl_aux
ops; at this point it's unlikely that we'll have any new platforms that
re-use gen9 or earlier power well configurations.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 242 +++++-------------
 1 file changed, 60 insertions(+), 182 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..ddeaa475b8a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -593,6 +593,38 @@ icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
 	hsw_power_well_disable(dev_priv, power_well);
 }
 
+static void
+icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
+			  struct i915_power_well *power_well)
+{
+	int pw_idx = power_well->desc->hsw.idx;
+	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
+
+	if (intel_phy_is_tc(dev_priv, phy))
+		return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
+	else if (IS_ICELAKE(dev_priv))
+		return icl_combo_phy_aux_power_well_enable(dev_priv,
+							   power_well);
+	else
+		return hsw_power_well_enable(dev_priv, power_well);
+}
+
+static void
+icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
+			   struct i915_power_well *power_well)
+{
+	int pw_idx = power_well->desc->hsw.idx;
+	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
+
+	if (intel_phy_is_tc(dev_priv, phy))
+		return icl_tc_phy_aux_power_well_disable(dev_priv, power_well);
+	else if (IS_ICELAKE(dev_priv))
+		return icl_combo_phy_aux_power_well_disable(dev_priv,
+							    power_well);
+	else
+		return hsw_power_well_disable(dev_priv, power_well);
+}
+
 /*
  * We should only use the power well if we explicitly asked the hardware to
  * enable it, so check if it's enabled and also check if we've requested it to
@@ -3503,17 +3535,10 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
 	},
 };
 
-static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
+static const struct i915_power_well_ops icl_aux_power_well_ops = {
 	.sync_hw = hsw_power_well_sync_hw,
-	.enable = icl_combo_phy_aux_power_well_enable,
-	.disable = icl_combo_phy_aux_power_well_disable,
-	.is_enabled = hsw_power_well_enabled,
-};
-
-static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
-	.sync_hw = hsw_power_well_sync_hw,
-	.enable = icl_tc_phy_aux_power_well_enable,
-	.disable = icl_tc_phy_aux_power_well_disable,
+	.enable = icl_aux_power_well_enable,
+	.disable = icl_aux_power_well_disable,
 	.is_enabled = hsw_power_well_enabled,
 };
 
@@ -3643,7 +3668,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX A",
 		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
-		.ops = &icl_combo_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3653,7 +3678,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX B",
 		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
-		.ops = &icl_combo_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3663,7 +3688,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX C TC1",
 		.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3674,7 +3699,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX D TC2",
 		.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3685,7 +3710,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX E TC3",
 		.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3696,7 +3721,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX F TC4",
 		.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3707,7 +3732,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX C TBT1",
 		.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3718,7 +3743,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX D TBT2",
 		.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3729,7 +3754,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX E TBT3",
 		.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3740,7 +3765,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "AUX F TBT4",
 		.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -3762,151 +3787,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	},
 };
 
-static const struct i915_power_well_desc ehl_power_wells[] = {
-	{
-		.name = "always-on",
-		.always_on = true,
-		.domains = POWER_DOMAIN_MASK,
-		.ops = &i9xx_always_on_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-	},
-	{
-		.name = "power well 1",
-		/* Handled by the DMC firmware */
-		.always_on = true,
-		.domains = 0,
-		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_1,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
-			.hsw.has_fuses = true,
-		},
-	},
-	{
-		.name = "DC off",
-		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
-		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_DC_OFF,
-	},
-	{
-		.name = "power well 2",
-		.domains = ICL_PW_2_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_2,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
-			.hsw.has_fuses = true,
-		},
-	},
-	{
-		.name = "power well 3",
-		.domains = ICL_PW_3_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
-			.hsw.irq_pipe_mask = BIT(PIPE_B),
-			.hsw.has_vga = true,
-			.hsw.has_fuses = true,
-		},
-	},
-	{
-		.name = "DDI A IO",
-		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_ddi_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
-		},
-	},
-	{
-		.name = "DDI B IO",
-		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_ddi_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
-		},
-	},
-	{
-		.name = "DDI C IO",
-		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_ddi_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
-		},
-	},
-	{
-		.name = "DDI D IO",
-		.domains = ICL_DDI_IO_D_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_ddi_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
-		},
-	},
-	{
-		.name = "AUX A",
-		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_aux_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
-		},
-	},
-	{
-		.name = "AUX B",
-		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_aux_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
-		},
-	},
-	{
-		.name = "AUX C",
-		.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_aux_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
-		},
-	},
-	{
-		.name = "AUX D",
-		.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &icl_aux_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
-		},
-	},
-	{
-		.name = "power well 4",
-		.domains = ICL_PW_4_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
-			.hsw.has_fuses = true,
-			.hsw.irq_pipe_mask = BIT(PIPE_C),
-		},
-	},
-};
-
 static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "always-on",
@@ -4051,7 +3931,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX A",
 		.domains = TGL_AUX_A_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4061,7 +3941,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX B",
 		.domains = TGL_AUX_B_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4071,7 +3951,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX C",
 		.domains = TGL_AUX_C_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4081,7 +3961,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX D TC1",
 		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4092,7 +3972,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX E TC2",
 		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4103,7 +3983,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX F TC3",
 		.domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4114,7 +3994,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX G TC4",
 		.domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4125,7 +4005,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX H TC5",
 		.domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4136,7 +4016,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX I TC6",
 		.domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
-		.ops = &icl_tc_phy_aux_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4147,7 +4027,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX D TBT1",
 		.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4158,7 +4038,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX E TBT2",
 		.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4169,7 +4049,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX F TBT3",
 		.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4180,7 +4060,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX G TBT4",
 		.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4191,7 +4071,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX H TBT5",
 		.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4202,7 +4082,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "AUX I TBT6",
 		.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
+		.ops = &icl_aux_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,
@@ -4383,8 +4263,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 */
 	if (IS_GEN(dev_priv, 12)) {
 		err = set_power_wells(power_domains, tgl_power_wells);
-	} else if (IS_ELKHARTLAKE(dev_priv)) {
-		err = set_power_wells(power_domains, ehl_power_wells);
 	} else if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+
  2020-04-14 20:57 [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+ Matt Roper
@ 2020-04-14 22:28 ` Souza, Jose
  2020-04-15  2:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Souza, Jose @ 2020-04-14 22:28 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Tue, 2020-04-14 at 13:57 -0700, Matt Roper wrote:
> AUX power wells sometimes need additional handling besides just
> programming the specific power well registers:
>  * Type-C PHY's also require additional Type-C register programming
>  * ICL combo PHY's require additional workarounds
>  * TGL & EHL combo PHY's can be treated like any other power well
> 
> Today we have dedicated aux ops for the ICL combo PHY and Type-C
> cases.
> This works fine, but means that when a new platform shows up with
> identical general power well handling, but different types of PHYs on
> its outputs, we have to define an entire new power well table for
> that
> platform and can't just re-use the table from the earlier platform --
> as
> an example, see ehl_power_wells[], which is a subset of
> icl_power_wells[], *except* that we need to specify different AUX ops
> for the third display.
> 
> If we instead create a single set of top-level aux ops that will
> check
> the PHY type and then dispatch to the appropriate handlers, we can
> get
> more reuse out of our power well definitions.  This allows us to
> immediately eliminate ehl_power_wells[] and simply reuse the ICL
> table;
> if future platforms follow the same general power well assignments as
> either ICL or TGL, we'll be able to re-use those tables in the same
> way.
> 
> Note that I've only changed ICL+ platforms over to using the new
> icl_aux
> ops; at this point it's unlikely that we'll have any new platforms
> that
> re-use gen9 or earlier power well configurations.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 242 +++++-----------
> --
>  1 file changed, 60 insertions(+), 182 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 433e5a81dd4d..ddeaa475b8a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -593,6 +593,38 @@ icl_tc_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
>  	hsw_power_well_disable(dev_priv, power_well);
>  }
>  
> +static void
> +icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
> +			  struct i915_power_well *power_well)
> +{
> +	int pw_idx = power_well->desc->hsw.idx;
> +	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> +

The above will not work for TBT aux powerwells.

Other than that looks a good idea.

> +	if (intel_phy_is_tc(dev_priv, phy))
> +		return icl_tc_phy_aux_power_well_enable(dev_priv, 
> power_well);
> +	else if (IS_ICELAKE(dev_priv))
> +		return icl_combo_phy_aux_power_well_enable(dev_priv,
> +							   power_well);
> +	else
> +		return hsw_power_well_enable(dev_priv, power_well);
> +}
> +
> +static void
> +icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
> +			   struct i915_power_well *power_well)
> +{
> +	int pw_idx = power_well->desc->hsw.idx;
> +	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> +
> +	if (intel_phy_is_tc(dev_priv, phy))
> +		return icl_tc_phy_aux_power_well_disable(dev_priv,
> power_well);
> +	else if (IS_ICELAKE(dev_priv))
> +		return icl_combo_phy_aux_power_well_disable(dev_priv,
> +							    power_well)
> ;
> +	else
> +		return hsw_power_well_disable(dev_priv, power_well);
> +}
> +
>  /*
>   * We should only use the power well if we explicitly asked the
> hardware to
>   * enable it, so check if it's enabled and also check if we've
> requested it to
> @@ -3503,17 +3535,10 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
>  	},
>  };
>  
> -static const struct i915_power_well_ops
> icl_combo_phy_aux_power_well_ops = {
> +static const struct i915_power_well_ops icl_aux_power_well_ops = {
>  	.sync_hw = hsw_power_well_sync_hw,
> -	.enable = icl_combo_phy_aux_power_well_enable,
> -	.disable = icl_combo_phy_aux_power_well_disable,
> -	.is_enabled = hsw_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops
> icl_tc_phy_aux_power_well_ops = {
> -	.sync_hw = hsw_power_well_sync_hw,
> -	.enable = icl_tc_phy_aux_power_well_enable,
> -	.disable = icl_tc_phy_aux_power_well_disable,
> +	.enable = icl_aux_power_well_enable,
> +	.disable = icl_aux_power_well_disable,
>  	.is_enabled = hsw_power_well_enabled,
>  };
>  
> @@ -3643,7 +3668,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX A",
>  		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> -		.ops = &icl_combo_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3653,7 +3678,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX B",
>  		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> -		.ops = &icl_combo_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3663,7 +3688,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX C TC1",
>  		.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3674,7 +3699,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX D TC2",
>  		.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3685,7 +3710,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX E TC3",
>  		.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3696,7 +3721,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX F TC4",
>  		.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3707,7 +3732,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX C TBT1",
>  		.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3718,7 +3743,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX D TBT2",
>  		.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3729,7 +3754,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX E TBT3",
>  		.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3740,7 +3765,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	{
>  		.name = "AUX F TBT4",
>  		.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -3762,151 +3787,6 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
>  	},
>  };
>  
> -static const struct i915_power_well_desc ehl_power_wells[] = {
> -	{
> -		.name = "always-on",
> -		.always_on = true,
> -		.domains = POWER_DOMAIN_MASK,
> -		.ops = &i9xx_always_on_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -	},
> -	{
> -		.name = "power well 1",
> -		/* Handled by the DMC firmware */
> -		.always_on = true,
> -		.domains = 0,
> -		.ops = &hsw_power_well_ops,
> -		.id = SKL_DISP_PW_1,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> -			.hsw.has_fuses = true,
> -		},
> -	},
> -	{
> -		.name = "DC off",
> -		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> -		.ops = &gen9_dc_off_power_well_ops,
> -		.id = SKL_DISP_DC_OFF,
> -	},
> -	{
> -		.name = "power well 2",
> -		.domains = ICL_PW_2_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = SKL_DISP_PW_2,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
> -			.hsw.has_fuses = true,
> -		},
> -	},
> -	{
> -		.name = "power well 3",
> -		.domains = ICL_PW_3_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> -			.hsw.irq_pipe_mask = BIT(PIPE_B),
> -			.hsw.has_vga = true,
> -			.hsw.has_fuses = true,
> -		},
> -	},
> -	{
> -		.name = "DDI A IO",
> -		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_ddi_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> -		},
> -	},
> -	{
> -		.name = "DDI B IO",
> -		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_ddi_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> -		},
> -	},
> -	{
> -		.name = "DDI C IO",
> -		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_ddi_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> -		},
> -	},
> -	{
> -		.name = "DDI D IO",
> -		.domains = ICL_DDI_IO_D_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_ddi_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
> -		},
> -	},
> -	{
> -		.name = "AUX A",
> -		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_aux_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> -		},
> -	},
> -	{
> -		.name = "AUX B",
> -		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_aux_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> -		},
> -	},
> -	{
> -		.name = "AUX C",
> -		.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_aux_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> -		},
> -	},
> -	{
> -		.name = "AUX D",
> -		.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &icl_aux_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
> -		},
> -	},
> -	{
> -		.name = "power well 4",
> -		.domains = ICL_PW_4_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> -			.hsw.has_fuses = true,
> -			.hsw.irq_pipe_mask = BIT(PIPE_C),
> -		},
> -	},
> -};
> -
>  static const struct i915_power_well_desc tgl_power_wells[] = {
>  	{
>  		.name = "always-on",
> @@ -4051,7 +3931,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX A",
>  		.domains = TGL_AUX_A_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4061,7 +3941,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX B",
>  		.domains = TGL_AUX_B_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4071,7 +3951,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX C",
>  		.domains = TGL_AUX_C_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4081,7 +3961,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX D TC1",
>  		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4092,7 +3972,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX E TC2",
>  		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4103,7 +3983,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX F TC3",
>  		.domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4114,7 +3994,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX G TC4",
>  		.domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4125,7 +4005,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX H TC5",
>  		.domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4136,7 +4016,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX I TC6",
>  		.domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
> -		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4147,7 +4027,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX D TBT1",
>  		.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4158,7 +4038,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX E TBT2",
>  		.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4169,7 +4049,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX F TBT3",
>  		.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4180,7 +4060,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX G TBT4",
>  		.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4191,7 +4071,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX H TBT5",
>  		.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4202,7 +4082,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  	{
>  		.name = "AUX I TBT6",
>  		.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> +		.ops = &icl_aux_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
>  			.hsw.regs = &icl_aux_power_well_regs,
> @@ -4383,8 +4263,6 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
>  	 */
>  	if (IS_GEN(dev_priv, 12)) {
>  		err = set_power_wells(power_domains, tgl_power_wells);
> -	} else if (IS_ELKHARTLAKE(dev_priv)) {
> -		err = set_power_wells(power_domains, ehl_power_wells);
>  	} else if (IS_GEN(dev_priv, 11)) {
>  		err = set_power_wells(power_domains, icl_power_wells);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Use single set of AUX powerwell ops for gen11+
  2020-04-14 20:57 [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+ Matt Roper
  2020-04-14 22:28 ` Souza, Jose
@ 2020-04-15  2:35 ` Patchwork
  2020-04-15  2:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2020-04-15 21:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-04-15  2:35 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Use single set of AUX powerwell ops for gen11+
URL   : https://patchwork.freedesktop.org/series/75943/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use single set of AUX powerwell ops for gen11+
  2020-04-14 20:57 [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+ Matt Roper
  2020-04-14 22:28 ` Souza, Jose
  2020-04-15  2:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
@ 2020-04-15  2:42 ` Patchwork
  2020-04-15 21:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-04-15  2:42 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Use single set of AUX powerwell ops for gen11+
URL   : https://patchwork.freedesktop.org/series/75943/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8298 -> Patchwork_17301
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/index.html

Known issues
------------

  Here are the changes found in Patchwork_17301 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@sanitycheck:
    - fi-bwr-2160:        [PASS][1] -> [INCOMPLETE][2] ([i915#489])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-cml-u2:          [PASS][3] -> [DMESG-WARN][4] ([IGT#4])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
  [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489


Participating hosts (48 -> 44)
------------------------------

  Missing    (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8298 -> Patchwork_17301

  CI-20190529: 20190529
  CI_DRM_8298: 17f82f0c2857d0b442adbdb62eb44b61d0f5b775 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17301: 9df67892b530cc90426bd404c750a6e3f2e96f40 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9df67892b530 drm/i915: Use single set of AUX powerwell ops for gen11+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use single set of AUX powerwell ops for gen11+
  2020-04-14 20:57 [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+ Matt Roper
                   ` (2 preceding siblings ...)
  2020-04-15  2:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-15 21:39 ` Patchwork
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-04-15 21:39 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Use single set of AUX powerwell ops for gen11+
URL   : https://patchwork.freedesktop.org/series/75943/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17301_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17301_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17301_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17301_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_dp_aux_dev:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb5/igt@kms_dp_aux_dev.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb8/igt@kms_dp_aux_dev.html

  
New tests
---------

  New tests have been introduced between CI_DRM_8298_full and Patchwork_17301_full:

### New IGT tests (27) ###

  * igt@kms_plane_cursor@pipe-a-overlay-size-128:
    - Statuses : 8 pass(s)
    - Exec time: [1.66, 3.69] s

  * igt@kms_plane_cursor@pipe-a-overlay-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [1.65, 3.65] s

  * igt@kms_plane_cursor@pipe-a-overlay-size-64:
    - Statuses : 8 pass(s)
    - Exec time: [1.65, 3.66] s

  * igt@kms_plane_cursor@pipe-a-primary-size-128:
    - Statuses : 8 pass(s)
    - Exec time: [1.63, 3.48] s

  * igt@kms_plane_cursor@pipe-a-primary-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [1.63, 3.40] s

  * igt@kms_plane_cursor@pipe-a-primary-size-64:
    - Statuses : 7 pass(s)
    - Exec time: [1.63, 2.59] s

  * igt@kms_plane_cursor@pipe-a-viewport-size-128:
    - Statuses : 8 pass(s)
    - Exec time: [1.65, 3.68] s

  * igt@kms_plane_cursor@pipe-a-viewport-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [1.64, 3.67] s

  * igt@kms_plane_cursor@pipe-a-viewport-size-64:
    - Statuses : 8 pass(s)
    - Exec time: [1.64, 3.68] s

  * igt@kms_plane_cursor@pipe-b-overlay-size-128:
    - Statuses : 8 pass(s)
    - Exec time: [2.22, 4.90] s

  * igt@kms_plane_cursor@pipe-b-overlay-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [2.22, 4.83] s

  * igt@kms_plane_cursor@pipe-b-overlay-size-64:
    - Statuses : 8 pass(s)
    - Exec time: [2.22, 4.85] s

  * igt@kms_plane_cursor@pipe-b-primary-size-128:
    - Statuses : 8 pass(s)
    - Exec time: [2.21, 4.66] s

  * igt@kms_plane_cursor@pipe-b-primary-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [2.21, 4.61] s

  * igt@kms_plane_cursor@pipe-b-primary-size-64:
    - Statuses : 8 pass(s)
    - Exec time: [2.20, 4.60] s

  * igt@kms_plane_cursor@pipe-b-viewport-size-128:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_plane_cursor@pipe-b-viewport-size-256:
    - Statuses : 8 pass(s)
    - Exec time: [2.23, 4.84] s

  * igt@kms_plane_cursor@pipe-b-viewport-size-64:
    - Statuses : 8 pass(s)
    - Exec time: [2.26, 4.86] s

  * igt@kms_plane_cursor@pipe-c-overlay-size-128:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.80] s

  * igt@kms_plane_cursor@pipe-c-overlay-size-256:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.89] s

  * igt@kms_plane_cursor@pipe-c-overlay-size-64:
    - Statuses : 6 pass(s) 1 skip(s)
    - Exec time: [0.0, 3.65] s

  * igt@kms_plane_cursor@pipe-c-primary-size-128:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.66] s

  * igt@kms_plane_cursor@pipe-c-primary-size-256:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.57] s

  * igt@kms_plane_cursor@pipe-c-primary-size-64:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.64] s

  * igt@kms_plane_cursor@pipe-c-viewport-size-128:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.89] s

  * igt@kms_plane_cursor@pipe-c-viewport-size-256:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.89] s

  * igt@kms_plane_cursor@pipe-c-viewport-size-64:
    - Statuses : 7 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.83] s

  

Known issues
------------

  Here are the changes found in Patchwork_17301_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4] ([i915#189])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb1/igt@i915_pm_rpm@i2c.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb7/igt@i915_pm_rpm@i2c.html

  * igt@i915_selftest@live@active:
    - shard-glk:          [PASS][5] -> [DMESG-FAIL][6] ([i915#666] / [i915#765])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk8/igt@i915_selftest@live@active.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-glk5/igt@i915_selftest@live@active.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +4 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl2/igt@i915_suspend@forcewake.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-kbl7/igt@i915_suspend@forcewake.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl1/igt@i915_suspend@sysfs-reader.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-apl4/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_legacy@all-pipes-torture-bo:
    - shard-hsw:          [PASS][11] -> [DMESG-WARN][12] ([i915#128])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw6/igt@kms_cursor_legacy@all-pipes-torture-bo.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-hsw7/igt@kms_cursor_legacy@all-pipes-torture-bo.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-glk1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#34])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#79])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-glk1/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#34])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#31])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-skl4/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * {igt@gem_wait@write-wait@all}:
    - shard-skl:          [FAIL][25] ([i915#1676]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl2/igt@gem_wait@write-wait@all.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-skl4/igt@gem_wait@write-wait@all.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][27] ([i915#716]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl3/igt@gen9_exec_parse@allowed-all.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][29] ([i915#79]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][33] ([fdo#109441]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb8/igt@kms_psr@psr2_basic.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb2/igt@kms_psr@psr2_basic.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][35] ([i915#31]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl4/igt@kms_setmode@basic.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-kbl6/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-kbl:          [FAIL][39] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) -> [FAIL][40] ([fdo#108145] / [i915#265])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
    - shard-apl:          [FAIL][41] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][42] ([fdo#108145] / [i915#265])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][43], [FAIL][44]) ([i915#1423] / [i915#716]) -> [FAIL][45] ([i915#1423])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl3/igt@runner@aborted.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl3/igt@runner@aborted.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-apl2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#1423]: https://gitlab.freedesktop.org/drm/intel/issues/1423
  [i915#1676]: https://gitlab.freedesktop.org/drm/intel/issues/1676
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8298 -> Patchwork_17301

  CI-20190529: 20190529
  CI_DRM_8298: 17f82f0c2857d0b442adbdb62eb44b61d0f5b775 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17301: 9df67892b530cc90426bd404c750a6e3f2e96f40 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2020-04-15 21:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-14 20:57 [Intel-gfx] [PATCH] drm/i915: Use single set of AUX powerwell ops for gen11+ Matt Roper
2020-04-14 22:28 ` Souza, Jose
2020-04-15  2:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
2020-04-15  2:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-15 21:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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