From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34731C38A29 for ; Tue, 14 Apr 2020 23:10:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 094E92054F for ; Tue, 14 Apr 2020 23:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586905812; bh=0Hgn3rozHbgSBMN0uA0qJTwL82xs0UurswWtNLVM4Pw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=R2MaZaCldGb48KRHGB1XMg1byMJ1qpzLVOvIxe/TStPM44N9OpoOz9jEo/wHq3CSe rEzCpnou4Qx5OKMjk0aa7Z2k3J1qB+ujRLjxIVTfQcCdEKrzmd/AfDlW6ML8dxPKEt XzJJ+NyLbz3BjcRQXtYR/Woyd9K/UC8rJW4XOWxU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2441012AbgDNXKL (ORCPT ); Tue, 14 Apr 2020 19:10:11 -0400 Received: from mail-oi1-f196.google.com ([209.85.167.196]:34402 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731377AbgDNXKJ (ORCPT ); Tue, 14 Apr 2020 19:10:09 -0400 Received: by mail-oi1-f196.google.com with SMTP id x10so2558912oie.1; Tue, 14 Apr 2020 16:10:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=nnA+hiteX7SC+b7tbnuixdpiQ4jhYp1NDyyYVqLC8Kk=; b=hiTUlddg9FvQsc7chItOZstOKRAkWUc2OEY3rEzTU1yLtD/5AMu18tebh1ZgemhEn8 ypD+dpSmbACDUK/oXFvKX7prIFD/9JC6K20wk4G22T9MQEzpTRT5SYU6BPQDuKMkmZDD bcM17O4BeAPP+iCHYuQtT5KG+Cxa8MggAA8r2ZxmlqZhT1cLTvKGITn4vjHOgWJpjwr0 3ecaMRt2ip3EX9hgZ3SonYHmldRZTJ8fHbvXyvDfj4A6OP5FUeEQREDYtIElWXZOFBSj qxzTPggJzqaCtXBJS4q0RqUF2GNf6gC/0roRGvYVx4OQGZOCbsTY7scQzf7jDdPdSw6l +kiw== X-Gm-Message-State: AGi0PuZz1hWSBeemmjaACE8DgEnY/a0MT5QaiPosehO0pDSf9oNE0jR2 MPywqRrQ1EgacliOdhL8tg== X-Google-Smtp-Source: APiQypJtzbcIYHC3GUgn2zyO2j2evzOR6eKeQ7eqShmZOkQRjj/3ILyd6wKDsY7XyxDA98fIRmPd5w== X-Received: by 2002:aca:f541:: with SMTP id t62mr2857983oih.148.1586905807549; Tue, 14 Apr 2020 16:10:07 -0700 (PDT) Received: from rob-hp-laptop (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id a131sm5937481oii.30.2020.04.14.16.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 16:10:06 -0700 (PDT) Received: (nullmailer pid 4550 invoked by uid 1000); Tue, 14 Apr 2020 23:10:05 -0000 Date: Tue, 14 Apr 2020 18:10:05 -0500 From: Rob Herring To: Laurent Pinchart Cc: Maxime Ripard , Laurent Pinchart , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Philipp Zabel , Mark Yao , Sandy Huang , Chen-Yu Tsai Subject: Re: [PATCH/RFC 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML Message-ID: <20200414231005.GA24462@bogus> References: <20200405233935.27599-1-laurent.pinchart+renesas@ideasonboard.com> <20200405233935.27599-5-laurent.pinchart+renesas@ideasonboard.com> <20200406080032.zlszhkjqmjeoa4ti@gilmour.lan> <20200406111927.GD4757@pendragon.ideasonboard.com> <20200406170915.x2ztz4q446h6vx2y@gilmour.lan> <20200406175028.GI16885@pendragon.ideasonboard.com> <20200407071251.npibrmzywiyigu2a@gilmour.lan> <20200408114552.GC4881@pendragon.ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200408114552.GC4881@pendragon.ideasonboard.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Apr 08, 2020 at 02:45:52PM +0300, Laurent Pinchart wrote: > Hi Maxime, > > On Tue, Apr 07, 2020 at 09:12:51AM +0200, Maxime Ripard wrote: > > On Mon, Apr 06, 2020 at 08:50:28PM +0300, Laurent Pinchart wrote: > > > On Mon, Apr 06, 2020 at 07:09:15PM +0200, Maxime Ripard wrote: > > > > On Mon, Apr 06, 2020 at 02:19:27PM +0300, Laurent Pinchart wrote: > > > > > On Mon, Apr 06, 2020 at 10:00:32AM +0200, Maxime Ripard wrote: > > > > > > On Mon, Apr 06, 2020 at 02:39:33AM +0300, Laurent Pinchart wrote: > > > > > > > Convert the Rockchip HDMI TX text binding to YAML. > > > > > > > > > > > > > > Signed-off-by: Laurent Pinchart > > > > > > > --- > > > > > > > .../display/rockchip/dw_hdmi-rockchip.txt | 74 -------- > > > > > > > .../display/rockchip/rockchip,dw-hdmi.yaml | 178 ++++++++++++++++++ > > > > > > > 2 files changed, 178 insertions(+), 74 deletions(-) > > > > > > > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > deleted file mode 100644 > > > > > > > index 3d32ce137e7f..000000000000 > > > > > > > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > +++ /dev/null > > > > > > > @@ -1,74 +0,0 @@ > > > > > > > -Rockchip DWC HDMI TX Encoder > > > > > > > -============================ > > > > > > > - > > > > > > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > > > > > > -with a companion PHY IP. > > > > > > > - > > > > > > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in > > > > > > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the > > > > > > > -following device-specific properties. > > > > > > > - > > > > > > > - > > > > > > > -Required properties: > > > > > > > - > > > > > > > -- compatible: should be one of the following: > > > > > > > - "rockchip,rk3228-dw-hdmi" > > > > > > > - "rockchip,rk3288-dw-hdmi" > > > > > > > - "rockchip,rk3328-dw-hdmi" > > > > > > > - "rockchip,rk3399-dw-hdmi" > > > > > > > -- reg: See dw_hdmi.txt. > > > > > > > -- reg-io-width: See dw_hdmi.txt. Shall be 4. > > > > > > > -- interrupts: HDMI interrupt number > > > > > > > -- clocks: See dw_hdmi.txt. > > > > > > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. > > > > > > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 > > > > > > > - corresponding to the video input of the controller. The port shall have two > > > > > > > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. > > > > > > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. > > > > > > > - > > > > > > > -Optional properties > > > > > > > - > > > > > > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master > > > > > > > - or the functionally-reduced I2C master contained in the DWC HDMI. When > > > > > > > - connected to a system I2C master this property contains a phandle to that > > > > > > > - I2C master controller. > > > > > > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. > > > > > > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt. > > > > > > > -- clock-names: May contain "grf", power for grf io. > > > > > > > -- clock-names: May contain "vpll", external clock for some hdmi phy. > > > > > > > -- phys: from general PHY binding: the phandle for the PHY device. > > > > > > > -- phy-names: Should be "hdmi" if phys references an external phy. > > > > > > > - > > > > > > > -Optional pinctrl entry: > > > > > > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi > > > > > > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an > > > > > > > - i2c timeout. It's intended that this unwedge pinctrl entry will > > > > > > > - cause the SDA line to be driven low to work around a hardware > > > > > > > - errata. > > > > > > > - > > > > > > > -Example: > > > > > > > - > > > > > > > -hdmi: hdmi@ff980000 { > > > > > > > - compatible = "rockchip,rk3288-dw-hdmi"; > > > > > > > - reg = <0xff980000 0x20000>; > > > > > > > - reg-io-width = <4>; > > > > > > > - ddc-i2c-bus = <&i2c5>; > > > > > > > - rockchip,grf = <&grf>; > > > > > > > - interrupts = ; > > > > > > > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; > > > > > > > - clock-names = "iahb", "isfr"; > > > > > > > - ports { > > > > > > > - hdmi_in: port { > > > > > > > - #address-cells = <1>; > > > > > > > - #size-cells = <0>; > > > > > > > - hdmi_in_vopb: endpoint@0 { > > > > > > > - reg = <0>; > > > > > > > - remote-endpoint = <&vopb_out_hdmi>; > > > > > > > - }; > > > > > > > - hdmi_in_vopl: endpoint@1 { > > > > > > > - reg = <1>; > > > > > > > - remote-endpoint = <&vopl_out_hdmi>; > > > > > > > - }; > > > > > > > - }; > > > > > > > - }; > > > > > > > -}; > > > > > > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > new file mode 100644 > > > > > > > index 000000000000..8ff544ae0ac2 > > > > > > > --- /dev/null > > > > > > > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > @@ -0,0 +1,178 @@ > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > +%YAML 1.2 > > > > > > > +--- > > > > > > > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > + > > > > > > > +title: Rockchip DWC HDMI TX Encoder > > > > > > > + > > > > > > > +maintainers: > > > > > > > + - Mark Yao > > > > > > > + > > > > > > > +description: | > > > > > > > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > > > > > > + with a companion PHY IP. > > > > > > > + > > > > > > > +allOf: > > > > > > > + - $ref: ../bridge/synopsys,dw-hdmi.yaml# > > > > > > > + > > > > > > > +properties: > > > > > > > + compatible: > > > > > > > + enum: > > > > > > > + - rockchip,rk3228-dw-hdmi > > > > > > > + - rockchip,rk3288-dw-hdmi > > > > > > > + - rockchip,rk3328-dw-hdmi > > > > > > > + - rockchip,rk3399-dw-hdmi > > > > > > > + > > > > > > > + reg: true > > > > > > > + > > > > > > > + reg-io-width: > > > > > > > + const: 4 > > > > > > > + > > > > > > > + clocks: > > > > > > > + minItems: 2 > > > > > > > + maxItems: 5 > > > > > > > + items: > > > > > > > + - description: The bus clock for either AHB and APB > > > > > > > + - description: The internal register configuration clock > > > > > > > + - description: The HDMI CEC controller main clock > > > > > > > + - description: Power for GRF IO > > > > > > > + - description: External clock for some HDMI PHY > > > > > > > + > > > > > > > + clock-names: > > > > > > > + minItems: 2 > > > > > > > + maxItems: 5 > > > > > > > + items: > > > > > > > + - const: iahb > > > > > > > + - const: isfr > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > > > > > > IIRC Rob wanted us to standardize the order of the clocks if possible, > > > > > > since it's a pain to support properly here, and your description won't > > > > > > match what you describe here either (and in general it's just a best > > > > > > practice), so if all your DTs have the same order you should just set > > > > > > that order in stone. > > > > > > > > > > But how do we handle the case where any of the cec, grf and vpll clocks > > > > > can be set ? Assuming, for instance, that > > > > > > > > > > clock-names = "iahb", "isfr", "cec"; > > > > > clock-names = "iahb", "isfr", "vpll"; > > > > > clock-names = "iahb", "isfr", "cec", "vpll"; > > > > > > > > > > would all be valid. > > > > > > > > It would be painful then... > > > > > > > > The easiest way to do so would be to simply use an enum there, and not > > > > bother checking the array at all. You'll get a warning if there's > > > > multiple occurences of the same string, and I guess that's what you > > > > would be really concerned about. > > > > > > > > However, now that I think about it, what's the interaction between the > > > > generic binding and this one when it comes to the third clock? The > > > > generic one expects it to be cec, and here you have other options? > > > > > > I'm not too familiar with the platform, but as far as I understand, any > > > of the cec, grf and vpll clock is optional (if someone could confirm > > > that, it would be useful). I don't care so much about the order, but > > > iahb and isfr are mandatory, and thus need to be specified as two const > > > items in the beginning as far as I understand. It would be nice to set > > > something along the lines of > > > > > > minItems: 2 > > > maxItems: 5 > > > items: > > > - const: iahb > > > - const: isfr > > > - enum: > > > - cec > > > - grf > > > - vpll > > > > I guess you could do something like: > > > > in the generic schema: > > > > clock-names: > > allOf: > > - minItems: 2 > > - enum: > > - iahb > > - isfr > > - cec > > additonalItems: true > > - items: > > - iahb > > - isfr > > > > Or something along those lines, I haven't tested it, but the basic > > idea is that you want to enforce that: > > a) there's a minimum of two clocks > > b) valid clock names are iahb, isfr and cec, but we will allow more > > c) the first two clocks are iahb and isfr > > Interesting idea. I've tried > > clock-names: > allOf: > - minItems: 2 > - enum: > - iahb > - isfr > - cec > additionalItems: true Instead of these 2, you want: items: enum: [ iahb, isfr, cec ] minItems: 2 maxItems: 3 Though I assume there's some others missing as with this and below, the 3rd clock can only be 'cec'. > - items: > - const: iahb > - const: isfr And this needs 'maxItems: 3' added. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D6FBC2BB1D for ; Tue, 14 Apr 2020 23:10:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB2B32054F for ; Tue, 14 Apr 2020 23:10:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB2B32054F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 340F06E115; Tue, 14 Apr 2020 23:10:09 +0000 (UTC) Received: from mail-oi1-f195.google.com (mail-oi1-f195.google.com [209.85.167.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id 685956E115 for ; Tue, 14 Apr 2020 23:10:08 +0000 (UTC) Received: by mail-oi1-f195.google.com with SMTP id o25so11945472oic.11 for ; Tue, 14 Apr 2020 16:10:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=nnA+hiteX7SC+b7tbnuixdpiQ4jhYp1NDyyYVqLC8Kk=; b=EFWOFNbd3J8WR91H3zDHBLfnAM9GhR5oWDj0Y6CXLt+dDfF9wotv9Y10mSPtLiVMBM DKHanGFjgdbu3TcYkM64A/Q7iuxSQoE3mUhEH6Gn93FnLn/qdaZnHPXTKDKCTK7BWwOD kJSHtSdAWRiiIjH7KEp9f0YnyYNiomBZX6nH/OlFLvQQi1TIUlSWFwTFyJ6HD25vh5Aa HPWr/3gFYKElK3jVdIxQPImWlPzNSy06kTD0sB55W2w442eq6FpLooOw0lNnlUtuq2Kd /IESko1YqpZEFTHfSfu+c91cTllJPSwCEQFIzHFqvSBbh8DYCfUW+pckfzL5hjY6JA8/ h3TQ== X-Gm-Message-State: AGi0PuaA8Nq0TnjU0iOjtVH4tInHaUbUUPAR+TNp7fxNPXfo+lpw+idU SIiOhKFiM+QjM+3PL0TV7w== X-Google-Smtp-Source: APiQypJtzbcIYHC3GUgn2zyO2j2evzOR6eKeQ7eqShmZOkQRjj/3ILyd6wKDsY7XyxDA98fIRmPd5w== X-Received: by 2002:aca:f541:: with SMTP id t62mr2857983oih.148.1586905807549; Tue, 14 Apr 2020 16:10:07 -0700 (PDT) Received: from rob-hp-laptop (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id a131sm5937481oii.30.2020.04.14.16.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 16:10:06 -0700 (PDT) Received: (nullmailer pid 4550 invoked by uid 1000); Tue, 14 Apr 2020 23:10:05 -0000 Date: Tue, 14 Apr 2020 18:10:05 -0500 From: Rob Herring To: Laurent Pinchart Subject: Re: [PATCH/RFC 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML Message-ID: <20200414231005.GA24462@bogus> References: <20200405233935.27599-1-laurent.pinchart+renesas@ideasonboard.com> <20200405233935.27599-5-laurent.pinchart+renesas@ideasonboard.com> <20200406080032.zlszhkjqmjeoa4ti@gilmour.lan> <20200406111927.GD4757@pendragon.ideasonboard.com> <20200406170915.x2ztz4q446h6vx2y@gilmour.lan> <20200406175028.GI16885@pendragon.ideasonboard.com> <20200407071251.npibrmzywiyigu2a@gilmour.lan> <20200408114552.GC4881@pendragon.ideasonboard.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200408114552.GC4881@pendragon.ideasonboard.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Laurent Pinchart , Sandy Huang , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Chen-Yu Tsai , Maxime Ripard , Mark Yao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Apr 08, 2020 at 02:45:52PM +0300, Laurent Pinchart wrote: > Hi Maxime, > > On Tue, Apr 07, 2020 at 09:12:51AM +0200, Maxime Ripard wrote: > > On Mon, Apr 06, 2020 at 08:50:28PM +0300, Laurent Pinchart wrote: > > > On Mon, Apr 06, 2020 at 07:09:15PM +0200, Maxime Ripard wrote: > > > > On Mon, Apr 06, 2020 at 02:19:27PM +0300, Laurent Pinchart wrote: > > > > > On Mon, Apr 06, 2020 at 10:00:32AM +0200, Maxime Ripard wrote: > > > > > > On Mon, Apr 06, 2020 at 02:39:33AM +0300, Laurent Pinchart wrote: > > > > > > > Convert the Rockchip HDMI TX text binding to YAML. > > > > > > > > > > > > > > Signed-off-by: Laurent Pinchart > > > > > > > --- > > > > > > > .../display/rockchip/dw_hdmi-rockchip.txt | 74 -------- > > > > > > > .../display/rockchip/rockchip,dw-hdmi.yaml | 178 ++++++++++++++++++ > > > > > > > 2 files changed, 178 insertions(+), 74 deletions(-) > > > > > > > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > deleted file mode 100644 > > > > > > > index 3d32ce137e7f..000000000000 > > > > > > > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > > > > > > +++ /dev/null > > > > > > > @@ -1,74 +0,0 @@ > > > > > > > -Rockchip DWC HDMI TX Encoder > > > > > > > -============================ > > > > > > > - > > > > > > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > > > > > > -with a companion PHY IP. > > > > > > > - > > > > > > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in > > > > > > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the > > > > > > > -following device-specific properties. > > > > > > > - > > > > > > > - > > > > > > > -Required properties: > > > > > > > - > > > > > > > -- compatible: should be one of the following: > > > > > > > - "rockchip,rk3228-dw-hdmi" > > > > > > > - "rockchip,rk3288-dw-hdmi" > > > > > > > - "rockchip,rk3328-dw-hdmi" > > > > > > > - "rockchip,rk3399-dw-hdmi" > > > > > > > -- reg: See dw_hdmi.txt. > > > > > > > -- reg-io-width: See dw_hdmi.txt. Shall be 4. > > > > > > > -- interrupts: HDMI interrupt number > > > > > > > -- clocks: See dw_hdmi.txt. > > > > > > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. > > > > > > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 > > > > > > > - corresponding to the video input of the controller. The port shall have two > > > > > > > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. > > > > > > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. > > > > > > > - > > > > > > > -Optional properties > > > > > > > - > > > > > > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master > > > > > > > - or the functionally-reduced I2C master contained in the DWC HDMI. When > > > > > > > - connected to a system I2C master this property contains a phandle to that > > > > > > > - I2C master controller. > > > > > > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. > > > > > > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt. > > > > > > > -- clock-names: May contain "grf", power for grf io. > > > > > > > -- clock-names: May contain "vpll", external clock for some hdmi phy. > > > > > > > -- phys: from general PHY binding: the phandle for the PHY device. > > > > > > > -- phy-names: Should be "hdmi" if phys references an external phy. > > > > > > > - > > > > > > > -Optional pinctrl entry: > > > > > > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi > > > > > > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an > > > > > > > - i2c timeout. It's intended that this unwedge pinctrl entry will > > > > > > > - cause the SDA line to be driven low to work around a hardware > > > > > > > - errata. > > > > > > > - > > > > > > > -Example: > > > > > > > - > > > > > > > -hdmi: hdmi@ff980000 { > > > > > > > - compatible = "rockchip,rk3288-dw-hdmi"; > > > > > > > - reg = <0xff980000 0x20000>; > > > > > > > - reg-io-width = <4>; > > > > > > > - ddc-i2c-bus = <&i2c5>; > > > > > > > - rockchip,grf = <&grf>; > > > > > > > - interrupts = ; > > > > > > > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; > > > > > > > - clock-names = "iahb", "isfr"; > > > > > > > - ports { > > > > > > > - hdmi_in: port { > > > > > > > - #address-cells = <1>; > > > > > > > - #size-cells = <0>; > > > > > > > - hdmi_in_vopb: endpoint@0 { > > > > > > > - reg = <0>; > > > > > > > - remote-endpoint = <&vopb_out_hdmi>; > > > > > > > - }; > > > > > > > - hdmi_in_vopl: endpoint@1 { > > > > > > > - reg = <1>; > > > > > > > - remote-endpoint = <&vopl_out_hdmi>; > > > > > > > - }; > > > > > > > - }; > > > > > > > - }; > > > > > > > -}; > > > > > > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > new file mode 100644 > > > > > > > index 000000000000..8ff544ae0ac2 > > > > > > > --- /dev/null > > > > > > > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > > > > @@ -0,0 +1,178 @@ > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > +%YAML 1.2 > > > > > > > +--- > > > > > > > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > + > > > > > > > +title: Rockchip DWC HDMI TX Encoder > > > > > > > + > > > > > > > +maintainers: > > > > > > > + - Mark Yao > > > > > > > + > > > > > > > +description: | > > > > > > > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > > > > > > + with a companion PHY IP. > > > > > > > + > > > > > > > +allOf: > > > > > > > + - $ref: ../bridge/synopsys,dw-hdmi.yaml# > > > > > > > + > > > > > > > +properties: > > > > > > > + compatible: > > > > > > > + enum: > > > > > > > + - rockchip,rk3228-dw-hdmi > > > > > > > + - rockchip,rk3288-dw-hdmi > > > > > > > + - rockchip,rk3328-dw-hdmi > > > > > > > + - rockchip,rk3399-dw-hdmi > > > > > > > + > > > > > > > + reg: true > > > > > > > + > > > > > > > + reg-io-width: > > > > > > > + const: 4 > > > > > > > + > > > > > > > + clocks: > > > > > > > + minItems: 2 > > > > > > > + maxItems: 5 > > > > > > > + items: > > > > > > > + - description: The bus clock for either AHB and APB > > > > > > > + - description: The internal register configuration clock > > > > > > > + - description: The HDMI CEC controller main clock > > > > > > > + - description: Power for GRF IO > > > > > > > + - description: External clock for some HDMI PHY > > > > > > > + > > > > > > > + clock-names: > > > > > > > + minItems: 2 > > > > > > > + maxItems: 5 > > > > > > > + items: > > > > > > > + - const: iahb > > > > > > > + - const: isfr > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > + - enum: > > > > > > > + - cec > > > > > > > + - grf > > > > > > > + - vpll > > > > > > > > > > > > IIRC Rob wanted us to standardize the order of the clocks if possible, > > > > > > since it's a pain to support properly here, and your description won't > > > > > > match what you describe here either (and in general it's just a best > > > > > > practice), so if all your DTs have the same order you should just set > > > > > > that order in stone. > > > > > > > > > > But how do we handle the case where any of the cec, grf and vpll clocks > > > > > can be set ? Assuming, for instance, that > > > > > > > > > > clock-names = "iahb", "isfr", "cec"; > > > > > clock-names = "iahb", "isfr", "vpll"; > > > > > clock-names = "iahb", "isfr", "cec", "vpll"; > > > > > > > > > > would all be valid. > > > > > > > > It would be painful then... > > > > > > > > The easiest way to do so would be to simply use an enum there, and not > > > > bother checking the array at all. You'll get a warning if there's > > > > multiple occurences of the same string, and I guess that's what you > > > > would be really concerned about. > > > > > > > > However, now that I think about it, what's the interaction between the > > > > generic binding and this one when it comes to the third clock? The > > > > generic one expects it to be cec, and here you have other options? > > > > > > I'm not too familiar with the platform, but as far as I understand, any > > > of the cec, grf and vpll clock is optional (if someone could confirm > > > that, it would be useful). I don't care so much about the order, but > > > iahb and isfr are mandatory, and thus need to be specified as two const > > > items in the beginning as far as I understand. It would be nice to set > > > something along the lines of > > > > > > minItems: 2 > > > maxItems: 5 > > > items: > > > - const: iahb > > > - const: isfr > > > - enum: > > > - cec > > > - grf > > > - vpll > > > > I guess you could do something like: > > > > in the generic schema: > > > > clock-names: > > allOf: > > - minItems: 2 > > - enum: > > - iahb > > - isfr > > - cec > > additonalItems: true > > - items: > > - iahb > > - isfr > > > > Or something along those lines, I haven't tested it, but the basic > > idea is that you want to enforce that: > > a) there's a minimum of two clocks > > b) valid clock names are iahb, isfr and cec, but we will allow more > > c) the first two clocks are iahb and isfr > > Interesting idea. I've tried > > clock-names: > allOf: > - minItems: 2 > - enum: > - iahb > - isfr > - cec > additionalItems: true Instead of these 2, you want: items: enum: [ iahb, isfr, cec ] minItems: 2 maxItems: 3 Though I assume there's some others missing as with this and below, the 3rd clock can only be 'cec'. > - items: > - const: iahb > - const: isfr And this needs 'maxItems: 3' added. Rob _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel