[PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[Andy Shevchenko]

Some devices may support MSI interrupts. Let's at least try to use them
in platforms that provide MSI capability.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
v2: fix slipped compilation error
 drivers/gpio/gpio-merrifield.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c
index 48918a016cd8..11e6ea70568a 100644
--- a/drivers/gpio/gpio-merrifield.c
+++ b/drivers/gpio/gpio-merrifield.c
@@ -473,6 +473,10 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	raw_spin_lock_init(&priv->lock);
 
+	retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
+	if (retval < 0)
+		return retval;
+
 	girq = &priv->chip.irq;
 	girq->chip = &mrfld_irqchip;
 	girq->init_hw = mrfld_irq_init_hw;
@@ -482,7 +486,7 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 				     sizeof(*girq->parents), GFP_KERNEL);
 	if (!girq->parents)
 		return -ENOMEM;
-	girq->parents[0] = pdev->irq;
+	girq->parents[0] = pci_irq_vector(pdev, 0);
 	girq->first = irq_base;
 	girq->default_type = IRQ_TYPE_NONE;
 	girq->handler = handle_bad_irq;
-- 
2.25.1

[PATCH v2 2/2] gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

[Andy Shevchenko]

It's a bit hard to realize what the BAR1 is for and what is the layout
of the data in it. Be slightly more verbose to better show how GPIO and
IRQ bases are derived from the hardware.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
v2: no change
 drivers/gpio/gpio-merrifield.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c
index 11e6ea70568a..706687fab634 100644
--- a/drivers/gpio/gpio-merrifield.c
+++ b/drivers/gpio/gpio-merrifield.c
@@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	base = pcim_iomap_table(pdev)[1];
 
-	irq_base = readl(base);
-	gpio_base = readl(sizeof(u32) + base);
+	irq_base = readl(base + 0 * sizeof(u32));
+	gpio_base = readl(base + 1 * sizeof(u32));
 
 	/* Release the IO mapping, since we already get the info from BAR1 */
 	pcim_iounmap_regions(pdev, BIT(1));
-- 
2.25.1

Re: [PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[Linus Walleij]

On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:

> Some devices may support MSI interrupts. Let's at least try to use them
> in platforms that provide MSI capability.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Patch applied.

Yours,
Linus Walleij

Re: [PATCH v2 2/2] gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

[Linus Walleij]

On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:

> It's a bit hard to realize what the BAR1 is for and what is the layout
> of the data in it. Be slightly more verbose to better show how GPIO and
> IRQ bases are derived from the hardware.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Patch applied.

Yours,
Linus Walleij

Re: [PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[Andy Shevchenko]

On Thu, Apr 16, 2020 at 12:50:43PM +0200, Linus Walleij wrote:
> On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> 
> > Some devices may support MSI interrupts. Let's at least try to use them
> > in platforms that provide MSI capability.
> >
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> Patch applied.

Can we return to established scheme when we send a PR to you? Or you think
better not to do like that anymore?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[Linus Walleij]

On Thu, Apr 16, 2020 at 1:35 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> On Thu, Apr 16, 2020 at 12:50:43PM +0200, Linus Walleij wrote:
> > On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko
> > <andriy.shevchenko@linux.intel.com> wrote:
> >
> > > Some devices may support MSI interrupts. Let's at least try to use them
> > > in platforms that provide MSI capability.
> > >
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >
> > Patch applied.
>
> Can we return to established scheme when we send a PR to you? Or you think
> better not to do like that anymore?

No problem, I haven't pushed this out or anything, I will drop these.

Yours,
Linus Walleij

Re: [PATCH v2 1/2] gpio: merrifield: Switch over to MSI interrupts

[Andy Shevchenko]

On Thu, Apr 16, 2020 at 02:16:36PM +0200, Linus Walleij wrote:
> On Thu, Apr 16, 2020 at 1:35 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Thu, Apr 16, 2020 at 12:50:43PM +0200, Linus Walleij wrote:
> > > On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko
> > > <andriy.shevchenko@linux.intel.com> wrote:
> > >
> > > > Some devices may support MSI interrupts. Let's at least try to use them
> > > > in platforms that provide MSI capability.
> > > >
> > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > >
> > > Patch applied.
> >
> > Can we return to established scheme when we send a PR to you? Or you think
> > better not to do like that anymore?
> 
> No problem, I haven't pushed this out or anything, I will drop these.

Thank you. Let's keep it the way we agreed before, i.e. PR for Intel GPIO
drivers. For this cycle it seems PCH and Merrifield ones to the date.

-- 
With Best Regards,
Andy Shevchenko