From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94E83C2BB55 for ; Thu, 16 Apr 2020 14:03:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DE6720732 for ; Thu, 16 Apr 2020 14:03:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587045798; bh=hdTXoxkrdgeEsruKVakXS40NWxVwkDOQ6lkFtL1wn40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Yp00cDYO3VjTuKtQGd/qjNKWHl9qHKpDfgi8blw81cWUxvqXH6UqC0cdNhWLfI5Ve iw91pwFcVpdzb+syfFIKGT4YRfwiVZi133eJpOAxNtkwc168El73D8uqVr7jgY3KDx giIxkdFJLjT6MulD3i0tNSLDg/SlqzYnilKNIaFo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728986AbgDPODP (ORCPT ); Thu, 16 Apr 2020 10:03:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:54908 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408486AbgDPNl6 (ORCPT ); Thu, 16 Apr 2020 09:41:58 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 61612214D8; Thu, 16 Apr 2020 13:41:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587044517; bh=hdTXoxkrdgeEsruKVakXS40NWxVwkDOQ6lkFtL1wn40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n4Ih8qB3EikyqQNrndltDE/Xb75ZsKt//slsaSwHTy3nfAiVHL+ICamOfkzD1h+5l 8hGDcasxmW0yWkGmIlGp4d9iv63q7/uLp32anEZQaw8KXf1adw1dgeOKYzI33OpY49 968p1DLnQ9ozShXjTyfDsFyxFSpINjdKxzt5iWC4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Yuxian Dai , Alex Deucher , Huang Rui , Kevin Wang Subject: [PATCH 5.5 210/257] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK Date: Thu, 16 Apr 2020 15:24:21 +0200 Message-Id: <20200416131352.314278648@linuxfoundation.org> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200416131325.891903893@linuxfoundation.org> References: <20200416131325.891903893@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yuxian Dai commit 022ac4c9c55be35a2d1f71019a931324c51b0dab upstream. 1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by: Yuxian Dai Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -181,6 +181,7 @@ static int renoir_print_clk_levels(struc uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -240,8 +241,13 @@ static int renoir_print_clk_levels(struc GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if (cur_value == value) + cur_value_match_level = true; } + if (!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n", cur_value); + return size; } --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct freq = table->SocClocks[dpm_level].Freq; \ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq; \ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq; \