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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8250: Add cpufreq hw node
Date: Mon, 20 Apr 2020 14:03:22 -0700	[thread overview]
Message-ID: <20200420210322.GS576963@builder.lan> (raw)
In-Reply-To: <20200415061806.740965-1-bjorn.andersson@linaro.org>

On Tue 14 Apr 23:18 PDT 2020, Bjorn Andersson wrote:

> Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores
> on SM8250 SoCs.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index d7b2049f339c..e62e77ff48c2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -41,6 +41,7 @@ CPU0: cpu@0 {
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -56,6 +57,7 @@ CPU1: cpu@100 {
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_100>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_100: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -68,6 +70,7 @@ CPU2: cpu@200 {
>  			reg = <0x0 0x200>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_200>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_200: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -80,6 +83,7 @@ CPU3: cpu@300 {
>  			reg = <0x0 0x300>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_300>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_300: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -92,6 +96,7 @@ CPU4: cpu@400 {
>  			reg = <0x0 0x400>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_400>;
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			L2_400: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -104,6 +109,7 @@ CPU5: cpu@500 {
>  			reg = <0x0 0x500>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_500>;
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			L2_500: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -117,6 +123,7 @@ CPU6: cpu@600 {
>  			reg = <0x0 0x600>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_600>;
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			L2_600: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -129,6 +136,7 @@ CPU7: cpu@700 {
>  			reg = <0x0 0x700>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_700>;
> +			qcom,freq-domain = <&cpufreq_hw 2>;
>  			L2_700: l2-cache {
>  			      compatible = "cache";
>  			      next-level-cache = <&L3_0>;
> @@ -499,6 +507,19 @@ frame@17c2d000 {
>  			};
>  		};
>  
> +		cpufreq_hw: cpufreq@18591000 {
> +			compatible = "qcom,cpufreq-hw";

As pointed out by Sibi, SM8250 comes with the new EPSS block for
frequency and voltage scaling, so this is wrong.

Regards,
Bjorn

> +			reg = <0 0x18591000 0 0x1000>,
> +			      <0 0x18592000 0 0x1000>,
> +			      <0 0x18593000 0 0x1000>;
> +			reg-names = "freq-domain0", "freq-domain1",
> +				    "freq-domain2";
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> +			clock-names = "xo", "alternate";
> +
> +			#freq-domain-cells = <1>;
> +		};
>  	};
>  
>  	timer {
> -- 
> 2.24.0
> 

      reply	other threads:[~2020-04-20 21:03 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-15  6:18 [PATCH] arm64: dts: qcom: sm8250: Add cpufreq hw node Bjorn Andersson
2020-04-20 21:03 ` Bjorn Andersson [this message]

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