From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F9FC54FC9 for ; Tue, 21 Apr 2020 09:20:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33DF420857 for ; Tue, 21 Apr 2020 09:20:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33DF420857 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA7226E44F; Tue, 21 Apr 2020 09:20:43 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id A342D6E44F for ; Tue, 21 Apr 2020 09:20:42 +0000 (UTC) IronPort-SDR: l/NWx2Nb3lJhc4/VlQul3gOEhqnW/aSzTEe5OM3o1yGovMvxFUOU2LLMi7k72EyLs24I1fou8P HXnabXLc7dFQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 02:20:42 -0700 IronPort-SDR: soSmUkpk+X9c6Fwt2Xb2rZ6E2ofNyk/vlCqKqLyI+y42vSve81YpvRwpq33XO4RAK2a+aQuZmQ 38Fz/s5hUatA== X-IronPort-AV: E=Sophos;i="5.72,409,1580803200"; d="scan'208";a="279572902" Received: from ideak-desk.fi.intel.com ([10.237.72.183]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 02:20:40 -0700 Date: Tue, 21 Apr 2020 12:19:47 +0300 From: Imre Deak To: Jani Nikula Message-ID: <20200421091947.GA29723@ideak-desk.fi.intel.com> References: <20200406112800.23762-1-pankaj.laxminarayan.bharadiya@intel.com> <20200406112800.23762-6-pankaj.laxminarayan.bharadiya@intel.com> <87tv1dz34n.fsf@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87tv1dz34n.fsf@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH 05/18] drm/i915/display/display: Prefer drm_WARN_ON over WARN_ON X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org, Chris Wilson Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Apr 21, 2020 at 10:53:12AM +0300, Jani Nikula wrote: > > Pankaj, the subject line is identical to patch 4, please update. > > Imre, one question inline for you. > > On Mon, 06 Apr 2020, Pankaj Bharadiya wrote: > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 433e5a81dd4d..5475f989df4c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -1850,22 +1850,29 @@ static u64 __async_put_domains_mask(struct i915_power_domains *power_domains) > > static bool > > assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) > > { > > - return !WARN_ON(power_domains->async_put_domains[0] & > > - power_domains->async_put_domains[1]); > > + struct drm_i915_private *i915 = container_of(power_domains, > > + struct drm_i915_private, > > + power_domains); > > + return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] & > > + power_domains->async_put_domains[1]); > > } > > Do we want to depend on struct i915_power_domains being a struct > drm_i915_private member via container_of? It looks ok to me, there is only one i915_power_domains struct per device. > BR, > Jani. > > > > > static bool > > __async_put_domains_state_ok(struct i915_power_domains *power_domains) > > { > > + struct drm_i915_private *i915 = container_of(power_domains, > > + struct drm_i915_private, > > + power_domains); > > enum intel_display_power_domain domain; > > bool err = false; > > > > err |= !assert_async_put_domain_masks_disjoint(power_domains); > > - err |= WARN_ON(!!power_domains->async_put_wakeref != > > - !!__async_put_domains_mask(power_domains)); > > + err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref != > > + !!__async_put_domains_mask(power_domains)); > > > > for_each_power_domain(domain, __async_put_domains_mask(power_domains)) > > - err |= WARN_ON(power_domains->domain_use_count[domain] != 1); > > + err |= drm_WARN_ON(&i915->drm, > > + power_domains->domain_use_count[domain] != 1); > > > > return !err; > > } > > @@ -2107,11 +2114,14 @@ static void > > queue_async_put_domains_work(struct i915_power_domains *power_domains, > > intel_wakeref_t wakeref) > > { > > - WARN_ON(power_domains->async_put_wakeref); > > + struct drm_i915_private *i915 = container_of(power_domains, > > + struct drm_i915_private, > > + power_domains); > > + drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); > > power_domains->async_put_wakeref = wakeref; > > - WARN_ON(!queue_delayed_work(system_unbound_wq, > > - &power_domains->async_put_work, > > - msecs_to_jiffies(100))); > > + drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq, > > + &power_domains->async_put_work, > > + msecs_to_jiffies(100))); > > } > > > > static void > > @@ -4318,6 +4328,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > > const struct i915_power_well_desc *power_well_descs, > > int power_well_count) > > { > > + struct drm_i915_private *i915 = container_of(power_domains, > > + struct drm_i915_private, > > + power_domains); > > u64 power_well_ids = 0; > > int i; > > > > @@ -4337,8 +4350,8 @@ __set_power_wells(struct i915_power_domains *power_domains, > > if (id == DISP_PW_ID_NONE) > > continue; > > > > - WARN_ON(id >= sizeof(power_well_ids) * 8); > > - WARN_ON(power_well_ids & BIT_ULL(id)); > > + drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8); > > + drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); > > power_well_ids |= BIT_ULL(id); > > } > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx