From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFEBEC55185 for ; Wed, 22 Apr 2020 19:33:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3DBE20767 for ; Wed, 22 Apr 2020 19:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726355AbgDVTdi (ORCPT ); Wed, 22 Apr 2020 15:33:38 -0400 Received: from muru.com ([72.249.23.125]:51032 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725935AbgDVTdh (ORCPT ); Wed, 22 Apr 2020 15:33:37 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 6910580EE; Wed, 22 Apr 2020 19:34:20 +0000 (UTC) Date: Wed, 22 Apr 2020 12:33:28 -0700 From: Tony Lindgren To: Philipp Rossak Cc: "H. Nikolaus Schaller" , Paul Cercueil , Maxime Ripard , Jonathan Bakker , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?Q?Beno=C3=AEt?= Cousson , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Chen-Yu Tsai , Thomas Bogendoerfer , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , OpenPVRSGX Linux Driver Group , linux-omap , Linux Kernel Mailing List Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200422193328.GD37466@atomide.com> References: <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> <20200422151328.2oyqz7gqkbunmd6o@gilmour.lan> <07923B6C-4CCD-4B81-A98F-E19C43412A89@goldelico.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Philipp Rossak [200422 19:05]: > A few years back, I did a big research on the PowerVR GPUs. Back then I > found an interesting TI datasheet. I forgot about this till I have seen the > right buzz words. Sorry that I remembered it that late. > > Back then I came to the conclusion that all PowerVR GPU's have in general 3 > Clocks. > > A system clock, a memory clock and a core clock. [1]. Hmm I'm not sure if those names are sgx or SoC specific. Anyways, the sgx clocks for omap variants are already handled by the ti-sysc module as "fck" and "ick" so nothing to do there. > The hyd_clk at sunxi devices seems to be the system clock. > > With those additional information it should be very easy to get a proper > binding. It would be best to find the clock(s) name used in the sgx docs to avoid using SoC specific naming :) But yeah "sysclk" "memclk" and "coreclk" seem just fine for me for the optional clocks if that works for other SoCs. Regards, Tony > [1]: https://github.com/embed-3d/PVRSGX_hwdoc/blob/master/sources/pdfs/Spruh73c_chapter_SGX_Graphics_Accelerator.pdf