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Fri, 24 Apr 2020 19:45:52 +0000 From: Saeed Mahameed To: Saeed Mahameed , Leon Romanovsky Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org, Moshe Shemesh , Tariq Toukan Subject: [PATCH mlx5-next 5/9] net/mlx5: Add structure layout and defines for MFRL register Date: Fri, 24 Apr 2020 12:45:06 -0700 Message-Id: <20200424194510.11221-6-saeedm@mellanox.com> X-Mailer: git-send-email 2.25.3 In-Reply-To: <20200424194510.11221-1-saeedm@mellanox.com> References: <20200424194510.11221-1-saeedm@mellanox.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BYAPR06CA0016.namprd06.prod.outlook.com (2603:10b6:a03:d4::29) To VI1PR05MB5102.eurprd05.prod.outlook.com (2603:10a6:803:5e::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from smtp.office365.com (73.15.39.150) by BYAPR06CA0016.namprd06.prod.outlook.com (2603:10b6:a03:d4::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2937.13 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: LD01Hx++sexolPrX7qZJ199xqKpIp0GHcDYinorsbZfsia1isOBLdT+izz/v2QrtuNfFkfx8rQ3wKQaDizIqlC7VAu6VamxsSye7tlVT8CwKF+3mCOs4E7XoHGaGA46AIu6PRImhl1CNnE5uNlvWc2Fm0VO4bIiLiXn3jJFp3TnkxHQcUPPA6D1acSKGz1MDEZO75vj9Yv6quL7FNeRiPd1hmaWSKIEcchm5+YkwSzOoehogSji7VA+tMDd5BsvsVthzf4lkgtZjUYDzru2Z46fJ778mXBkkwH95Qqc+6fqwRNuoQ2A7ZmPCZQnLUzTo3hio6c8vp2KM8OJ8cQozuPovHzO1BruykMINKsoTD12es95jD3Lny9C4X+/J98ROgKJ8akxEtH2Oro+AryMdQBBk/81cLTohZW5sj8v6rcEr7nLdC5UUq1VufQGB4xismjqP8cvvSacFv8IL9aoG5J0KUY9DKMEaBwuli555z78xQu7DgqSRO80L8NQGabcV X-MS-Exchange-AntiSpam-MessageData: qZeNH+pEzzY3rFTZTIwSRmRZbTXycydaDhQxn8unK1fwpu+80ku/l2VmlSzGR+LBc6J3ar690VI+At1HIPCXNWhmksJ/s3LgPS9gmkV+c9gyG9IBBihEL5rk/Q7278hi0JvQiPwD0YmKKSsghfv+QA== X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fecf1454-f203-44eb-56f0-08d7e88814b9 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2020 19:45:46.3907 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zmHIcjEWx7/Ae0tZCpzUlc2yY8R8nLPRQFGowvq69fU+YaKz3W8QEpHwieeLAeFmo4+cC2VnWsOMBhC7ZotS9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR05MB5072 Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Moshe Shemesh Add needed structure layouts and defines for MFRL (Management Firmware Reset Level) register. This structure will be used for the firmware upgrade and reset flow in the downstream patches. Signed-off-by: Moshe Shemesh Reviewed-by: Tariq Toukan Signed-off-by: Saeed Mahameed --- include/linux/mlx5/driver.h | 1 + include/linux/mlx5/mlx5_ifc.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index b46537a81703..d82dbbab8179 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -130,6 +130,7 @@ enum { MLX5_REG_NODE_DESC = 0x6001, MLX5_REG_HOST_ENDIANNESS = 0x7004, MLX5_REG_MCIA = 0x9014, + MLX5_REG_MFRL = 0x9028, MLX5_REG_MLCR = 0x902b, MLX5_REG_MTRC_CAP = 0x9040, MLX5_REG_MTRC_CONF = 0x9041, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cf971d341189..9e6a3cec1e32 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -9703,6 +9703,29 @@ struct mlx5_ifc_mcda_reg_bits { u8 data[0][0x20]; }; +enum { + MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), + MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), +}; + +enum { + MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), + MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), + MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), +}; + +struct mlx5_ifc_mfrl_reg_bits { + u8 reserved_at_0[0x20]; + + u8 reserved_at_20[0x2]; + u8 pci_sync_for_fw_update_start[0x1]; + u8 pci_sync_for_fw_update_resp[0x2]; + u8 rst_type_sel[0x3]; + u8 reserved_at_28[0x8]; + u8 reset_type[0x8]; + u8 reset_level[0x8]; +}; + struct mlx5_ifc_mirc_reg_bits { u8 reserved_at_0[0x18]; u8 status_code[0x8]; @@ -9766,6 +9789,7 @@ union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_mcc_reg_bits mcc_reg; struct mlx5_ifc_mcda_reg_bits mcda_reg; struct mlx5_ifc_mirc_reg_bits mirc_reg; + struct mlx5_ifc_mfrl_reg_bits mfrl_reg; u8 reserved_at_0[0x60e0]; }; -- 2.25.3