From: Stephen Long <steplong@quicinc.com>
To: <qemu-devel@nongnu.org>
Cc: qemu-arm@nongnu.org, richard.henderson@linaro.org, apazos@quicinc.com
Subject: [PATCH RFC v3 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1
Date: Mon, 27 Apr 2020 14:40:46 -0700 [thread overview]
Message-ID: <20200427214046.31401-4-steplong@quicinc.com> (raw)
In-Reply-To: <20200427214046.31401-1-steplong@quicinc.com>
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/crypto_helper.c | 12 ++++++++++++
target/arm/helper-sve.h | 1 +
target/arm/helper.h | 2 ++
target/arm/sve.decode | 4 ++++
target/arm/sve_helper.c | 8 ++++++++
target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++
6 files changed, 57 insertions(+)
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 45740c1bfd..0720b3b98f 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -705,3 +705,15 @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
rd[0] = d.l[0];
rd[1] = d.l[1];
}
+
+void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+
+ for (i = 0; i < opr_sz; ++i) {
+ uint64_t nn = n[i];
+ uint64_t mm = m[i];
+ d[i] = nn ^ rol64(mm, 1);
+ }
+}
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 7eef4eb476..059003c26e 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2692,3 +2692,4 @@ DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 37f489412c..c74cea76a2 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -537,6 +537,8 @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 1cb5792bb1..278530ca83 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1435,3 +1435,7 @@ AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
+
+## SVE2 crypto constructive binary operations
+SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
+RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index b3a7594981..3b560e702a 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7524,3 +7524,11 @@ void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
HELPER(crypto_sm4e)(vd + i, vn + i);
}
}
+
+void HELPER(sve2_sm4ekey)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4ekey)(vd + i, vn + i, vm + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4253955471..affe41779b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7990,3 +7990,33 @@ static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
}
return true;
}
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_sm4ekey);
+ }
+ return true;
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_crypto_rax1);
+ }
+ return true;
+}
--
2.17.1
next prev parent reply other threads:[~2020-04-27 21:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-27 21:40 [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
2020-04-27 21:40 ` Stephen Long [this message]
2020-06-16 18:19 ` [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Richard Henderson
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