From: Francisco Jerez <currojerez@riseup.net> To: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada\, Srinivas" <srinivas.pandruvada@intel.com> Cc: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org, chris.p.wilson@intel.com, "Vivi\, Rodrigo" <rodrigo.vivi@intel.com>, Peter Zijlstra <peterz@infradead.org> Subject: [PATCHv2.99 03/11] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs. Date: Mon, 27 Apr 2020 20:22:50 -0700 [thread overview] Message-ID: <20200428032258.2518-4-currojerez@riseup.net> (raw) In-Reply-To: <20200428032258.2518-1-currojerez@riseup.net> v3: Rename CPU_RESPONSE_FREQUENCY to CPU_SCALING_RESPONSE (Rafael). Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/gpu/drm/i915/i915_debugfs.c | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index aa35a59f1c7d..16a45fd2c376 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1247,6 +1247,72 @@ static int i915_llc(struct seq_file *m, void *data) return 0; } +static int +i915_sf_qos_delay_max_ns_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.delay_max_ns, val); + return 0; +} + +static int +i915_sf_qos_delay_max_ns_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.delay_max_ns); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_delay_max_ns_fops, + i915_sf_qos_delay_max_ns_get, + i915_sf_qos_delay_max_ns_set, "%llu\n"); + +static int +i915_sf_qos_delay_slope_shift_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.delay_slope_shift, val); + return 0; +} + +static int +i915_sf_qos_delay_slope_shift_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.delay_slope_shift); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_delay_slope_shift_fops, + i915_sf_qos_delay_slope_shift_get, + i915_sf_qos_delay_slope_shift_set, "%llu\n"); + +static int +i915_sf_qos_target_hz_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.target_hz, val); + return 0; +} + +static int +i915_sf_qos_target_hz_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.target_hz); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_target_hz_fops, + i915_sf_qos_target_hz_get, + i915_sf_qos_target_hz_set, "%llu\n"); + static int i915_runtime_pm_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -1882,6 +1948,9 @@ static const struct i915_debugfs_files { {"i915_error_state", &i915_error_state_fops}, {"i915_gpu_info", &i915_gpu_info_fops}, #endif + {"i915_sf_qos_delay_max_ns", &i915_sf_qos_delay_max_ns_fops}, + {"i915_sf_qos_delay_slope_shift", &i915_sf_qos_delay_slope_shift_fops}, + {"i915_sf_qos_target_hz", &i915_sf_qos_target_hz_fops} }; void i915_debugfs_register(struct drm_i915_private *dev_priv) -- 2.22.1
WARNING: multiple messages have this Message-ID (diff)
From: Francisco Jerez <currojerez@riseup.net> To: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada\, Srinivas" <srinivas.pandruvada@intel.com> Cc: Peter Zijlstra <peterz@infradead.org>, intel-gfx@lists.freedesktop.org, chris.p.wilson@intel.com, linux-pm@vger.kernel.org Subject: [Intel-gfx] [PATCHv2.99 03/11] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs. Date: Mon, 27 Apr 2020 20:22:50 -0700 [thread overview] Message-ID: <20200428032258.2518-4-currojerez@riseup.net> (raw) In-Reply-To: <20200428032258.2518-1-currojerez@riseup.net> v3: Rename CPU_RESPONSE_FREQUENCY to CPU_SCALING_RESPONSE (Rafael). Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/gpu/drm/i915/i915_debugfs.c | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index aa35a59f1c7d..16a45fd2c376 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1247,6 +1247,72 @@ static int i915_llc(struct seq_file *m, void *data) return 0; } +static int +i915_sf_qos_delay_max_ns_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.delay_max_ns, val); + return 0; +} + +static int +i915_sf_qos_delay_max_ns_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.delay_max_ns); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_delay_max_ns_fops, + i915_sf_qos_delay_max_ns_get, + i915_sf_qos_delay_max_ns_set, "%llu\n"); + +static int +i915_sf_qos_delay_slope_shift_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.delay_slope_shift, val); + return 0; +} + +static int +i915_sf_qos_delay_slope_shift_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.delay_slope_shift); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_delay_slope_shift_fops, + i915_sf_qos_delay_slope_shift_get, + i915_sf_qos_delay_slope_shift_set, "%llu\n"); + +static int +i915_sf_qos_target_hz_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.sf_qos.target_hz, val); + return 0; +} + +static int +i915_sf_qos_target_hz_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.sf_qos.target_hz); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sf_qos_target_hz_fops, + i915_sf_qos_target_hz_get, + i915_sf_qos_target_hz_set, "%llu\n"); + static int i915_runtime_pm_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -1882,6 +1948,9 @@ static const struct i915_debugfs_files { {"i915_error_state", &i915_error_state_fops}, {"i915_gpu_info", &i915_gpu_info_fops}, #endif + {"i915_sf_qos_delay_max_ns", &i915_sf_qos_delay_max_ns_fops}, + {"i915_sf_qos_delay_slope_shift", &i915_sf_qos_delay_slope_shift_fops}, + {"i915_sf_qos_target_hz", &i915_sf_qos_target_hz_fops} }; void i915_debugfs_register(struct drm_i915_private *dev_priv) -- 2.22.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-04-28 3:27 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-28 3:22 [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2.99) Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 01/11] PM: QoS: Add CPU_SCALING_RESPONSE global PM QoS limit Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 02/11] drm/i915: Adjust PM QoS scaling response frequency based on GPU load Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` Francisco Jerez [this message] 2020-04-28 3:22 ` [Intel-gfx] [PATCHv2.99 03/11] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 04/11] cpufreq: Define ADAPTIVE frequency governor policy Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 05/11] cpufreq: intel_pstate: Reorder intel_pstate_clear_update_util_hook() and intel_pstate_set_update_util_hook() Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 06/11] cpufreq: intel_pstate: Call intel_pstate_set_update_util_hook() once from the setpolicy hook Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 07/11] cpufreq: intel_pstate: Implement VLP controller statistics and target range calculation Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 08/11] cpufreq: intel_pstate: Implement VLP controller for HWP parts Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 09/11] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 10/11] OPTIONAL: cpufreq: intel_pstate: Add tracing of VLP controller status Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 11/11] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:32 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [PATCHv2.99,01/11] PM: QoS: Add CPU_SCALING_RESPONSE global PM QoS limit Patchwork 2020-05-11 10:57 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2.99) Peter Zijlstra 2020-05-11 10:57 ` [Intel-gfx] " Peter Zijlstra 2020-05-11 21:01 ` Francisco Jerez 2020-05-11 21:01 ` [Intel-gfx] " Francisco Jerez 2020-05-14 10:26 ` Rafael J. Wysocki 2020-05-14 10:26 ` [Intel-gfx] " Rafael J. Wysocki 2020-05-15 0:48 ` Francisco Jerez 2020-05-15 0:48 ` [Intel-gfx] " Francisco Jerez 2020-05-14 11:50 ` Valentin Schneider 2020-05-14 11:50 ` [Intel-gfx] " Valentin Schneider 2020-05-15 0:48 ` Francisco Jerez 2020-05-15 0:48 ` [Intel-gfx] " Francisco Jerez 2020-05-15 18:09 ` Valentin Schneider 2020-05-15 18:09 ` [Intel-gfx] " Valentin Schneider 2020-05-28 9:29 ` Lukasz Luba 2020-05-28 9:29 ` [Intel-gfx] " Lukasz Luba
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