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From: "Pali Rohár" <pali@kernel.org>
To: "Jason Cooper" <jason@lakedaemon.net>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Gregory Clement" <gregory.clement@bootlin.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Andrew Murray" <amurray@thegoodpenguin.co.uk>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Remi Pommarel" <repk@triplefau.lt>,
	"Marek Behún" <marek.behun@nic.cz>,
	"Tomasz Maciej Nowak" <tmn505@gmail.com>,
	Xogium <contact@xogium.me>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: [PATCH v4 08/12] PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros
Date: Thu, 30 Apr 2020 10:06:21 +0200	[thread overview]
Message-ID: <20200430080625.26070-9-pali@kernel.org> (raw)
In-Reply-To: <20200430080625.26070-1-pali@kernel.org>

PCI-E capability macros are already defined in linux/pci_regs.h.
Remove their reimplementation in pcie-aardvark.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 41 ++++++++++++---------------
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 053ae6c19a3d..c53ae2511a9c 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -34,17 +34,6 @@
 #define     PCIE_CORE_CMD_MEM_IO_REQ_EN				BIT(2)
 #define PCIE_CORE_DEV_REV_REG					0x8
 #define PCIE_CORE_PCIEXP_CAP					0xc0
-#define PCIE_CORE_DEV_CTRL_STATS_REG				0xc8
-#define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE	(0 << 4)
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT	5
-#define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ		0x2
-#define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
-#define     PCIE_CORE_LINK_L0S_ENTRY				BIT(0)
-#define     PCIE_CORE_LINK_TRAINING				BIT(5)
-#define     PCIE_CORE_LINK_SPEED_SHIFT				16
-#define     PCIE_CORE_LINK_WIDTH_SHIFT				20
 #define PCIE_CORE_ERR_CAPCTL_REG				0x118
 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)
 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN			BIT(6)
@@ -223,6 +212,11 @@ static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
 	return readl(pcie->base + reg);
 }
 
+static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg)
+{
+	return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8);
+}
+
 static int advk_pcie_link_up(struct advk_pcie *pcie)
 {
 	u32 val, ltssm_state;
@@ -286,16 +280,16 @@ static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen)
 	 * Start link training immediately after enabling it.
 	 * This solves problems for some buggy cards.
 	 */
-	reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
-	reg |= PCIE_CORE_LINK_TRAINING;
-	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
+	reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
+	reg |= PCI_EXP_LNKCTL_RL;
+	advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
 
 	ret = advk_pcie_wait_for_link(pcie);
 	if (ret)
 		return ret;
 
-	reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
-	neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf;
+	reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA);
+	neg_gen = reg & PCI_EXP_LNKSTA_CLS;
 
 	return neg_gen;
 }
@@ -385,13 +379,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 		PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
 	advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
 
-	/* Set PCIe Device Control and Status 1 PF0 register */
-	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
-		(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
-		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
-		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
-		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
-	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+	/* Set PCIe Device Control register */
+	reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
+	reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
+	reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
+	reg &= ~PCI_EXP_DEVCTL_READRQ;
+	reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */
+	reg |= PCI_EXP_DEVCTL_READRQ_512B;
+	advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
 
 	/* Program PCIe Control 2 to disable strict ordering */
 	reg = PCIE_CORE_CTRL2_RESERVED |
-- 
2.20.1


  parent reply	other threads:[~2020-04-30  8:07 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30  8:06 [PATCH v4 00/12] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Pali Rohár
2020-04-30  8:06 ` [PATCH v4 01/12] PCI: aardvark: Train link immediately after enabling training Pali Rohár
2020-05-04 15:50   ` Bjorn Helgaas
2020-05-07 21:05   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 02/12] PCI: aardvark: Don't blindly enable ASPM L0s and don't write to read-only register Pali Rohár
2020-05-07 21:07   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 03/12] PCI: of: Zero max-link-speed value is invalid Pali Rohár
2020-05-07 21:07   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 04/12] PCI: aardvark: Improve link training Pali Rohár
2020-05-07 21:10   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 05/12] PCI: aardvark: Issue PERST via GPIO Pali Rohár
2020-04-30  8:22   ` Pali Rohár
2020-05-07 21:20     ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 06/12] PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access Pali Rohár
2020-05-07 21:20   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 07/12] PCI: aardvark: Add PHY support Pali Rohár
2020-05-07 21:23   ` Rob Herring
2020-04-30  8:06 ` Pali Rohár [this message]
2020-05-04 15:52   ` [PATCH v4 08/12] PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros Bjorn Helgaas
2020-05-07 21:24   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 09/12] dt-bindings: PCI: aardvark: Describe new properties Pali Rohár
2020-05-07 21:25   ` Rob Herring
2020-04-30  8:06 ` [PATCH v4 10/12] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio function Pali Rohár
2020-04-30  8:06 ` [PATCH v4 11/12] arm64: dts: marvell: armada-37xx: Move PCIe comphy handle property Pali Rohár
2020-04-30  8:06 ` [PATCH v4 12/12] arm64: dts: marvell: armada-37xx: Move PCIe max-link-speed property Pali Rohár
2020-05-04 15:50   ` Bjorn Helgaas
2020-05-08 13:11 ` [PATCH v4 00/12] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Tomasz Maciej Nowak
2020-05-13 11:16 ` Pali Rohár
2020-05-13 11:33   ` Lorenzo Pieralisi
2020-05-13 11:59     ` Pali Rohár
2020-05-13 11:56 ` Thomas Petazzoni
2020-05-17 15:57   ` Gregory CLEMENT
2020-05-18 10:30     ` Pali Rohár
2020-05-18 13:46       ` Lorenzo Pieralisi
2020-05-18 13:50         ` Marek Behun

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