* [Intel-gfx] Wait-for-submit on future syncobj
@ 2020-05-04 13:50 Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] " Chris Wilson
` (11 more replies)
0 siblings, 12 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth
This series extends the I915_EXEC_FENCE_SUBMIT to syncobj; with the
primary motivation for this to allow userspace to schedule between
individual clients coordinating with semaphores. The advantage syncobj
have over sync-file is that since the syncobj is known a priori, it can
be used to pass the location of a not-yet-submitted fence. This is used
by iris in its deferred flush implementations where a fence is acquired
for an incomplete batch, and that future-fence may be used to
serlisation execution in another context. Since we already handle
'bonded execution' for media submission, we need only extend support to
syncobjs.
A simplified example of out-of-order execution that is required by iris:
struct drm_i915_gem_exec_object2 obj = {
.offset = 24 << 20,
.handle = future_submit_batch(i915, 24 << 20),
.flags = EXEC_OBJECT_PINNED,
};
struct drm_i915_gem_exec_fence fence = {
.handle = syncobj_create(i915, 0),
};
struct drm_i915_gem_execbuffer2 execbuf = {
.buffers_ptr = to_user_pointer(&obj),
.buffer_count = 1,
.cliprects_ptr = to_user_pointer(&fence),
.num_cliprects = 1,
.flags = engine | I915_EXEC_FENCE_ARRAY,
};
uint32_t result;
int out;
/*
* Here we submit client A waiting on client B, but internally client
* B has a semaphore that waits on client A. This relies on timeslicing
* to reorder B before A, even though userspace has asked to submit
* A & B simultaneously (and due to the sequence we will submit B
* then A).
*/
igt_require(gem_scheduler_has_timeslicing(i915));
execbuf.rsvd1 = gem_context_create(i915);
fence.flags = I915_EXEC_FENCE_WAIT | I915_EXEC_FENCE_WAIT_SUBMIT;
execbuf.batch_start_offset = 0;
execbuf.flags |= I915_EXEC_FENCE_OUT;
igt_require(__gem_execbuf_wr(i915, &execbuf) == 0); /* writes 1 */
execbuf.flags &= ~I915_EXEC_FENCE_OUT;
gem_context_destroy(i915, execbuf.rsvd1);
execbuf.rsvd1 = gem_context_create(i915);
fence.flags = I915_EXEC_FENCE_SIGNAL;
execbuf.batch_start_offset = 64;
gem_execbuf(i915, &execbuf); /* writes 2 */
gem_context_destroy(i915, execbuf.rsvd1);
gem_sync(i915, obj.handle); /* write hazard lies */
gem_read(i915, obj.handle, 4000, &result, sizeof(result));
igt_assert_eq(result, 2);
/* check we didn't autotimeout */
out = execbuf.rsvd2 >> 32;
igt_assert_eq(sync_fence_status(out), 1);
close(out);
gem_close(i915, obj.handle);
syncobj_destroy(i915, fence.handle);
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 2/6] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
` (10 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, lionel.g.landwerlin, kenneth, Chris Wilson, stable
We recorded the dependencies for WAIT_FOR_SUBMIT in order that we could
correctly perform priority inheritance from the parallel branches to the
common trunk. However, for the purpose of timeslicing and reset
handling, the dependency is weak -- as we the pair of requests are
allowed to run in parallel and not in strict succession. So for example
we do need to suspend one if the other hangs.
The real significance though is that this allows us to rearrange
groups of WAIT_FOR_SUBMIT linked requests along the single engine, and
so can resolve user level inter-batch scheduling dependencies from user
semaphores.
Fixes: c81471f5e95c ("drm/i915: Copy across scheduler behaviour flags across submit fences")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: <stable@vger.kernel.org> # v5.6+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +++++++++
drivers/gpu/drm/i915/i915_request.c | 8 ++++++--
drivers/gpu/drm/i915/i915_scheduler.c | 4 +++-
drivers/gpu/drm/i915/i915_scheduler.h | 3 ++-
drivers/gpu/drm/i915/i915_scheduler_types.h | 1 +
5 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..a47e4e15cbaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1883,6 +1883,9 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2729,6 +2732,9 @@ static void __execlists_hold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2853,6 +2859,9 @@ static void __execlists_unhold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Propagate any change in error status */
if (rq->fence.error)
i915_request_set_error_once(w, rq->fence.error);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 22635bbabf06..95edc5523a01 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1038,7 +1038,9 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
if (to->engine->schedule) {
- ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ ret = i915_sched_node_add_dependency(&to->sched,
+ &from->sched,
+ 0);
if (ret < 0)
return ret;
}
@@ -1200,7 +1202,9 @@ __i915_request_await_execution(struct i915_request *to,
/* Couple the dependency tree for PI on this exposed to->fence */
if (to->engine->schedule) {
- err = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ err = i915_sched_node_add_dependency(&to->sched,
+ &from->sched,
+ I915_DEPENDENCY_WEAK);
if (err < 0)
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 37cfcf5b321b..5f4c1e49e974 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -462,7 +462,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
}
int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal)
+ struct i915_sched_node *signal,
+ unsigned long flags)
{
struct i915_dependency *dep;
@@ -473,6 +474,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
local_bh_disable();
if (!__i915_sched_node_add_dependency(node, signal, dep,
+ flags |
I915_DEPENDENCY_EXTERNAL |
I915_DEPENDENCY_ALLOC))
i915_dependency_free(dep);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index d1dc4efef77b..6f0bf00fc569 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -34,7 +34,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
unsigned long flags);
int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal);
+ struct i915_sched_node *signal,
+ unsigned long flags);
void i915_sched_node_fini(struct i915_sched_node *node);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index d18e70550054..7186875088a0 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -78,6 +78,7 @@ struct i915_dependency {
unsigned long flags;
#define I915_DEPENDENCY_ALLOC BIT(0)
#define I915_DEPENDENCY_EXTERNAL BIT(1)
+#define I915_DEPENDENCY_WEAK BIT(2)
};
#endif /* _I915_SCHEDULER_TYPES_H_ */
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency
@ 2020-05-04 13:50 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson, stable
We recorded the dependencies for WAIT_FOR_SUBMIT in order that we could
correctly perform priority inheritance from the parallel branches to the
common trunk. However, for the purpose of timeslicing and reset
handling, the dependency is weak -- as we the pair of requests are
allowed to run in parallel and not in strict succession. So for example
we do need to suspend one if the other hangs.
The real significance though is that this allows us to rearrange
groups of WAIT_FOR_SUBMIT linked requests along the single engine, and
so can resolve user level inter-batch scheduling dependencies from user
semaphores.
Fixes: c81471f5e95c ("drm/i915: Copy across scheduler behaviour flags across submit fences")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: <stable@vger.kernel.org> # v5.6+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +++++++++
drivers/gpu/drm/i915/i915_request.c | 8 ++++++--
drivers/gpu/drm/i915/i915_scheduler.c | 4 +++-
drivers/gpu/drm/i915/i915_scheduler.h | 3 ++-
drivers/gpu/drm/i915/i915_scheduler_types.h | 1 +
5 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..a47e4e15cbaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1883,6 +1883,9 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2729,6 +2732,9 @@ static void __execlists_hold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2853,6 +2859,9 @@ static void __execlists_unhold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Propagate any change in error status */
if (rq->fence.error)
i915_request_set_error_once(w, rq->fence.error);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 22635bbabf06..95edc5523a01 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1038,7 +1038,9 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
if (to->engine->schedule) {
- ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ ret = i915_sched_node_add_dependency(&to->sched,
+ &from->sched,
+ 0);
if (ret < 0)
return ret;
}
@@ -1200,7 +1202,9 @@ __i915_request_await_execution(struct i915_request *to,
/* Couple the dependency tree for PI on this exposed to->fence */
if (to->engine->schedule) {
- err = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ err = i915_sched_node_add_dependency(&to->sched,
+ &from->sched,
+ I915_DEPENDENCY_WEAK);
if (err < 0)
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 37cfcf5b321b..5f4c1e49e974 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -462,7 +462,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
}
int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal)
+ struct i915_sched_node *signal,
+ unsigned long flags)
{
struct i915_dependency *dep;
@@ -473,6 +474,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
local_bh_disable();
if (!__i915_sched_node_add_dependency(node, signal, dep,
+ flags |
I915_DEPENDENCY_EXTERNAL |
I915_DEPENDENCY_ALLOC))
i915_dependency_free(dep);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index d1dc4efef77b..6f0bf00fc569 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -34,7 +34,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
unsigned long flags);
int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal);
+ struct i915_sched_node *signal,
+ unsigned long flags);
void i915_sched_node_fini(struct i915_sched_node *node);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index d18e70550054..7186875088a0 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -78,6 +78,7 @@ struct i915_dependency {
unsigned long flags;
#define I915_DEPENDENCY_ALLOC BIT(0)
#define I915_DEPENDENCY_EXTERNAL BIT(1)
+#define I915_DEPENDENCY_WEAK BIT(2)
};
#endif /* _I915_SCHEDULER_TYPES_H_ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 2/6] dma-buf: Proxy fence, an unsignaled fence placeholder
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] " Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 3/6] drm/syncobj: Allow use of dma-fence-proxy Chris Wilson
` (9 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real fence completes, and any future listeners will instead be
attach directly to the real fence avoiding any indirection overhead.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/dma-buf/Makefile | 13 +-
drivers/dma-buf/dma-fence-private.h | 20 +
drivers/dma-buf/dma-fence-proxy.c | 255 ++++++++++
drivers/dma-buf/dma-fence.c | 4 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-proxy.c | 699 +++++++++++++++++++++++++++
include/linux/dma-fence-proxy.h | 34 ++
7 files changed, 1022 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-private.h
create mode 100644 drivers/dma-buf/dma-fence-proxy.c
create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c
create mode 100644 include/linux/dma-fence-proxy.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 995e05f609ff..afaf6dadd9a3 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
- dma-resv.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-proxy.o \
+ dma-resv.o \
+ seqno-fence.o
obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o
obj-$(CONFIG_DMABUF_HEAPS) += heaps/
obj-$(CONFIG_SYNC_FILE) += sync_file.o
@@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
dmabuf_selftests-y := \
selftest.o \
st-dma-fence.o \
- st-dma-fence-chain.o
+ st-dma-fence-chain.o \
+ st-dma-fence-proxy.o
obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/dma-fence-private.h b/drivers/dma-buf/dma-fence-private.h
new file mode 100644
index 000000000000..6924d28af0fa
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-private.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark <robdclark@gmail.com>
+ * Maarten Lankhorst <maarten.lankhorst@canonical.com>
+ */
+
+#ifndef DMA_FENCE_PRIVATE_H
+#define DMA_FENCE_PRIAVTE_H
+
+struct dma_fence;
+
+bool __dma_fence_enable_signaling(struct dma_fence *fence);
+
+#endif /* DMA_FENCE_PRIAVTE_H */
diff --git a/drivers/dma-buf/dma-fence-proxy.c b/drivers/dma-buf/dma-fence-proxy.c
new file mode 100644
index 000000000000..d6cde1f30ef4
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-proxy.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dma-fence-proxy: placeholder unsignaled fence
+ *
+ * Copyright (C) 2017-2019 Intel Corporation
+ */
+
+#include <linux/dma-fence.h>
+#include <linux/dma-fence-proxy.h>
+#include <linux/export.h>
+#include <linux/irq_work.h>
+#include <linux/slab.h>
+
+#include "dma-fence-private.h"
+
+struct dma_fence_proxy {
+ struct dma_fence base;
+
+ struct dma_fence *real;
+ struct dma_fence_cb cb;
+ struct irq_work work;
+
+ wait_queue_head_t wq;
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+#define same_lockclass(A, B) (A)->dep_map.key == (B)->dep_map.key
+#else
+#define same_lockclass(A, B) 0
+#endif
+
+static const char *proxy_get_driver_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_driver_name(real) : "proxy";
+}
+
+static const char *proxy_get_timeline_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_timeline_name(real) : "unset";
+}
+
+static void proxy_irq_work(struct irq_work *work)
+{
+ struct dma_fence_proxy *p = container_of(work, typeof(*p), work);
+
+ dma_fence_signal(&p->base);
+ dma_fence_put(&p->base);
+}
+
+static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb)
+{
+ struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb);
+
+ if (real->error)
+ dma_fence_set_error(&p->base, real->error);
+
+ /* Lower the height of the proxy chain -> single stack frame */
+ irq_work_queue(&p->work);
+}
+
+static bool proxy_enable_signaling(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+ bool ret = true;
+
+ if (real) {
+ spin_lock_nested(real->lock,
+ same_lockclass(&p->wq.lock, real->lock));
+ ret = __dma_fence_enable_signaling(real);
+ spin_unlock(real->lock);
+ }
+
+ return ret;
+}
+
+static void proxy_release(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+
+ dma_fence_put(p->real);
+ dma_fence_free(&p->base);
+}
+
+const struct dma_fence_ops dma_fence_proxy_ops = {
+ .get_driver_name = proxy_get_driver_name,
+ .get_timeline_name = proxy_get_timeline_name,
+ .enable_signaling = proxy_enable_signaling,
+ .wait = dma_fence_default_wait,
+ .release = proxy_release,
+};
+EXPORT_SYMBOL_GPL(dma_fence_proxy_ops);
+
+/**
+ * dma_fence_create_proxy - Create an unset dma-fence
+ *
+ * dma_fence_create_proxy() creates a new dma_fence stub that is initially
+ * unsignaled and may later be replaced with a real fence. Any listeners
+ * to the proxy fence will be signaled when the target fence signals its
+ * completion.
+ */
+struct dma_fence *dma_fence_create_proxy(void)
+{
+ struct dma_fence_proxy *p;
+
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return NULL;
+
+ init_waitqueue_head(&p->wq);
+ dma_fence_init(&p->base, &dma_fence_proxy_ops, &p->wq.lock,
+ dma_fence_context_alloc(1), 0);
+ init_irq_work(&p->work, proxy_irq_work);
+
+ return &p->base;
+}
+EXPORT_SYMBOL(dma_fence_create_proxy);
+
+static void wrap_signal_locked(struct dma_fence *fence, struct dma_fence *real)
+{
+ if (real->error)
+ dma_fence_set_error(fence, real->error);
+ dma_fence_signal_locked(fence);
+}
+
+static void __wake_up_listeners(struct dma_fence_proxy *p)
+{
+ struct wait_queue_entry *wait, *next;
+
+ list_for_each_entry_safe(wait, next, &p->wq.head, entry) {
+ INIT_LIST_HEAD(&wait->entry);
+ wait->func(wait, TASK_NORMAL, 0, p->real);
+ }
+}
+
+static void proxy_assign(struct dma_fence *fence, struct dma_fence *real)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ unsigned long flags;
+
+ if (WARN_ON(fence == real))
+ return;
+
+ if (WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)))
+ return;
+
+ if (WARN_ON(p->real))
+ return;
+
+ spin_lock_irqsave(&p->wq.lock, flags);
+
+ if (unlikely(!real)) {
+ dma_fence_signal_locked(&p->base);
+ goto unlock;
+ }
+
+ p->real = dma_fence_get(real);
+
+ spin_lock_nested(real->lock, same_lockclass(&p->wq.lock, real->lock));
+ if (dma_fence_is_signaled(real)) {
+ wrap_signal_locked(&p->base, real);
+ } else if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+ &p->base.flags) &&
+ !__dma_fence_enable_signaling(real)) {
+ wrap_signal_locked(&p->base, real);
+ } else {
+ dma_fence_get(&p->base);
+ p->cb.func = proxy_callback;
+ list_add_tail(&p->cb.node, &real->cb_list);
+ }
+ spin_unlock(real->lock);
+
+unlock:
+ __wake_up_listeners(p);
+ spin_unlock_irqrestore(&p->wq.lock, flags);
+}
+
+/**
+ * dma_fence_replace_proxy - Replace the proxy fence with the real target
+ * @slot: pointer to location of fence to update
+ * @fence: the new fence to store in @slot
+ *
+ * Once the real dma_fence is known, we can replace the proxy fence holder
+ * with a pointer to the real dma fence. Future listeners will attach to
+ * the real fence, avoiding any indirection overhead. Previous listeners
+ * will remain attached to the proxy fence, and be signaled in turn when
+ * the target fence completes.
+ */
+struct dma_fence *
+dma_fence_replace_proxy(struct dma_fence __rcu **slot, struct dma_fence *fence)
+{
+ struct dma_fence *old;
+
+ if (fence)
+ dma_fence_get(fence);
+
+ old = rcu_replace_pointer(*slot, fence, true);
+ if (old && dma_fence_is_proxy(old))
+ proxy_assign(old, fence);
+
+ return old;
+}
+EXPORT_SYMBOL(dma_fence_replace_proxy);
+
+void dma_fence_add_proxy_listener(struct dma_fence *fence,
+ struct wait_queue_entry *wait)
+{
+ if (dma_fence_is_proxy(fence)) {
+ struct dma_fence_proxy *p =
+ container_of(fence, typeof(*p), base);
+ unsigned long flags;
+
+ spin_lock_irqsave(&p->wq.lock, flags);
+ if (!p->real) {
+ list_add_tail(&wait->entry, &p->wq.head);
+ wait = NULL;
+ }
+ fence = p->real;
+ spin_unlock_irqrestore(&p->wq.lock, flags);
+ }
+
+ if (wait) {
+ INIT_LIST_HEAD(&wait->entry);
+ wait->func(wait, TASK_NORMAL, 0, fence);
+ }
+}
+EXPORT_SYMBOL(dma_fence_add_proxy_listener);
+
+bool dma_fence_remove_proxy_listener(struct dma_fence *fence,
+ struct wait_queue_entry *wait)
+{
+ bool ret = false;
+
+ if (dma_fence_is_proxy(fence)) {
+ struct dma_fence_proxy *p =
+ container_of(fence, typeof(*p), base);
+ unsigned long flags;
+
+ spin_lock_irqsave(&p->wq.lock, flags);
+ if (!list_empty(&wait->entry)) {
+ list_del_init(&wait->entry);
+ ret = true;
+ }
+ spin_unlock_irqrestore(&p->wq.lock, flags);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(dma_fence_remove_proxy_listener);
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 052a41e2451c..fa7bedc6703d 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -19,6 +19,8 @@
#define CREATE_TRACE_POINTS
#include <trace/events/dma_fence.h>
+#include "dma-fence-private.h"
+
EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
@@ -273,7 +275,7 @@ void dma_fence_free(struct dma_fence *fence)
}
EXPORT_SYMBOL(dma_fence_free);
-static bool __dma_fence_enable_signaling(struct dma_fence *fence)
+bool __dma_fence_enable_signaling(struct dma_fence *fence)
{
bool was_set;
diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h
index 55918ef9adab..616eca70e2d8 100644
--- a/drivers/dma-buf/selftests.h
+++ b/drivers/dma-buf/selftests.h
@@ -12,3 +12,4 @@
selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */
selftest(dma_fence, dma_fence)
selftest(dma_fence_chain, dma_fence_chain)
+selftest(dma_fence_proxy, dma_fence_proxy)
diff --git a/drivers/dma-buf/st-dma-fence-proxy.c b/drivers/dma-buf/st-dma-fence-proxy.c
new file mode 100644
index 000000000000..c95811199c16
--- /dev/null
+++ b/drivers/dma-buf/st-dma-fence-proxy.c
@@ -0,0 +1,699 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-fence.h>
+#include <linux/dma-fence-proxy.h>
+#include <linux/kernel.h>
+#include <linux/sched/signal.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "selftest.h"
+
+static struct kmem_cache *slab_fences;
+
+static struct mock_fence {
+ struct dma_fence base;
+ spinlock_t lock;
+} *to_mock_fence(struct dma_fence *f) {
+ return container_of(f, struct mock_fence, base);
+}
+
+static const char *mock_name(struct dma_fence *f)
+{
+ return "mock";
+}
+
+static void mock_fence_release(struct dma_fence *f)
+{
+ kmem_cache_free(slab_fences, to_mock_fence(f));
+}
+
+static const struct dma_fence_ops mock_ops = {
+ .get_driver_name = mock_name,
+ .get_timeline_name = mock_name,
+ .release = mock_fence_release,
+};
+
+static struct dma_fence *mock_fence(void)
+{
+ struct mock_fence *f;
+
+ f = kmem_cache_alloc(slab_fences, GFP_KERNEL);
+ if (!f)
+ return NULL;
+
+ spin_lock_init(&f->lock);
+ dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0);
+
+ return &f->base;
+}
+
+static int sanitycheck(void *arg)
+{
+ struct dma_fence *f;
+
+ f = dma_fence_create_proxy();
+ if (!f)
+ return -ENOMEM;
+
+ dma_fence_signal(f);
+ dma_fence_put(f);
+
+ return 0;
+}
+
+struct fences {
+ struct dma_fence *real;
+ struct dma_fence *proxy;
+ struct dma_fence __rcu *slot;
+};
+
+static int create_fences(struct fences *f, bool attach)
+{
+ f->proxy = dma_fence_create_proxy();
+ if (!f->proxy)
+ return -ENOMEM;
+
+ RCU_INIT_POINTER(f->slot, f->proxy);
+
+ f->real = mock_fence();
+ if (!f->real) {
+ dma_fence_put(f->proxy);
+ return -ENOMEM;
+ }
+
+ if (attach)
+ dma_fence_replace_proxy(&f->slot, f->real);
+
+ return 0;
+}
+
+static void free_fences(struct fences *f)
+{
+ dma_fence_put(dma_fence_replace_proxy(&f->slot, NULL));
+ dma_fence_put(f->real);
+ dma_fence_put(f->proxy);
+}
+
+static int wrap_signaling(void *arg)
+{
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_is_signaled(f.proxy)) {
+ pr_err("Fence unexpectedly signaled on creation\n");
+ goto err_free;
+ }
+
+ if (dma_fence_signal(f.real)) {
+ pr_err("Fence reported being already signaled\n");
+ goto err_free;
+ }
+
+ if (!dma_fence_is_signaled(f.proxy)) {
+ pr_err("Fence not reporting signaled\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_signaling_recurse(void *arg)
+{
+ struct fences f;
+ struct dma_fence *chain;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ chain = dma_fence_create_proxy();
+ if (!chain) {
+ err = -ENOMEM;
+ goto err_free;
+ }
+
+ dma_fence_replace_proxy(&f.slot, chain);
+ dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real));
+ dma_fence_put(chain);
+
+ /* f.real <- chain <- f.proxy */
+
+ if (dma_fence_is_signaled(f.proxy)) {
+ pr_err("Fence unexpectedly signaled on creation\n");
+ goto err_free;
+ }
+
+ if (dma_fence_signal(f.real)) {
+ pr_err("Fence reported being already signaled\n");
+ goto err_free;
+ }
+
+ if (!dma_fence_is_signaled(f.proxy)) {
+ pr_err("Fence not reporting signaled\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+struct simple_cb {
+ struct dma_fence_cb cb;
+ bool seen;
+};
+
+static void simple_callback(struct dma_fence *f, struct dma_fence_cb *cb)
+{
+ smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true);
+}
+
+static int wrap_add_callback(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_add_callback_recurse(void *arg)
+{
+ struct simple_cb cb = {};
+ struct dma_fence *chain;
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ chain = dma_fence_create_proxy();
+ if (!chain) {
+ err = -ENOMEM;
+ goto err_free;
+ }
+
+ dma_fence_replace_proxy(&f.slot, chain);
+ dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real));
+ dma_fence_put(chain);
+
+ /* f.real <- chain <- f.proxy */
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_late_add_callback(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ dma_fence_signal(f.real);
+
+ if (!dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Added callback, but fence was already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (cb.seen) {
+ pr_err("Callback called after failed attachment!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_early_add_callback(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_replace_proxy(&f.slot, f.real);
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_early_add_callback_late(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ dma_fence_signal(f.real);
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_replace_proxy(&f.slot, f.real);
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_early_add_callback_early(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_replace_proxy(&f.slot, f.real);
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_rm_callback(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ if (!dma_fence_remove_callback(f.proxy, &cb.cb)) {
+ pr_err("Failed to remove callback!\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (cb.seen) {
+ pr_err("Callback still signaled after removal!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_late_rm_callback(void *arg)
+{
+ struct simple_cb cb = {};
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) {
+ pr_err("Failed to add callback, fence already signaled!\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (!cb.seen) {
+ pr_err("Callback failed!\n");
+ goto err_free;
+ }
+
+ if (dma_fence_remove_callback(f.proxy, &cb.cb)) {
+ pr_err("Callback removal succeed after being executed!\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_status(void *arg)
+{
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_get_status(f.proxy)) {
+ pr_err("Fence unexpectedly has signaled status on creation\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (!dma_fence_get_status(f.proxy)) {
+ pr_err("Fence not reporting signaled status\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_error(void *arg)
+{
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ dma_fence_set_error(f.real, -EIO);
+
+ if (dma_fence_get_status(f.proxy)) {
+ pr_err("Fence unexpectedly has error status before signal\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+ if (dma_fence_get_status(f.proxy) != -EIO) {
+ pr_err("Fence not reporting error status, got %d\n",
+ dma_fence_get_status(f.proxy));
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_wait(void *arg)
+{
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, true))
+ return -ENOMEM;
+
+ if (dma_fence_wait_timeout(f.proxy, false, 0) != 0) {
+ pr_err("Wait reported complete before being signaled\n");
+ goto err_free;
+ }
+
+ dma_fence_signal(f.real);
+
+ if (dma_fence_wait_timeout(f.proxy, false, 0) == 0) {
+ pr_err("Wait reported incomplete after being signaled\n");
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ dma_fence_signal(f.real);
+ free_fences(&f);
+ return err;
+}
+
+struct wait_timer {
+ struct timer_list timer;
+ struct fences f;
+};
+
+static void wait_timer(struct timer_list *timer)
+{
+ struct wait_timer *wt = from_timer(wt, timer, timer);
+
+ dma_fence_signal(wt->f.real);
+}
+
+static int wrap_wait_timeout(void *arg)
+{
+ struct wait_timer wt;
+ int err = -EINVAL;
+
+ if (create_fences(&wt.f, true))
+ return -ENOMEM;
+
+ timer_setup_on_stack(&wt.timer, wait_timer, 0);
+
+ if (dma_fence_wait_timeout(wt.f.proxy, false, 1) != 0) {
+ pr_err("Wait reported complete before being signaled\n");
+ goto err_free;
+ }
+
+ mod_timer(&wt.timer, jiffies + 1);
+
+ if (dma_fence_wait_timeout(wt.f.proxy, false, 2) != 0) {
+ if (timer_pending(&wt.timer)) {
+ pr_notice("Timer did not fire within the jiffie!\n");
+ err = 0; /* not our fault! */
+ } else {
+ pr_err("Wait reported incomplete after timeout\n");
+ }
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ del_timer_sync(&wt.timer);
+ destroy_timer_on_stack(&wt.timer);
+ dma_fence_signal(wt.f.real);
+ free_fences(&wt.f);
+ return err;
+}
+
+struct proxy_wait {
+ struct wait_queue_entry base;
+ struct dma_fence *fence;
+ bool seen;
+};
+
+static int proxy_wait_cb(struct wait_queue_entry *entry,
+ unsigned int mode, int flags, void *key)
+{
+ struct proxy_wait *p = container_of(entry, typeof(*p), base);
+
+ p->fence = key;
+ p->seen = true;
+
+ return 0;
+}
+
+static int wrap_listen_early(void *arg)
+{
+ struct proxy_wait wait = { .base.func = proxy_wait_cb };
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ dma_fence_replace_proxy(&f.slot, f.real);
+ dma_fence_add_proxy_listener(f.proxy, &wait.base);
+
+ if (!wait.seen) {
+ pr_err("Proxy listener was not called after replace!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ if (wait.fence != f.real) {
+ pr_err("Proxy listener was not passed the real fence!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ dma_fence_signal(f.real);
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_listen_late(void *arg)
+{
+ struct proxy_wait wait = { .base.func = proxy_wait_cb };
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ dma_fence_add_proxy_listener(f.proxy, &wait.base);
+ dma_fence_replace_proxy(&f.slot, f.real);
+
+ if (!wait.seen) {
+ pr_err("Proxy listener was not called on replace!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ if (wait.fence != f.real) {
+ pr_err("Proxy listener was not passed the real fence!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ dma_fence_signal(f.real);
+ free_fences(&f);
+ return err;
+}
+
+static int wrap_listen_cancel(void *arg)
+{
+ struct proxy_wait wait = { .base.func = proxy_wait_cb };
+ struct fences f;
+ int err = -EINVAL;
+
+ if (create_fences(&f, false))
+ return -ENOMEM;
+
+ dma_fence_add_proxy_listener(f.proxy, &wait.base);
+ if (!dma_fence_remove_proxy_listener(f.proxy, &wait.base)) {
+ pr_err("Cancelling listener, already detached?\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+ dma_fence_replace_proxy(&f.slot, f.real);
+
+ if (wait.seen) {
+ pr_err("Proxy listener was called after being removed!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ if (dma_fence_remove_proxy_listener(f.proxy, &wait.base)) {
+ pr_err("Double listener cancellation!\n");
+ err = -EINVAL;
+ goto err_free;
+ }
+
+ err = 0;
+err_free:
+ dma_fence_signal(f.real);
+ free_fences(&f);
+ return err;
+}
+
+int dma_fence_proxy(void)
+{
+ static const struct subtest tests[] = {
+ SUBTEST(sanitycheck),
+ SUBTEST(wrap_signaling),
+ SUBTEST(wrap_signaling_recurse),
+ SUBTEST(wrap_add_callback),
+ SUBTEST(wrap_add_callback_recurse),
+ SUBTEST(wrap_late_add_callback),
+ SUBTEST(wrap_early_add_callback),
+ SUBTEST(wrap_early_add_callback_late),
+ SUBTEST(wrap_early_add_callback_early),
+ SUBTEST(wrap_rm_callback),
+ SUBTEST(wrap_late_rm_callback),
+ SUBTEST(wrap_status),
+ SUBTEST(wrap_error),
+ SUBTEST(wrap_wait),
+ SUBTEST(wrap_wait_timeout),
+ SUBTEST(wrap_listen_early),
+ SUBTEST(wrap_listen_late),
+ SUBTEST(wrap_listen_cancel),
+ };
+ int ret;
+
+ slab_fences = KMEM_CACHE(mock_fence,
+ SLAB_TYPESAFE_BY_RCU |
+ SLAB_HWCACHE_ALIGN);
+ if (!slab_fences)
+ return -ENOMEM;
+
+ ret = subtests(tests, NULL);
+
+ kmem_cache_destroy(slab_fences);
+
+ return ret;
+}
diff --git a/include/linux/dma-fence-proxy.h b/include/linux/dma-fence-proxy.h
new file mode 100644
index 000000000000..063cde6b42c4
--- /dev/null
+++ b/include/linux/dma-fence-proxy.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * dma-fence-proxy: allows waiting upon unset and future fences
+ *
+ * Copyright (C) 2017 Intel Corporation
+ */
+
+#ifndef __LINUX_DMA_FENCE_PROXY_H
+#define __LINUX_DMA_FENCE_PROXY_H
+
+#include <linux/kernel.h>
+#include <linux/dma-fence.h>
+
+struct wait_queue_entry;
+
+extern const struct dma_fence_ops dma_fence_proxy_ops;
+
+struct dma_fence *dma_fence_create_proxy(void);
+
+static inline bool dma_fence_is_proxy(struct dma_fence *fence)
+{
+ return fence->ops == &dma_fence_proxy_ops;
+}
+
+struct dma_fence *
+dma_fence_replace_proxy(struct dma_fence __rcu **slot,
+ struct dma_fence *fence);
+
+void dma_fence_add_proxy_listener(struct dma_fence *fence,
+ struct wait_queue_entry *wait);
+bool dma_fence_remove_proxy_listener(struct dma_fence *fence,
+ struct wait_queue_entry *wait);
+
+#endif /* __LINUX_DMA_FENCE_PROXY_H */
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/syncobj: Allow use of dma-fence-proxy
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] " Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 2/6] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
` (8 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/drm_syncobj.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 42d46414f767..e141db0e1eb6 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -184,6 +184,7 @@
*/
#include <linux/anon_inodes.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/file.h>
#include <linux/fs.h>
#include <linux/sched/signal.h>
@@ -324,14 +325,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
struct dma_fence *old_fence;
struct syncobj_wait_entry *cur, *tmp;
- if (fence)
- dma_fence_get(fence);
-
spin_lock(&syncobj->lock);
- old_fence = rcu_dereference_protected(syncobj->fence,
- lockdep_is_held(&syncobj->lock));
- rcu_assign_pointer(syncobj->fence, fence);
+ old_fence = dma_fence_replace_proxy(&syncobj->fence, fence);
if (fence != old_fence) {
list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node)
--
2.20.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (2 preceding siblings ...)
2020-05-04 13:50 ` [Intel-gfx] [PATCH 3/6] drm/syncobj: Allow use of dma-fence-proxy Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-05 13:48 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-05-05 15:02 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 5/6] drm/i915/gem: Allow combining submit-fences with syncobj Chris Wilson
` (7 subsequent siblings)
11 siblings, 2 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 +++-
drivers/gpu/drm/i915/i915_request.c | 113 ++++++++++++++++++
2 files changed, 132 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cce7df231cb9..71e4dbf7b9a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
*/
#include <linux/intel-iommu.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/dma-resv.h>
#include <linux/sync_file.h>
#include <linux/uaccess.h>
@@ -2472,8 +2473,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
+ if (!fence) {
+ struct dma_fence *old;
+
+ fence = dma_fence_create_proxy();
+ if (!fence)
+ return -ENOMEM;
+
+ spin_lock(&syncobj->lock);
+ old = rcu_dereference_protected(syncobj->fence, true);
+ if (unlikely(old)) {
+ dma_fence_put(fence);
+ fence = dma_fence_get(old);
+ } else {
+ rcu_assign_pointer(syncobj->fence,
+ dma_fence_get(fence));
+ }
+ spin_unlock(&syncobj->lock);
+ }
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 95edc5523a01..8583fe5bb3b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -23,6 +23,7 @@
*/
#include <linux/dma-fence-array.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/irq_work.h>
#include <linux/prefetch.h>
#include <linux/sched.h>
@@ -1065,6 +1066,116 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
}
+struct await_proxy {
+ struct wait_queue_entry base;
+ struct i915_request *request;
+ struct dma_fence *fence;
+ struct timer_list timer;
+ struct work_struct work;
+ int (*attach)(struct await_proxy *ap);
+ void *data;
+};
+
+static void await_proxy_work(struct work_struct *work)
+{
+ struct await_proxy *ap = container_of(work, typeof(*ap), work);
+ struct i915_request *rq = ap->request;
+ int err;
+
+ del_timer_sync(&ap->timer);
+
+ if (ap->fence) {
+ mutex_lock(&rq->context->timeline->mutex);
+ err = ap->attach(ap);
+ mutex_unlock(&rq->context->timeline->mutex);
+ if (err < 0)
+ i915_sw_fence_set_error_once(&rq->submit, err);
+ }
+
+ i915_sw_fence_complete(&rq->submit);
+
+ dma_fence_put(ap->fence);
+ kfree(ap);
+}
+
+static int
+await_proxy_wake(struct wait_queue_entry *entry,
+ unsigned int mode,
+ int flags,
+ void *fence)
+{
+ struct await_proxy *ap = container_of(entry, typeof(*ap), base);
+
+ ap->fence = dma_fence_get(fence);
+ schedule_work(&ap->work);
+
+ return 0;
+}
+
+static void
+await_proxy_timer(struct timer_list *t)
+{
+ struct await_proxy *ap = container_of(t, typeof(*ap), timer);
+
+ if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) {
+ struct i915_request *rq = ap->request;
+
+ pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n",
+ rq->fence.ops->get_driver_name(&rq->fence),
+ rq->fence.ops->get_timeline_name(&rq->fence),
+ rq->fence.seqno);
+ i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT);
+
+ schedule_work(&ap->work);
+ }
+}
+
+static int
+__i915_request_await_proxy(struct i915_request *rq,
+ struct dma_fence *fence,
+ unsigned long timeout,
+ int (*attach)(struct await_proxy *ap),
+ void *data)
+{
+ struct await_proxy *ap;
+
+ ap = kzalloc(sizeof(*ap), I915_FENCE_GFP);
+ if (!ap)
+ return -ENOMEM;
+
+ i915_sw_fence_await(&rq->submit);
+
+ ap->base.private = fence;
+ ap->base.func = await_proxy_wake;
+ ap->request = rq;
+ INIT_WORK(&ap->work, await_proxy_work);
+ ap->attach = attach;
+ ap->data = data;
+
+ timer_setup(&ap->timer, await_proxy_timer, 0);
+ if (timeout)
+ mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout));
+
+ dma_fence_add_proxy_listener(fence, &ap->base);
+ return 0;
+}
+
+static int await_proxy(struct await_proxy *ap)
+{
+ return i915_request_await_dma_fence(ap->request, ap->fence);
+}
+
+static int
+i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence)
+{
+ /*
+ * Wait until we know the real fence so that can optimise the
+ * inter-fence synchronisation.
+ */
+ return __i915_request_await_proxy(rq, fence, I915_FENCE_TIMEOUT,
+ await_proxy, NULL);
+}
+
int
i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
{
@@ -1111,6 +1222,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
if (dma_fence_is_i915(fence))
ret = i915_request_await_request(rq, to_request(fence));
+ else if (dma_fence_is_proxy(fence))
+ ret = i915_request_await_proxy(rq, fence);
else
ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
fence->context ? I915_FENCE_TIMEOUT : 0,
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915/gem: Allow combining submit-fences with syncobj
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (3 preceding siblings ...)
2020-05-04 13:50 ` [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
` (6 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson
We allow exported sync_file fences to be used as submit fences, but they
are not the only source of user fences. We also accept an array of
syncobj, and as with sync_file these are dma_fences underneath and so
feature the same set of controls. The submit-fence allows for a request
to be scheduled at the same time as the signaler, rather than as normal
after. Userspace can combine submit-fence with its own semaphores for
intra-batch scheduling.
Not exposing submit-fences to syncobj was at the time just a matter of
pragmatic expediency.
Fixes: a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf")
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 14 ++++++----
drivers/gpu/drm/i915/i915_request.c | 26 ++++++++++++++++++-
include/uapi/drm/i915_drm.h | 7 ++---
3 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 71e4dbf7b9a8..a47aa33e722e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2380,7 +2380,7 @@ static void
__free_fence_array(struct drm_syncobj **fences, unsigned int n)
{
while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ drm_syncobj_put(ptr_mask_bits(fences[n], 3));
kvfree(fences);
}
@@ -2437,7 +2437,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
- fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+ fences[n] = ptr_pack_bits(syncobj, fence.flags, 3);
}
return fences;
@@ -2468,7 +2468,7 @@ await_fence_array(struct i915_execbuffer *eb,
struct dma_fence *fence;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n], &flags, 3);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
@@ -2492,7 +2492,11 @@ await_fence_array(struct i915_execbuffer *eb,
spin_unlock(&syncobj->lock);
}
- err = i915_request_await_dma_fence(eb->request, fence);
+ if (flags & I915_EXEC_FENCE_WAIT_SUBMIT)
+ err = i915_request_await_execution(eb->request, fence,
+ eb->engine->bond_execute);
+ else
+ err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
if (err < 0)
return err;
@@ -2513,7 +2517,7 @@ signal_fence_array(struct i915_execbuffer *eb,
struct drm_syncobj *syncobj;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n], &flags, 3);
if (!(flags & I915_EXEC_FENCE_SIGNAL))
continue;
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 8583fe5bb3b6..92fa5267bcce 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1326,6 +1326,26 @@ __i915_request_await_execution(struct i915_request *to,
&from->fence);
}
+static int execution_proxy(struct await_proxy *ap)
+{
+ return i915_request_await_execution(ap->request, ap->fence, ap->data);
+}
+
+static int
+i915_request_await_proxy_execution(struct i915_request *rq,
+ struct dma_fence *fence,
+ void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal))
+{
+ /*
+ * We have to wait until the real request is known in order to
+ * be able to hook into its execution, as opposed to waiting for
+ * its completion.
+ */
+ return __i915_request_await_proxy(rq, fence, I915_FENCE_TIMEOUT,
+ execution_proxy, hook);
+}
+
int
i915_request_await_execution(struct i915_request *rq,
struct dma_fence *fence,
@@ -1362,10 +1382,14 @@ i915_request_await_execution(struct i915_request *rq,
ret = __i915_request_await_execution(rq,
to_request(fence),
hook);
+ else if (dma_fence_is_proxy(fence))
+ ret = i915_request_await_proxy_execution(rq,
+ fence,
+ hook);
else
ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
I915_FENCE_TIMEOUT,
- GFP_KERNEL);
+ I915_FENCE_GFP);
if (ret < 0)
return ret;
} while (--nchild);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 14b67cd6b54b..704dd0e3bc1d 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1040,9 +1040,10 @@ struct drm_i915_gem_exec_fence {
*/
__u32 handle;
-#define I915_EXEC_FENCE_WAIT (1<<0)
-#define I915_EXEC_FENCE_SIGNAL (1<<1)
-#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
+#define I915_EXEC_FENCE_WAIT (1u << 0)
+#define I915_EXEC_FENCE_SIGNAL (1u << 1)
+#define I915_EXEC_FENCE_WAIT_SUBMIT (1u << 2)
+#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_WAIT_SUBMIT << 1))
__u32 flags;
};
--
2.20.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915/gt: Declare when we enabled timeslicing
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (4 preceding siblings ...)
2020-05-04 13:50 ` [Intel-gfx] [PATCH 5/6] drm/i915/gem: Allow combining submit-fences with syncobj Chris Wilson
@ 2020-05-04 13:50 ` Chris Wilson
2020-05-04 13:54 ` [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (5 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth, Chris Wilson
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..8415511f1465 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
MAP(HAS_PREEMPTION, PREEMPTION),
MAP(HAS_SEMAPHORES, SEMAPHORES),
MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
+ MAP(HAS_TIMESLICES, TIMESLICING),
#undef MAP
};
struct intel_engine_cs *engine;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 704dd0e3bc1d..1ee227b5131a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.20.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] Wait-for-submit on future syncobj
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (5 preceding siblings ...)
2020-05-04 13:50 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
@ 2020-05-04 13:54 ` Chris Wilson
2020-05-04 14:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-04 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: kenneth
Quoting Chris Wilson (2020-05-04 14:50:24)
> A simplified example of out-of-order execution that is required by iris:
>
> struct drm_i915_gem_exec_object2 obj = {
> .offset = 24 << 20,
> .handle = future_submit_batch(i915, 24 << 20),
> .flags = EXEC_OBJECT_PINNED,
> };
> struct drm_i915_gem_exec_fence fence = {
> .handle = syncobj_create(i915, 0),
> };
> struct drm_i915_gem_execbuffer2 execbuf = {
> .buffers_ptr = to_user_pointer(&obj),
> .buffer_count = 1,
> .cliprects_ptr = to_user_pointer(&fence),
> .num_cliprects = 1,
> .flags = engine | I915_EXEC_FENCE_ARRAY,
> };
> uint32_t result;
> int out;
>
> /*
> * Here we submit client A waiting on client B, but internally client
> * B has a semaphore that waits on client A. This relies on timeslicing
> * to reorder B before A, even though userspace has asked to submit
A before B
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (6 preceding siblings ...)
2020-05-04 13:54 ` [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
@ 2020-05-04 14:41 ` Patchwork
2020-05-04 15:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-05-04 14:41 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
URL : https://patchwork.freedesktop.org/series/76912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aa08f9739363 drm/i915: Mark concurrent submissions with a weak-dependency
55c216ab5caf dma-buf: Proxy fence, an unsignaled fence placeholder
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
new file mode 100644
-:387: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#387: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20:
+ spinlock_t lock;
-:547: WARNING:MEMORY_BARRIER: memory barrier without comment
#547: FILE: drivers/dma-buf/st-dma-fence-proxy.c:180:
+ smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true);
total: 0 errors, 2 warnings, 1 checks, 1050 lines checked
2f097bd40cbf drm/syncobj: Allow use of dma-fence-proxy
09b46dbf7d9f drm/i915/gem: Teach execbuf how to wait on future syncobj
ce52e4177208 drm/i915/gem: Allow combining submit-fences with syncobj
8bd2f81ece02 drm/i915/gt: Declare when we enabled timeslicing
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (7 preceding siblings ...)
2020-05-04 14:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency Patchwork
@ 2020-05-04 15:08 ` Patchwork
2020-05-05 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3) Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-05-04 15:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
URL : https://patchwork.freedesktop.org/series/76912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8419 -> Patchwork_17569
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17569 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17569, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17569:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-icl-u2/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-icl-u2/igt@i915_selftest@live@execlists.html
New tests
---------
New tests have been introduced between CI_DRM_8419 and Patchwork_17569:
### New IGT tests (1) ###
* igt@dmabuf@all@dma_fence_proxy:
- Statuses : 40 pass(s)
- Exec time: [0.03, 0.10] s
Known issues
------------
Here are the changes found in Patchwork_17569 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][3] ([i915#262]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* {igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1}:
- fi-pnv-d510: [FAIL][5] ([i915#34]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
Participating hosts (51 -> 44)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8419 -> Patchwork_17569
CI-20190529: 20190529
CI_DRM_8419: 4331ff197d0a7330c311830569aee90bab940694 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17569: 8bd2f81ece028dc8a4c91f64d193d7f563ddcc64 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8bd2f81ece02 drm/i915/gt: Declare when we enabled timeslicing
ce52e4177208 drm/i915/gem: Allow combining submit-fences with syncobj
09b46dbf7d9f drm/i915/gem: Teach execbuf how to wait on future syncobj
2f097bd40cbf drm/syncobj: Allow use of dma-fence-proxy
55c216ab5caf dma-buf: Proxy fence, an unsignaled fence placeholder
aa08f9739363 drm/i915: Mark concurrent submissions with a weak-dependency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gem: Teach execbuf how to wait on future syncobj
2020-05-04 13:50 ` [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
@ 2020-05-05 13:48 ` Chris Wilson
2020-05-05 13:53 ` Chris Wilson
2020-05-05 15:02 ` Chris Wilson
1 sibling, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2020-05-05 13:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 ++-
drivers/gpu/drm/i915/i915_request.c | 146 ++++++++++++++++++
2 files changed, 165 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 966523a8503f..7abb96505a31 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
*/
#include <linux/intel-iommu.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/dma-resv.h>
#include <linux/sync_file.h>
#include <linux/uaccess.h>
@@ -2524,8 +2525,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
+ if (!fence) {
+ struct dma_fence *old;
+
+ fence = dma_fence_create_proxy();
+ if (!fence)
+ return -ENOMEM;
+
+ spin_lock(&syncobj->lock);
+ old = rcu_dereference_protected(syncobj->fence, true);
+ if (unlikely(old)) {
+ dma_fence_put(fence);
+ fence = dma_fence_get(old);
+ } else {
+ rcu_assign_pointer(syncobj->fence,
+ dma_fence_get(fence));
+ }
+ spin_unlock(&syncobj->lock);
+ }
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index d369b25e46bb..f7ef9fd178a0 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -23,6 +23,7 @@
*/
#include <linux/dma-fence-array.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/irq_work.h>
#include <linux/prefetch.h>
#include <linux/sched.h>
@@ -1065,6 +1066,149 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
}
+struct await_proxy {
+ struct wait_queue_entry base;
+ struct i915_request *request;
+ struct dma_fence *fence;
+ struct timer_list timer;
+ struct work_struct work;
+ int (*attach)(struct await_proxy *ap);
+ void *data;
+};
+
+static void await_proxy_work(struct work_struct *work)
+{
+ struct await_proxy *ap = container_of(work, typeof(*ap), work);
+ struct i915_request *rq = ap->request;
+
+ del_timer_sync(&ap->timer);
+
+ if (ap->fence) {
+ int err = 0;
+
+ /*
+ * If the fence is external, we impose a 10s timeout.
+ * However, if the fence is internal, we skip a timeout in
+ * the belief that all fences are in-order (DAG, no cycles)
+ * and we can enforce forward progress by reset the GPU if
+ * necessary. A future fence, provided userspace, can trivially
+ * generate a cycle in the dependency graph, and so cause
+ * that entire cycle to become deadlocked and for no forward
+ * progress to either be made, and the driver being kept
+ * eternally awake.
+ *
+ * While we do have a full DAG-verifier in the i915_sw_fence
+ * debug code, that is perhaps prohibitiverly expensive
+ * (and is necessarily global), so we replace that by
+ * checking to see if the endpoints have a recorded cycle.
+ */
+ if (dma_fence_is_i915(ap->fence)) {
+ struct i915_request *signal = to_request(ap->fence);
+
+ rcu_read_lock();
+ if (intel_timeline_sync_is_later(rcu_dereference(signal->timeline),
+ &rq->fence)) {
+ i915_sw_fence_set_error_once(&signal->submit,
+ -EDEADLK);
+ err = -EDEADLK;
+ }
+ rcu_read_unlock();
+ }
+
+ if (!err) {
+ mutex_lock(&rq->context->timeline->mutex);
+ err = ap->attach(ap);
+ mutex_unlock(&rq->context->timeline->mutex);
+ }
+
+ if (err < 0)
+ i915_sw_fence_set_error_once(&rq->submit, err);
+ }
+
+ i915_sw_fence_complete(&rq->submit);
+
+ dma_fence_put(ap->fence);
+ kfree(ap);
+}
+
+static int
+await_proxy_wake(struct wait_queue_entry *entry,
+ unsigned int mode,
+ int flags,
+ void *fence)
+{
+ struct await_proxy *ap = container_of(entry, typeof(*ap), base);
+
+ ap->fence = dma_fence_get(fence);
+ schedule_work(&ap->work);
+
+ return 0;
+}
+
+static void
+await_proxy_timer(struct timer_list *t)
+{
+ struct await_proxy *ap = container_of(t, typeof(*ap), timer);
+
+ if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) {
+ struct i915_request *rq = ap->request;
+
+ pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n",
+ rq->fence.ops->get_driver_name(&rq->fence),
+ rq->fence.ops->get_timeline_name(&rq->fence),
+ rq->fence.seqno);
+ i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT);
+
+ schedule_work(&ap->work);
+ }
+}
+
+static int
+__i915_request_await_proxy(struct i915_request *rq,
+ struct dma_fence *fence,
+ unsigned long timeout,
+ int (*attach)(struct await_proxy *ap),
+ void *data)
+{
+ struct await_proxy *ap;
+
+ ap = kzalloc(sizeof(*ap), I915_FENCE_GFP);
+ if (!ap)
+ return -ENOMEM;
+
+ i915_sw_fence_await(&rq->submit);
+
+ ap->base.private = fence;
+ ap->base.func = await_proxy_wake;
+ ap->request = rq;
+ INIT_WORK(&ap->work, await_proxy_work);
+ ap->attach = attach;
+ ap->data = data;
+
+ timer_setup(&ap->timer, await_proxy_timer, 0);
+ if (timeout)
+ mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout));
+
+ dma_fence_add_proxy_listener(fence, &ap->base);
+ return 0;
+}
+
+static int await_proxy(struct await_proxy *ap)
+{
+ return i915_request_await_dma_fence(ap->request, ap->fence);
+}
+
+static int
+i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence)
+{
+ /*
+ * Wait until we know the real fence so that can optimise the
+ * inter-fence synchronisation.
+ */
+ return __i915_request_await_proxy(rq, fence, I915_FENCE_TIMEOUT,
+ await_proxy, NULL);
+}
+
int
i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
{
@@ -1111,6 +1255,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
if (dma_fence_is_i915(fence))
ret = i915_request_await_request(rq, to_request(fence));
+ else if (dma_fence_is_proxy(fence))
+ ret = i915_request_await_proxy(rq, fence);
else
ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
fence->context ? I915_FENCE_TIMEOUT : 0,
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gem: Teach execbuf how to wait on future syncobj
2020-05-05 13:48 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-05-05 13:53 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-05 13:53 UTC (permalink / raw)
To: intel-gfx
Quoting Chris Wilson (2020-05-05 14:48:19)
> +static void await_proxy_work(struct work_struct *work)
> +{
> + struct await_proxy *ap = container_of(work, typeof(*ap), work);
> + struct i915_request *rq = ap->request;
> +
> + del_timer_sync(&ap->timer);
> +
> + if (ap->fence) {
> + int err = 0;
> +
> + /*
> + * If the fence is external, we impose a 10s timeout.
> + * However, if the fence is internal, we skip a timeout in
> + * the belief that all fences are in-order (DAG, no cycles)
> + * and we can enforce forward progress by reset the GPU if
> + * necessary. A future fence, provided userspace, can trivially
> + * generate a cycle in the dependency graph, and so cause
> + * that entire cycle to become deadlocked and for no forward
> + * progress to either be made, and the driver being kept
> + * eternally awake.
> + *
> + * While we do have a full DAG-verifier in the i915_sw_fence
> + * debug code, that is perhaps prohibitiverly expensive
> + * (and is necessarily global), so we replace that by
> + * checking to see if the endpoints have a recorded cycle.
> + */
> + if (dma_fence_is_i915(ap->fence)) {
> + struct i915_request *signal = to_request(ap->fence);
> +
> + rcu_read_lock();
> + if (intel_timeline_sync_is_later(rcu_dereference(signal->timeline),
> + &rq->fence)) {
> + i915_sw_fence_set_error_once(&signal->submit,
> + -EDEADLK);
> + err = -EDEADLK;
> + }
> + rcu_read_unlock();
End points are not enough. It covers the trivial example I made for
testing, but only that. I think for this to be safe we do need the full
DAG verifier. Oh well, by the time Tvrtko has finished complaining about
it being recursive it might not be so terrible.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gem: Teach execbuf how to wait on future syncobj
2020-05-04 13:50 ` [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
2020-05-05 13:48 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-05-05 15:02 ` Chris Wilson
1 sibling, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2020-05-05 15:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 ++-
drivers/gpu/drm/i915/i915_request.c | 133 ++++++++++++++++++
drivers/gpu/drm/i915/i915_scheduler.c | 41 ++++++
drivers/gpu/drm/i915/i915_scheduler.h | 3 +
4 files changed, 196 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 966523a8503f..7abb96505a31 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
*/
#include <linux/intel-iommu.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/dma-resv.h>
#include <linux/sync_file.h>
#include <linux/uaccess.h>
@@ -2524,8 +2525,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
+ if (!fence) {
+ struct dma_fence *old;
+
+ fence = dma_fence_create_proxy();
+ if (!fence)
+ return -ENOMEM;
+
+ spin_lock(&syncobj->lock);
+ old = rcu_dereference_protected(syncobj->fence, true);
+ if (unlikely(old)) {
+ dma_fence_put(fence);
+ fence = dma_fence_get(old);
+ } else {
+ rcu_assign_pointer(syncobj->fence,
+ dma_fence_get(fence));
+ }
+ spin_unlock(&syncobj->lock);
+ }
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index d369b25e46bb..9c5de07db47d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -23,6 +23,7 @@
*/
#include <linux/dma-fence-array.h>
+#include <linux/dma-fence-proxy.h>
#include <linux/irq_work.h>
#include <linux/prefetch.h>
#include <linux/sched.h>
@@ -1065,6 +1066,136 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
}
+struct await_proxy {
+ struct wait_queue_entry base;
+ struct i915_request *request;
+ struct dma_fence *fence;
+ struct timer_list timer;
+ struct work_struct work;
+ int (*attach)(struct await_proxy *ap);
+ void *data;
+};
+
+static void await_proxy_work(struct work_struct *work)
+{
+ struct await_proxy *ap = container_of(work, typeof(*ap), work);
+ struct i915_request *rq = ap->request;
+
+ del_timer_sync(&ap->timer);
+
+ if (ap->fence) {
+ int err = 0;
+
+ /*
+ * If the fence is external, we impose a 10s timeout.
+ * However, if the fence is internal, we skip a timeout in
+ * the belief that all fences are in-order (DAG, no cycles)
+ * and we can enforce forward progress by reset the GPU if
+ * necessary. A future fence, provided userspace, can trivially
+ * generate a cycle in the dependency graph, and so cause
+ * that entire cycle to become deadlocked and for no forward
+ * progress to either be made, and the driver being kept
+ * eternally awake.
+ */
+ if (dma_fence_is_i915(ap->fence) &&
+ !i915_sched_node_verify_dag(&rq->sched,
+ &to_request(ap->fence)->sched))
+ err = -EDEADLK;
+
+ if (!err) {
+ mutex_lock(&rq->context->timeline->mutex);
+ err = ap->attach(ap);
+ mutex_unlock(&rq->context->timeline->mutex);
+ }
+
+ if (err < 0)
+ i915_sw_fence_set_error_once(&rq->submit, err);
+ }
+
+ i915_sw_fence_complete(&rq->submit);
+
+ dma_fence_put(ap->fence);
+ kfree(ap);
+}
+
+static int
+await_proxy_wake(struct wait_queue_entry *entry,
+ unsigned int mode,
+ int flags,
+ void *fence)
+{
+ struct await_proxy *ap = container_of(entry, typeof(*ap), base);
+
+ ap->fence = dma_fence_get(fence);
+ schedule_work(&ap->work);
+
+ return 0;
+}
+
+static void
+await_proxy_timer(struct timer_list *t)
+{
+ struct await_proxy *ap = container_of(t, typeof(*ap), timer);
+
+ if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) {
+ struct i915_request *rq = ap->request;
+
+ pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n",
+ rq->fence.ops->get_driver_name(&rq->fence),
+ rq->fence.ops->get_timeline_name(&rq->fence),
+ rq->fence.seqno);
+ i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT);
+
+ schedule_work(&ap->work);
+ }
+}
+
+static int
+__i915_request_await_proxy(struct i915_request *rq,
+ struct dma_fence *fence,
+ unsigned long timeout,
+ int (*attach)(struct await_proxy *ap),
+ void *data)
+{
+ struct await_proxy *ap;
+
+ ap = kzalloc(sizeof(*ap), I915_FENCE_GFP);
+ if (!ap)
+ return -ENOMEM;
+
+ i915_sw_fence_await(&rq->submit);
+
+ ap->base.private = fence;
+ ap->base.func = await_proxy_wake;
+ ap->request = rq;
+ INIT_WORK(&ap->work, await_proxy_work);
+ ap->attach = attach;
+ ap->data = data;
+
+ timer_setup(&ap->timer, await_proxy_timer, 0);
+ if (timeout)
+ mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout));
+
+ dma_fence_add_proxy_listener(fence, &ap->base);
+ return 0;
+}
+
+static int await_proxy(struct await_proxy *ap)
+{
+ return i915_request_await_dma_fence(ap->request, ap->fence);
+}
+
+static int
+i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence)
+{
+ /*
+ * Wait until we know the real fence so that can optimise the
+ * inter-fence synchronisation.
+ */
+ return __i915_request_await_proxy(rq, fence, I915_FENCE_TIMEOUT,
+ await_proxy, NULL);
+}
+
int
i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
{
@@ -1111,6 +1242,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
if (dma_fence_is_i915(fence))
ret = i915_request_await_request(rq, to_request(fence));
+ else if (dma_fence_is_proxy(fence))
+ ret = i915_request_await_proxy(rq, fence);
else
ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
fence->context ? I915_FENCE_TIMEOUT : 0,
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 5f4c1e49e974..ad6c4363eaa6 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -484,6 +484,47 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
return 0;
}
+bool i915_sched_node_verify_dag(struct i915_sched_node *waiter,
+ struct i915_sched_node *signaler)
+{
+ struct i915_dependency *dep, *p;
+ struct i915_dependency stack;
+ bool result = false;
+ LIST_HEAD(dfs);
+
+ if (waiter == signaler)
+ return true;
+
+ spin_lock_irq(&schedule_lock);
+
+ stack.signaler = signaler;
+ list_add(&stack.dfs_link, &dfs);
+
+ list_for_each_entry(dep, &dfs, dfs_link) {
+ struct i915_sched_node *node = dep->signaler;
+
+ if (node_signaled(node))
+ continue;
+
+ list_for_each_entry(p, &node->signalers_list, signal_link) {
+ if (p->signaler == waiter)
+ goto out;
+
+ if (list_empty(&p->dfs_link))
+ list_add_tail(&p->dfs_link, &dfs);
+ }
+ }
+
+ result = true;
+out:
+ list_for_each_entry_safe(dep, p, &dfs, dfs_link)
+ INIT_LIST_HEAD(&dep->dfs_link);
+
+ spin_unlock_irq(&schedule_lock);
+
+ return result;
+}
+
void i915_sched_node_fini(struct i915_sched_node *node)
{
struct i915_dependency *dep, *tmp;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 6f0bf00fc569..13432add8929 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -28,6 +28,9 @@
void i915_sched_node_init(struct i915_sched_node *node);
void i915_sched_node_reinit(struct i915_sched_node *node);
+bool i915_sched_node_verify_dag(struct i915_sched_node *waiter,
+ struct i915_sched_node *signal);
+
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
struct i915_sched_node *signal,
struct i915_dependency *dep,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (8 preceding siblings ...)
2020-05-04 15:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-05-05 16:00 ` Patchwork
2020-05-05 16:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-06 4:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-05-05 16:00 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
URL : https://patchwork.freedesktop.org/series/76912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d336bdf650f8 drm/i915: Mark concurrent submissions with a weak-dependency
19243ac2eee1 dma-buf: Proxy fence, an unsignaled fence placeholder
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
new file mode 100644
-:387: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#387: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20:
+ spinlock_t lock;
-:547: WARNING:MEMORY_BARRIER: memory barrier without comment
#547: FILE: drivers/dma-buf/st-dma-fence-proxy.c:180:
+ smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true);
total: 0 errors, 2 warnings, 1 checks, 1050 lines checked
f3138b0d84f7 drm/syncobj: Allow use of dma-fence-proxy
e796d58b1084 drm/i915/gem: Teach execbuf how to wait on future syncobj
f3459c71c608 drm/i915/gem: Allow combining submit-fences with syncobj
7e5f8efa9a8d drm/i915/gt: Declare when we enabled timeslicing
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (9 preceding siblings ...)
2020-05-05 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3) Patchwork
@ 2020-05-05 16:24 ` Patchwork
2020-05-06 4:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-05-05 16:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
URL : https://patchwork.freedesktop.org/series/76912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8430 -> Patchwork_17584
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/index.html
New tests
---------
New tests have been introduced between CI_DRM_8430 and Patchwork_17584:
### New IGT tests (1) ###
* igt@dmabuf@all@dma_fence_proxy:
- Statuses : 40 pass(s)
- Exec time: [0.02, 0.09] s
Changes
-------
No changes found
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8430 -> Patchwork_17584
CI-20190529: 20190529
CI_DRM_8430: 2daa6f8cad645f49a898158190a20a893b4aabe3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5632: e630cb8cd2ec01d6d5358eb2a3f6ea70498b8183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17584: 7e5f8efa9a8d423a289def24f06bd53489a08ad2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7e5f8efa9a8d drm/i915/gt: Declare when we enabled timeslicing
f3459c71c608 drm/i915/gem: Allow combining submit-fences with syncobj
e796d58b1084 drm/i915/gem: Teach execbuf how to wait on future syncobj
f3138b0d84f7 drm/syncobj: Allow use of dma-fence-proxy
19243ac2eee1 dma-buf: Proxy fence, an unsignaled fence placeholder
d336bdf650f8 drm/i915: Mark concurrent submissions with a weak-dependency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
` (10 preceding siblings ...)
2020-05-05 16:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-06 4:44 ` Patchwork
11 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-05-06 4:44 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3)
URL : https://patchwork.freedesktop.org/series/76912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8430_full -> Patchwork_17584_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17584_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_fence@parallel@bcs0}:
- shard-tglb: [PASS][1] -> [FAIL][2] +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-tglb6/igt@gem_exec_fence@parallel@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-tglb5/igt@gem_exec_fence@parallel@bcs0.html
* {igt@gem_exec_fence@syncobj-invalid-wait}:
- shard-snb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-snb5/igt@gem_exec_fence@syncobj-invalid-wait.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-snb2/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-skl: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl8/igt@gem_exec_fence@syncobj-invalid-wait.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl10/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-glk: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-glk8/igt@gem_exec_fence@syncobj-invalid-wait.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-glk1/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-apl: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl8/igt@gem_exec_fence@syncobj-invalid-wait.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl4/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-kbl: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl2/igt@gem_exec_fence@syncobj-invalid-wait.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-kbl7/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-iclb: [PASS][13] -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb1/igt@gem_exec_fence@syncobj-invalid-wait.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-iclb1/igt@gem_exec_fence@syncobj-invalid-wait.html
- shard-hsw: [PASS][15] -> [FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-hsw4/igt@gem_exec_fence@syncobj-invalid-wait.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-hsw2/igt@gem_exec_fence@syncobj-invalid-wait.html
New tests
---------
New tests have been introduced between CI_DRM_8430_full and Patchwork_17584_full:
### New IGT tests (1) ###
* igt@dmabuf@all@dma_fence_proxy:
- Statuses : 8 pass(s)
- Exec time: [0.03, 0.10] s
Known issues
------------
Here are the changes found in Patchwork_17584_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([CI#80])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb5/igt@gem_exec_whisper@basic-contexts-forked-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-iclb7/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#300])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- shard-apl: [PASS][21] -> [FAIL][22] ([i915#70])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl3/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl7/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
- shard-kbl: [PASS][23] -> [FAIL][24] ([i915#70])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-kbl6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#72])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@all-pipes-single-move:
- shard-hsw: [PASS][27] -> [INCOMPLETE][28] ([i915#61])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-hsw7/igt@kms_cursor_legacy@all-pipes-single-move.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-hsw8/igt@kms_cursor_legacy@all-pipes-single-move.html
* igt@kms_fbcon_fbt@fbc:
- shard-tglb: [PASS][29] -> [FAIL][30] ([i915#64])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-tglb2/igt@kms_fbcon_fbt@fbc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-tglb6/igt@kms_fbcon_fbt@fbc.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-tglb: [PASS][31] -> [SKIP][32] ([i915#668]) +7 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#49])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][35] -> [INCOMPLETE][36] ([i915#123] / [i915#69])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#180] / [i915#95])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
#### Possible fixes ####
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][41] ([i915#180] / [i915#95]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1}:
- shard-apl: [FAIL][43] ([i915#79]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* {igt@kms_flip@flip-vs-expired-vblank@b-edp1}:
- shard-skl: [FAIL][45] ([i915#79]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* {igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1}:
- shard-skl: [FAIL][47] ([i915#34]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
- shard-skl: [FAIL][49] ([i915#49]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl9/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl2/igt@kms_hdr@bpc-switch.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl4/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-hsw: [FAIL][57] ([i915#1542]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-hsw8/igt@perf@blocking-parameterized.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-hsw1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [SKIP][59] ([i915#468]) -> [SKIP][60] ([i915#668])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][61] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][62] ([i915#1319])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl1/igt@kms_content_protection@atomic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [TIMEOUT][63] ([i915#1319]) -> [FAIL][64] ([fdo#110321] / [fdo#110336])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl7/igt@kms_content_protection@atomic-dpms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-kbl: [TIMEOUT][65] ([i915#1319]) -> [FAIL][66] ([fdo#110321] / [i915#93] / [i915#95])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl4/igt@kms_content_protection@lic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/shard-kbl1/igt@kms_content_protection@lic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8430 -> Patchwork_17584
CI-20190529: 20190529
CI_DRM_8430: 2daa6f8cad645f49a898158190a20a893b4aabe3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5632: e630cb8cd2ec01d6d5358eb2a3f6ea70498b8183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17584: 7e5f8efa9a8d423a289def24f06bd53489a08ad2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17584/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency
2020-05-04 13:50 ` [Intel-gfx] " Chris Wilson
@ 2020-05-06 23:42 ` Sasha Levin
-1 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-05-06 23:42 UTC (permalink / raw)
To: Sasha Levin, Chris Wilson, intel-gfx
Cc: tvrtko.ursulin, lionel.g.landwerlin, Tvrtko Ursulin, stable
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: c81471f5e95c ("drm/i915: Copy across scheduler behaviour flags across submit fences").
The bot has tested the following trees: v5.6.10.
v5.6.10: Failed to apply! Possible dependencies:
8e9f84cf5cac ("drm/i915/gt: Propagate change in error status to children on unhold")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency
@ 2020-05-06 23:42 ` Sasha Levin
0 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-05-06 23:42 UTC (permalink / raw)
To: Sasha Levin, Chris Wilson, intel-gfx; +Cc: stable
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: c81471f5e95c ("drm/i915: Copy across scheduler behaviour flags across submit fences").
The bot has tested the following trees: v5.6.10.
v5.6.10: Failed to apply! Possible dependencies:
8e9f84cf5cac ("drm/i915/gt: Propagate change in error status to children on unhold")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2020-05-06 23:42 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-04 13:50 [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
2020-05-04 13:50 ` [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] " Chris Wilson
2020-05-06 23:42 ` Sasha Levin
2020-05-06 23:42 ` [Intel-gfx] " Sasha Levin
2020-05-04 13:50 ` [Intel-gfx] [PATCH 2/6] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 3/6] drm/syncobj: Allow use of dma-fence-proxy Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
2020-05-05 13:48 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-05-05 13:53 ` Chris Wilson
2020-05-05 15:02 ` Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 5/6] drm/i915/gem: Allow combining submit-fences with syncobj Chris Wilson
2020-05-04 13:50 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
2020-05-04 13:54 ` [Intel-gfx] Wait-for-submit on future syncobj Chris Wilson
2020-05-04 14:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency Patchwork
2020-05-04 15:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-05-05 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency (rev3) Patchwork
2020-05-05 16:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-06 4:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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